JP4625798B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor chip and a semiconductor package that perform information processing using high-speed signals.

In recent years, with the increase in operating frequency of semiconductor integrated circuits, semiconductor devices are required to operate at high speed. As the signal speed increases, the signal slew rate increases, and the waveform quality deteriorates due to simultaneous switching noise, crosstalk, and reflection. There is differential transmission as a method for improving signal quality. However, this requires two signal wirings and is expensive, so in the Data I / O system of a system that is desired to be inexpensive such as a DRAM. Single-ended is the mainstream. In a single-ended receiver circuit, the reference voltage (Vref) is used as a reference potential for logic determination. In this case, unlike differential transmission, common mode noise occurs in Vref and signals, so it is difficult to ensure a noise margin. As a method for solving this problem, there is Patent Document 1. In Patent Document 1, a threshold conversion circuit is used to give hysteresis to the Vref, thereby increasing the noise margin of the receiving circuit.
JP 2006-60689 A

  However, since the technique disclosed in Patent Document 1 requires a threshold value conversion circuit for each data signal, there is a problem that the cost increases, such as an increase in circuit scale or a large mounting area. The present invention has been made in view of the above, and the above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the semiconductor device of the present invention, a signal is input to one input of a receiver circuit via a first transmission unit (for example, transmission line), and a reference voltage is input to the other input via a second transmission unit (for example, transmission line). An input configuration is provided, and the first transmission unit and the second transmission unit are arranged to be electromagnetically coupled. That is, the input potential difference of the receiver circuit is expanded by inducing a forward crosstalk signal having a polarity opposite to that of the signal of the first transmission unit in the second transmission unit. Alternatively, a backward crosstalk signal having the same polarity as that of the signal of the first transmission unit is induced in the second transmission unit, and a reflected signal having a reverse polarity is generated, thereby expanding the input potential difference of the receiver circuit. It has become.

  By using such a configuration, for example, the noise margin can be expanded without providing a special circuit such as the above-described threshold conversion circuit, and it is possible to realize a reduction in cost, an increase in speed, or an improvement in reliability. Become.

  The first transmission unit and the second transmission unit can be realized by using, for example, wiring on a semiconductor chip or wiring on a package substrate. For example, in the case of a configuration using a backward crosstalk signal, the above-described reflected signal having the reverse polarity can be obtained by connecting a low-pass filter including a resistor and a capacitor to the node on the input side of the reference voltage in the second transmission unit. It is good to generate. Then, for example, in a configuration in which a plurality of receiver circuits are provided and a reference voltage is commonly supplied to them, noise that wraps around from a certain receiver circuit through a common reference voltage wiring can be reduced by this low-pass filter. Moreover, the function of generating the above-described reverse polarity reflected signal by the capacitor in the low-pass filter can also be used.

  To briefly explain the effects obtained by typical inventions among the inventions disclosed in the present application, it is possible to increase the noise margin at a low cost.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a circuit diagram showing an example of the configuration of the semiconductor device according to the first embodiment of the present invention. The semiconductor device according to the first embodiment includes a semiconductor chip (hereinafter abbreviated as a chip) 1, and an input circuit IBUF1 that transmits a signal input from an external terminal (node) 10 and makes a logic determination is included in the chip 1. include. Although not shown, the chip 1 includes various functional blocks such as a desired logic circuit and / or a memory circuit, and these circuits perform a desired operation upon receiving the output of the input circuit IBUF1. .

  A data signal DQ is input to the external terminal 10, and this signal is transmitted to the receiver 6 via the chip 1 internal wiring. The input data signal DQ is matched and terminated by a termination resistor 2 such as ODT (On Die Termination). The termination resistor 2 is connected to a termination voltage (Vtt) via an external terminal (node) 12. The termination resistor 2 is not limited to the external terminal 12 and may be connected to a termination voltage generated in the chip 1.

  The receiver 6 converts the voltage difference between the two nodes into a logical value. One node is connected to the external terminal 10 via the transmission line 3 and the transmission line 7, and the other node is connected to the external terminal (node) 11 via the transmission line 3 and the transmission line 4. The external terminal 11 is supplied with a reference voltage (Vref) that is a constant voltage from outside the chip 1.

  The transmission line 3 is, for example, a coupled line formed by wiring on the chip 1 and includes electromagnetically coupled lines 3a and 3b that are wired in parallel to each other at a close distance. At the node of the transmission line (coupled line) 3, the connection point with the transmission line 7 is called A, the connection point with the receiver 6 is called B and D, and the connection point with the transmission line 4 is called C. In the transmission line 3, when a rectangular pulse signal is applied to one line 3 a of the transmission line 3 by this electromagnetic coupling, crosstalk occurs in the other line 3 b of the transmission line 3. In digital circuits, timing regulation and the like are often defined by signal rise time and fall time. Therefore, the representative frequency is not the operating frequency but Knee Frequency (Fknee). A wavelength λ of a signal transmitted through a line in a medium having a relative dielectric constant εr is expressed as λ = Co / (Fknee · √εr). Here, Co is the speed of light. It is known that when the line length is about 10 times longer than this wavelength λ, a distributed constant circuit can be formed, so that different waveforms are induced with respect to the signal traveling direction. This is called a direction. Cross-talk from the pulse applied to the transmission line 3 toward the point C and the point D (referred to as the rear and the front, respectively) on the other line 3b with respect to the direction in which the one line 3a propagates from the point A to the point B. Is induced. The wave propagating backward is called backward crosstalk, and the wave propagating forward is called forward crosstalk.

  The transmission line 3 has a characteristic impedance (Z0) defined by the voltage-current ratio of the traveling signal, and the propagation delay time between points A and B or point C and D is td0. The transmission line 7 is a wiring having a characteristic impedance approximately equal to the characteristic impedance (Z0) of the transmission line 3, and is designed so that there is no reflection at the point A. On the other hand, the transmission line 4 is designed to have a characteristic impedance (Z1) lower than Z0 of the transmission line 3, and this causes negative reflection at the point C.

  The semiconductor device according to the first embodiment is characterized in that the noise margin is improved by using backward crosstalk and reflection induced on the transmission line 3 using such a configuration.

  FIG. 2 is a waveform diagram showing an example of the operation in the semiconductor device of FIG. 1, and shows waveforms at points A to D when the data signal DQ is applied to the external terminal 10 of the chip 1. In the operation of the semiconductor device in FIG. 1, backward crosstalk and forward crosstalk occur. The waveform diagram of FIG. 2 shows only the waveform change due to backward crosstalk. The data signal DQ has an amplitude V0 based on the reference voltage Vref applied to the external terminal 11. That is, the high level is Vref + V0 / 2, and the low level is Vref−V0 / 2. Since a signal having information is in an AC component and does not depend on a DC component, the signal has only to consider what the signal amplitude V0 will be.

  A signal having a signal amplitude V 0 applied to the external terminal 10 reaches the point A via the transmission line 7. However, since the characteristic impedances of the transmission line 7 and the transmission line 3 are the same, there is no reflection at this portion. However, a voltage waveform of Kb · V0, which is the product of the voltage V0 and the coupling coefficient Kb, is induced at the point C of the coupling line (transmission line) 3. Here, Kb is called a backward crosstalk coefficient, and is known to always take a positive value regardless of the shape.

  This induced backward crosstalk waveform propagates backward in the direction from point D to point C through the coupled line 3. At the point C, the characteristic impedance (Z1) of the transmission line 4 is lower than the characteristic impedance (Z0) of the transmission line 3 as shown in the equation (1), so the reflection coefficient Γ1 (equation (2)) at the point C is It becomes a negative value (formula (3)).

Z1 <Z0 (1)
Γ1 = (Z1−Z0) / (Z1 + Z0) (2)
Γ1 <0 (3)
For this reason, the backward crosstalk transmitted to the point C generates a negative reflection at the point C, and this negative reflected wave travels along the transmission line 3 from the point C to the point D and is input to the receiver 6. It will be. At this time, the voltage at the point D input to the receiver 6 is Γ1 · Kb · V0 and has the opposite sign to V0. Accordingly, since a negative wave propagates at point D with respect to the positive amplitude V0 applied to point A and propagated to point B, as a result, the voltage (Vd) between the two input terminals of the receiver 6 is
Vd = V (B) -V (D)
= V0-Γ1 · Kb · V0
= V0 (1-Γ1 · Kb)> V0 (4)
It becomes. Here, V (B) and V (D) indicate voltages at points B and D, respectively. That is, the signal amplitude of the differential input of the receiver 6 is increased. Therefore, the noise margin is improved.

  FIG. 2 shows the operation described above. First, when a positive pulse waveform (amplitude V0) is propagated at point A, this pulse is transmitted at point B after delay time td0 of transmission line 3. The waveform arrives. On the other hand, along with the propagation of the positive pulse waveform at the point A, a positive backward crosstalk (amplitude Kb · V0) is induced at the point C, and this backward crosstalk is caused by the propagation of the pulse waveform at the point A. It is known that this occurs immediately after the round-trip time of the transmission line (that is, 2td0). This backward crosstalk generates a negative reflection waveform (amplitude | Γ1 · Kb · V0 |) at point C, and this negative reflection waveform reaches point D after td0.

  Therefore, when the first embodiment is not used, the logic determination margin of the receiver 6 is “V0−Vref”, but by using the first embodiment, “V0− (Vref− | Γ1 · Kb · V0”. 2), the logic determination margin is improved by the amount of | Γ1 · Kb · V0 | .Note that although the case where a positive pulse waveform (high level signal) is propagated at point A has been described in FIG. Of course, the same applies to the case where a negative pulse waveform (low level signal) is propagated, in which case a positive reflected waveform (amplitude | Γ1 · Kb · V0 |) is generated at the point C, and the logical determination is made accordingly. Since the forward crosstalk from the line 3a appears at the point D almost simultaneously with the negative reflected wave of the backward crosstalk described above, the voltage waveform at the point D is accurately However, it can be implemented so that the forward crosstalk coefficient Kf is negative, in which case the logic judgment margin is not limited even if the voltage change due to forward crosstalk is taken into account. More and more.

  FIG. 3 is a timing chart showing an operation example when the semiconductor device of FIG. 1 performs a DDR latch operation. In the DDR (Double-data-rate) method, the data signal DQ is latched at the rising edge and falling edge of the clock (CK). Since the pulse width of the backward crosstalk is the round trip time 2td0 of the coupled line 3, it is desirable that this pulse width be longer than (1) the setup / hold time and (2) be within the same data rate. This is because (1) the noise margin can be expanded more reliably by causing a voltage change of Vref between latch timings including setup and hold, and (2) intersymbol interference by being within the same data rate. This is because it can be prevented. Therefore, when the semiconductor device of FIG. 1 is used, it is desirable to design the coupling line 3 and the like so as to satisfy Expression (5).

tS + tH <2td0 <tDQ (5)
Here, tS is a latch setup time, tH is a latch hold time, and tDQ is a data rate time. Further, when the propagation speed of the waveform propagating through the coupled line 3 is vp, the data rate is represented by the frequency fDQ, and the equation (5) is converted into the line length L1 of the coupled line 3, the equation (6) is obtained.

{(TS + tH) · vp / 2} <L1 <vp / (2fDQ) (6)
Note that tL in FIG. 3 indicates the time from the rise of the signal to the latch.

  FIG. 4 is a waveform diagram showing an example of a simulation result using the semiconductor device of FIG. This simulation was performed by adjusting the wiring width, wiring length, and wiring interval of the metal wiring in which the various transmission lines 3, 4, and 7 of the semiconductor device of FIG. 1 were formed on the semiconductor substrate. As shown in FIG. 4, at one end (point B) of the receiver 6 of FIG. 1, a data signal DQ in which a high pulse and a low pulse are alternately shifted around the reference voltage (Vref) propagates. At the other end of 6 (point D), a signal is generated in which a low pulse and a high pulse alternately shift around Vref in the same cycle as DQ. Therefore, it can be seen that the noise margin can be expanded if the latch timing of the data signal DQ is set near the center of each pulse.

  As described above, when the semiconductor device of the first embodiment is used, the input amplitude of the receiver 6 can be increased by providing a simple wiring structure on the chip 1, and the noise margin can be increased. As a result, high speed or high reliability of the semiconductor device can be realized. Further, the circuit for expanding the noise margin is not provided at each terminal as in Patent Document 1 described above, but the noise margin is expanded by the wiring structure, so that the area can be reduced or the cost can be reduced. .

  Here, a description has been given of a configuration example in which a coupled line or the like is formed in a path from the external terminal of the chip to the receiver, but the path for forming the coupled line or the like is not limited to this. For example, in a configuration having a plurality of functional blocks in a chip, such as a microcomputer, it is formed on a wiring path that connects the functional blocks, or a package substrate on which a chip is mounted without being limited to a chip. Alternatively, it can be formed on a printed circuit board on which a packaged semiconductor device is mounted.

  In addition, here, the lines 3a and 3b in FIG. 1 have the same characteristic impedance Z0, but they need only be electromagnetically coupled, and need not necessarily have the same characteristic impedance. Further, the distance between the line 3a and the line 3b is not particularly limited as long as a desired electromagnetic coupling is obtained, but according to the study by the present inventors, for example, the wider wiring width of the lines 3a and 3b Good electromagnetic coupling can be obtained by wiring in parallel at intervals of 4 times or less.

(Embodiment 2)
The semiconductor device of the second embodiment is particularly useful when applied to the case where the transmission line 3 of the first embodiment described above cannot take a sufficient length and the crosstalk pulse width for Vref margin expansion is not sufficient. It is. FIG. 5 is a circuit diagram showing an example of the configuration of the semiconductor device according to the second embodiment of the present invention. Specifically, the semiconductor device according to the second embodiment compensates for the short pulse width by optimizing the arrival timing of the Vref margin expanding crosstalk at the receiver. This will be described based on the waveform.

  Prior to the description of FIG. 5, an outline of the operation of the semiconductor device of the second embodiment will be described using the voltage waveforms of FIG. In FIG. 3, when the crosstalk pulse width 2td0 is sufficiently smaller than the pulse width of the data signal DQ, the crosstalk pulse may be input to the receiver only in the time zone near the rising edge of the data signal DQ. Usually, the latch timing of the data signal DQ by the receiver is often set near the center of the pulse time width of the data signal DQ, so it is desirable that the crosstalk pulse reach the receiver in the time zone near the latch timing. . In order to realize this, it is only necessary to adjust the time so that the center of the crosstalk pulse comes to the latch timing of the receiver (defined after tL time from the rise of data).

  Therefore, in the semiconductor device of FIG. 5, a transmission line 5 is added between the transmission line 3 (line 3b) and the transmission line 4 for generating reflected waves in the semiconductor device of FIG. Note that the transmission line 7 of FIG. 1 is omitted in FIG. 5 because it is not an essential part. The transmission line 5 has the same characteristic impedance Z0 as the line 3b, for example, by making it the same line width as the line 3b. Since the characteristic impedance is the same, no reflection occurs in the transmission line 5, and reflection occurs only after passing through the transmission line 5 and reaching the transmission line 4. Therefore, the backward crosstalk generated in the coupled line 3 reaches the receiver 6 with a delay of the round-trip delay time (2td1) of the transmission line 5 from the rising time of the data signal DQ. A sufficient effect can be obtained even when the above is not sufficient.

  The round trip delay time (2td1) is adjusted based on the previously defined tL. In other words, as a measure of the round trip delay time (2td1), it is within a range satisfying, for example, Expression (7) based on the waveform of FIG. Further, when the waveform propagation speed is vp and converted to the line length L2 of the transmission line 5, the range satisfies the formula (8).

tL-tS <2td1 <tL (7)
{(TL-tS) · vp / 2} <L2 <tL · vp / 2 (8)
As described above, by using the semiconductor device according to the second embodiment, in addition to the various effects described in the first embodiment, a noise margin expansion method using backward crosstalk can be applied to various layout constraints. It can be flexibly applied to existing semiconductor chips. The transmission line 5 may be inserted between the coupling line 3 and the receiver 6 (that is, at the point E) instead of between the coupling line 3 and the transmission line 4 described above. However, in this case, adjustment is made with a one-way delay time rather than a round trip, so that the line length is twice that of the former case. Therefore, it is desirable to provide the transmission line 5 between the coupling line 3 and the transmission line 4 from the viewpoint of area efficiency.

(Embodiment 3)
In the first and second embodiments described above, backward crosstalk is used. However, backward crosstalk has a waveform characteristic that determines the pulse width generated by the coupled wiring length. In a system in which a long wiring length cannot be obtained, it is expected that there will be restrictions on use. Therefore, in the semiconductor device of the third embodiment, an example using forward crosstalk, which is crosstalk propagating in the same direction as the data signal in the coupled line, will be described. In the case of forward crosstalk, the pulse width is almost determined by the rise time of the signal.

  FIG. 6 is a circuit diagram showing an example of the configuration of the semiconductor device according to the third embodiment of the present invention. As in FIG. 1, the semiconductor device of FIG. 6 includes an input circuit IBUF3 connected to the external terminals 10 to 12 and various functional blocks that receive the output of the input circuit IBUF3 and perform desired operations in the semiconductor chip 1b. It is included. A data signal DQ is input to the external terminal 10, and the data signal DQ is transmitted to one end of the receiver 6 through one line 30 a constituting the transmission line (coupled line) 30. A termination resistor 2 is provided between one end of the receiver 6 and the external terminal 12 to which a termination voltage (Vtt) is supplied, and the data signal DQ is matched and terminated by the termination resistor 2.

  A reference voltage (Vref) is supplied to the external terminal 11. This reference voltage (Vref) is transmitted to the other line 30 b constituting the coupled line 30 and the other end of the receiver 6 via the transmission line 50. The lines 30a and 30b constituting the coupled line 30 are formed, for example, by wiring on the chip 1, and are electromagnetically coupled by being parallel-wired at close distances. The characteristic impedance of the coupled line 30 (lines 30a and 30b) is Z0, and the propagation delay time is td0. The transmission line 50 is also formed by wiring on the chip 1, and its characteristic impedance is Z0, which is the same as that of the coupling line 30, and the propagation delay time is td1. Here, one end of the line 30a (external terminal 10 side) is the point E, one end of the receiver 6 (the other end of the transmission line 30a) is the point G, one end of the line 30b (the transmission line 50 side) is the point F, The other end (one end of the transmission line 50) is a point H.

  When forward crosstalk is used, a signal coupled by the coupled line 30 travels in a direction from point F to point H. At the same time, backward crosstalk occurs, but this is not used in the third embodiment. Unlike the first and second embodiments, the reflection point having a different wiring width is not provided on the Vref wiring side, so that the influence on the receiver 6 side need not be considered. When the voltage amplitude of the pulse input to the line 30a is V0, the voltage amplitude of the forward crosstalk induced in the line 30b is Kf · L · V0 / Tr. Here, Kf is a forward crosstalk coefficient, L is a coupled line length, and Tr is a signal rise time. In the receiver 6, since the signal to be input to the Vref side needs to have a voltage opposite to that of the data signal, in the third embodiment, Kf <0 is a condition.

  The pulse width tW of the forward crosstalk is substantially the same as the rise time Tr of the pulse input to the line 30a of the coupled line 30, and the case where Tr is very fast with respect to the signal period is described in the second embodiment. The same situation may occur. In other words, if the crosstalk pulse width is not sufficient, it is possible that the potential of Vref does not swing to a desired polarity at the latch timing of the receiver 6. In such a case, the timing of crosstalk generated on the Vref side may be adjusted based on the same concept as in the second embodiment. This is the transmission line 50 in FIG. 6, and the propagation delay time (td1) of this line is used to match the latch timing.

  FIG. 7 is a waveform diagram showing an example of the operation of the semiconductor device of FIG. When a pulse signal having a positive amplitude V 0 is input to the external terminal 10 (corresponding to the point E) in FIG. 6, the pulse signal reaches the point G after the propagation delay time (td 0) of the coupling line 30. On the other hand, a forward crosstalk having a negative amplitude | Kf · L · V0 / Tr | is generated at the point F. This forward crosstalk reaches point H after the occurrence of further propagation delay time (td1) of transmission line 50. In FIG. 7, for example, when the pulse signal at the point G is latched at a timing near the center thereof, the forward crosstalk is delayed by td1 by the transmission line 50, so that the input voltage amplitude to the receiver 6 at this latch timing. The noise margin can be expanded.

  In addition, as a standard of the propagation delay time (td1) of the transmission line 50, the expression (9) is obtained based on the expression (7) described in the second embodiment. Based on Equation (8), Equation (10) is obtained. That is, while the equations (7) and (8) are adjusted by the round trip time of the transmission line, the equations (9) and (10) are adjusted by the one-way time of the transmission line.

tL-tS <td1 <tL (9)
{(TL-tS) · vp} <L3 <tL · vp (10)
Similarly to the case of FIG. 3, the pulse width tW of the forward crosstalk satisfies the equation (11) where tS is the setup time of the latch, tH is the hold time of the latch, and tDQ is the time of one data rate. Is desirable.

tS + tH <tW <tDQ (11)
As described above, by using the semiconductor device according to the third embodiment, in addition to the various effects described in the first embodiment, a noise margin expansion method using forward crosstalk has various layout constraints. It is possible to flexibly apply to a semiconductor chip.

(Embodiment 4)
The semiconductor device of the fourth embodiment is useful when a plurality of input circuits described in the first to third embodiments are provided and a reference voltage (Vref) is supplied to each input circuit in common. That is, normally, Vref is supplied from one pin in the chip, and is distributed to each receiver to supply power. Therefore, in the case of the first and second embodiments, the generated backward crosstalk noise transmitted wave propagates to other receivers, or in the case of the third embodiment, the reflection of the forward crosstalk noise at the receiver is different. May propagate to other receivers and may have adverse effects.

  In the fourth embodiment, in view of the above, a filter is provided at the Vref wiring branch point in the chip as shown in FIGS. FIG. 8 is a circuit diagram showing a configuration example for each input circuit in the semiconductor device according to the fourth embodiment of the present invention. FIG. 9 is a circuit diagram showing a configuration example including a plurality of input circuits of FIG. The semiconductor device (semiconductor chip 1c) shown in FIG. 8 is provided with a low-pass filter including a resistor 8 and a capacitor 9 between the line 3b and the external terminal 11 to which the reference voltage (Vref) is supplied in the semiconductor device of FIG. It becomes the composition. That is, the external terminal 11 is connected to one end of the resistor 8 through the wiring 14 and the other end of the resistor 8 is connected to the line 3b. A capacitor 9 is provided between the other end of the resistor 8 and the external terminal 13 to which the ground voltage GND is supplied.

  The semiconductor device (semiconductor chip 1d) shown in FIG. 9 has a configuration in which a plurality of input circuits IBUF4 including the low-pass filter shown in FIG. The data signal DQ1 from the external terminal 10a and the reference voltage (Vref) from the external terminal 11 are input to one input circuit IBUF4a, and the data signal DQ2 from the external terminal 10b and the external terminal are input to the other input circuit IBUF4b. The reference voltage (Vref) from 11 is input. Here, the reference voltage (Vref) from the external terminal 11 is connected to the low-pass filter in the IBUF 4 a and the low-pass filter in the IBUF 4 b through the wiring 14. The resistor 8 constituting the low-pass filter is realized by, for example, a diffusion layer formed on the semiconductor substrate, and the capacitor 9 is formed by a junction capacitance of a diode formed on the semiconductor substrate, a gate capacitance of a MOS transistor, or the like. Realized.

  When such a configuration is used, for example, when noise wraps around the wiring 14 from the IBUF 4a in FIG. 9, in the IBUF 4b, the low-pass filter included therein suppresses the propagation of the noise. Noise is not input. Therefore, it is possible to realize a semiconductor device with improved noise margin and high reliability. Since the impedance when viewed from the transmission line 3 side can be lowered by the capacitor 9 connected to the ground voltage GND, the same function as that of the transmission line 4 in FIG. 1 (that is, a function as a negative reflection generation point) is also used. It is also possible. Here, assuming that the backward crosstalk frequency is fb, the impedance Zc of the capacitor 9 is expressed by equation (12).

Zc = 1 / (2π · fb · C) (12)
The reflection coefficient Γ is expressed by equation (13).

Γ = (Zc−Z0) / (Z0 + Zc) (13)
The present invention is for obtaining a noise margin expansion effect of about several to 10%. Therefore, when Γ = −0.1, the capacitance value of the capacitor 9 is C = 11 / (18π · fb · Z0) from the equations (12) and (13). When the resistance value of the resistor 8 is R, the cut-off frequency of the low-pass filter is expressed by Equation (14).

1 / (2π · R · C) (14)
In order to suppress the propagation of backward crosstalk, 1 / (2π · R · C) <fb must be satisfied. Therefore, the resistance value of the resistor 8 is R> 9 · Z0 / 11 from the equation (14) and the capacitance value of the capacitor 9. Here, Γ = −0.1, but it is not limited to this value. By using the capacitor 9 constituting the low-pass filter as a negative reflection generation point, a semiconductor device with high area efficiency can be realized.

  As described above, by using the semiconductor device according to the fourth embodiment, even if the configuration of FIG. 1 is connected in parallel on the semiconductor chip, there is an effect of preventing the wraparound of the crosstalk generated in other coupling lines. Here, the example in which the low-pass filter is applied to the configuration example of FIG. 1 has been described, but it is of course applicable to the configuration example of FIG.

(Embodiment 5)
In the first to fourth embodiments described above, the case where the coupling line or the like is formed in the semiconductor chip has been mainly described. In the fifth embodiment, the case where the coupling line or the like is formed in the semiconductor package will be described. . Here, the configuration in the case of using backward crosstalk as described in the first and second embodiments will be described, but the same may be considered in the case of using forward crosstalk.

  In general, a semiconductor device often uses a low-cost package substrate having a single wiring layer. In this case, the restrictions on the wiring layout in the semiconductor package become very large. The biggest constraint is the number of wires. For example, in the semiconductor package, providing one Vref wiring for each data signal wiring eventually requires the same number of wirings as the differential case, resulting in a high-cost package. Most are unacceptable. In such a system, the Vref noise margin is not increased for all the data signal lines, but the Vref noise margin may be increased by paying attention to, for example, one data wiring. This is the idea of the fifth embodiment, which will be described with reference to FIG.

  FIG. 10 is a schematic diagram showing an example of the configuration of the semiconductor device according to the fifth embodiment of the present invention. Here, description will be made based on the wiring layout of a semiconductor package having four data signal lines. In FIG. 10, chip pads (Chip Pad) which are external terminals on a semiconductor chip, ball bumps (Ball bumps) which are external terminals on a semiconductor package and are composed of a plurality of solder balls 21 and the like, and wiring between them, A package substrate 20 is shown. Such a package substrate 20 is used in a semiconductor package such as a BGA (Ball Grid Array) and a CSP (Chip Size Package). The Ball bump is a place that becomes an electrical / physical contact between the printed circuit board on which the semiconductor package is mounted and the package board, and the Chip Pad is a place that becomes an electrical / physical contact between the semiconductor chip and the package board. It is.

  The Ball bump and the Chip pad are electrically connected by wiring on the package substrate 20. Here, a package substrate having four data wirings (DQ1 to DQ4) is considered, but the number of data wirings may be more or less. The four data wirings are connected by wirings having different lengths for the convenience of the layout of the package substrate. In general, noise superimposed on a data signal is mainly noise due to inductance, and the data wiring having a longer wiring length tends to have a larger noise amount (smaller noise margin).

  Therefore, as shown in FIG. 10, paying attention to the data wiring having the longest wiring length (DQ1 in this case), the Vref wiring is brought close to a part of the section of the data wiring, and the coupling wiring 22 for generating crosstalk (that is, FIG. 10). 1 corresponding to the coupled line 3). Further, a negative reflected wave generating wiring 23 (corresponding to the transmission line 4 in FIG. 1) having a wiring width wider than the coupling wiring 22 on the wiring between the coupling wiring 22 and the Vref Ball bump. ). In general, the characteristic impedance can be lowered as the wiring width is increased. However, in addition to this, for example, the distance from the ground voltage GND surface in the package substrate can be shortened or the wiring thickness can be changed. The characteristic impedance can also be lowered by such as.

  As described above, by using the semiconductor device according to the fifth embodiment, it is possible to realize a noise margin that is considered to have the lowest noise margin among all data at a low cost, and the anti-noise performance when looking over the entire semiconductor device Can be improved. In this case, the noise margin of the data signal combined with Vref can be enlarged, but the noise margin of other data signals may be lowered. However, the noise margin is improved when viewed from the whole semiconductor device. Of course, there is no problem if the timing of the crosstalk signal is shifted by adjusting the timing of other data signals and the wiring length. Here, the noise margin is expanded for one data wiring on the package substrate. However, when a package substrate having a plurality of wiring layers is used, layout constraints on the package substrate are allowed. It is also possible to expand the noise margin for two or more data wirings. Although an example using wiring on a package substrate has been described here, the same thing can be realized by using a wiring layer of a printed circuit board on which a packaged semiconductor device is mounted.

(Embodiment 6)
The semiconductor device according to the sixth embodiment performs signal transmission of a semiconductor chip having a plurality of differential interfaces by single-ended connection. Since the differential interface requires two signal wirings per signal, the occupied area of the signal wiring is increased and the cost is increased as compared with the single end. Therefore, the semiconductor device of the sixth embodiment reduces the occupied area of the signal wiring and improves the cost performance by reducing the signal transmission speed and making the single-ended connection. Specifically, the reference voltage wiring is connected to one input of the differential receiver, and the signal wiring is connected to the other. And a noise margin is ensured by forming the coupling line etc. which were described until now with respect to this reference voltage wiring and signal wiring. The coupled line is formed on a semiconductor package or a printed board.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  The semiconductor device of the present invention is widely applicable to all semiconductor devices that perform desired processing by receiving a high-speed digital signal from the outside, such as a logic circuit device such as a processor or a memory device.

1 is a circuit diagram showing an example of the configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a waveform diagram showing an example of operation in the semiconductor device of FIG. 1. 3 is a timing chart showing an operation example when the semiconductor device of FIG. 1 performs a DDR type latch operation. It is a wave form diagram which shows an example of the simulation result using the semiconductor device of FIG. FIG. 6 is a circuit diagram showing an example of the configuration of a semiconductor device according to a second embodiment of the present invention. FIG. 10 is a circuit diagram showing an example of the configuration of a semiconductor device according to a third embodiment of the present invention. FIG. 7 is a waveform diagram showing an example of operation in the semiconductor device of FIG. 6. In the semiconductor device of Embodiment 4 of this invention, it is a circuit diagram which shows the structural example for every each input circuit. It is a circuit diagram which shows the structural example provided with two or more input circuits of FIG. In the semiconductor device of Embodiment 5 of this invention, it is the schematic which shows an example of the structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1a-1d Semiconductor chip 2 Termination resistor 3,30 Coupling line 3a, 3b, 30a, 30b Line 4, 5, 7, 50 Transmission line 6 Receiver 8 Resistance 9 Capacitor 10-13, 10a, 10b External terminal 14,23 Wiring 20 Package substrate 21 Solder ball 22 Bonding wiring IBUF Input circuit DQ Data signal Vtt Termination voltage Vref Reference voltage CK, / CK Clock signal

Claims (17)

A receiver circuit including a first node and a second node, and performing a logic determination based on a potential difference between the first node and the second node;
A third node to which the first signal is input;
A fourth node to which a reference voltage is supplied;
A first transmission unit configured to transmit the first signal input to the third node to the first node;
A second transmission unit arranged to transmit the reference voltage supplied to the fourth node to the second node and to be electromagnetically coupled to the first transmission unit;
A third transmission unit provided between the second transmission unit and the fourth node and having a characteristic impedance lower than a characteristic impedance of the second transmission unit;
In the second transmission unit, when the first signal is transmitted through the first transmission unit, a second signal having the same polarity as the first signal and traveling toward the third transmission unit is induced,
When the second signal is input to the third transmission unit, a reflected signal having a polarity opposite to that of the second signal is generated, and the reflected signal is transmitted to the fourth node through the second transmission unit. A semiconductor device which is transmitted. The semiconductor device according to claim 1,
Furthermore, a fourth transmission unit having a characteristic impedance equal to the characteristic impedance of the second transmission unit is provided between the second transmission unit and the third transmission unit. The semiconductor device according to claim 2,
The fourth transmission unit is realized by a transmission line,
The line length L2 of the transmission line is such that tS is the setup time required for latching the receiver circuit, tL is the time from the start of transition of the first signal at the first node to the latch, and vp is the signal waveform Assuming transmission speed
A semiconductor device characterized by satisfying “{(tL−tS) · vp / 2} <L2 <tL · vp / 2”. The semiconductor device according to claim 1,
The first transmission unit and the second transmission unit are realized by two transmission lines having the same line length,
The line length L1 is tS is a setup time required for latching the receiver circuit, tH is a hold time required for latching the receiver circuit, vp is a signal waveform transmission rate, and fDQ is a data rate frequency. When
A semiconductor device characterized by satisfying “{(tS + tH) · vp / 2} <L1 <vp / (2fDQ)”. The semiconductor device according to claim 1,
The semiconductor device comprises one semiconductor chip,
The semiconductor device, wherein the first transmission unit and the second transmission unit are realized by wiring on the semiconductor chip. The semiconductor device according to claim 1,
The semiconductor device comprises one semiconductor chip and a package substrate on which the semiconductor chip is mounted,
The semiconductor device, wherein the first transmission unit and the second transmission unit are realized by wiring on the package substrate. The semiconductor device according to claim 1,
The third transmission unit includes:
A resistor connected between a connection node to the second transmission unit and a connection node to the fourth node;
A semiconductor device comprising: a connection node to the second transmission unit; and a capacitor connected between a ground voltage. A receiver circuit including a first node and a second node, and performing a logic determination based on a potential difference between the first node and the second node;
A third node to which the first signal is input;
A fourth node to which a reference voltage is supplied;
A first transmission unit configured to transmit the first signal input to the third node to the first node;
A second transmission unit arranged to transmit the reference voltage supplied to the fourth node to the second node and to be electromagnetically coupled to the first transmission unit;
In the second transmission unit, when the first signal is transmitted through the first transmission unit, a second signal having a polarity opposite to that of the first signal and traveling toward the second node is induced. A featured semiconductor device. The semiconductor device according to claim 8.
The pulse width tW of the second signal has tS as a setup time necessary for latching the receiver circuit, tH as a hold time necessary for latching the receiver circuit, and tDQ as a data rate time.
A semiconductor device satisfying “tS + tH <tW <tDQ”. The semiconductor device according to claim 8.
Furthermore, a third transmission unit having a characteristic impedance equal to the characteristic impedance of the second transmission unit is provided between the second transmission unit and the second node. The semiconductor device according to claim 10.
The third transmission unit is realized by a transmission line,
The line length L3 of the transmission line is such that tS is the setup time required for latching the receiver circuit, tL is the time from the start of transition of the first signal at the first node to the latch, and vp is the signal waveform Assuming transmission speed
A semiconductor device characterized by satisfying “{(tL−tS) · vp} <L3 <tL · vp”. The semiconductor device according to claim 8.
The semiconductor device comprises one semiconductor chip,
The semiconductor device, wherein the first transmission unit and the second transmission unit are realized by wiring on the semiconductor chip. The semiconductor device according to claim 8.
The semiconductor device comprises one semiconductor chip and a package substrate on which the semiconductor chip is mounted,
The semiconductor device, wherein the first transmission unit and the second transmission unit are realized by wiring on the package substrate. A first receiver circuit including a first node and a second node, wherein the first receiver circuit performs logic determination based on a potential difference between the first node and the second node;
A second receiver circuit including a third node and a fourth node, and performing a logic determination based on a potential difference between the third node and the fourth node;
A fifth node to which the first signal is input;
A sixth node to which the second signal is input;
A seventh node to which a reference voltage is supplied;
A first transmission unit configured to transmit the first signal input to the fifth node to the first node;
A second transmission unit arranged to be electromagnetically coupled to the first transmission unit;
A third transmission unit for transmitting the second signal input to the sixth node to the third node;
A fourth transmission unit arranged to be electromagnetically coupled to the third transmission unit;
A fifth transmission unit that transmits the reference voltage supplied to the seventh node and includes a first branch node and a second branch node;
A first low-pass filter provided between the first branch node and the second transmission unit;
A second low-pass filter provided between the second branch node and the fourth transmission unit;
The reference voltage supplied to the seventh node is transmitted to the second node through the fifth transmission unit, the first low-pass filter, and the second transmission unit, and the fifth transmission unit and the second transmission unit. Transmitted to the fourth node through a low-pass filter and the fourth transmission unit,
In the second transmission unit, when the first signal is transmitted through the first transmission unit, a third signal having the same polarity as the first signal and traveling toward the first low-pass filter is induced,
In the fourth transmission unit, when the second signal is transmitted through the third transmission unit, a fourth signal having the same polarity as the second signal and traveling toward the second low-pass filter is induced,
The first low-pass filter receives the third signal and generates a first reflected signal having a polarity opposite to that of the third signal,
The second low-pass filter receives the fourth signal and generates a second reflected signal having a polarity opposite to that of the fourth signal. The semiconductor device according to claim 14.
The first low-pass filter is
A first resistor connected between the first branch node and the second transmission unit;
A first capacitor connected between a connection node on the second transmission side of the first resistor and a ground voltage;
The second low-pass filter is
A second resistor connected between the second branch node and the fourth transmission unit;
A semiconductor device comprising: a second capacitor connected between a connection node of the second resistor on the four transmission side and a ground voltage. The semiconductor device according to claim 15, wherein
The semiconductor device comprises one semiconductor chip,
The semiconductor device according to claim 1, wherein the first to fifth transmission units are realized by wiring on the semiconductor chip. The semiconductor device according to claim 1,
The semiconductor device, wherein the first transmission unit and the second transmission unit are realized by wiring on a semiconductor package.

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