JPH06152253A - Frequency multiplier - Google Patents

Abstract

PURPOSE:To secure the long-time reliability of an FET without damaging the multiplication efficiency by generating a detection voltage in accordance with an input signal level higher than a threshold and superposing it on a gate bias voltage to suppress the gate current. CONSTITUTION:The input signal is inputted to not only a detector D1 through a coupler 21 but also the gate of an PET 12 through a matching device 11. The detector D1 outputs a detection voltage -V corresponding to the difference between the applied signal level and a threshold -V3 to a resistance R2, and it is superposed on an external bias voltage -V4 and is applied to the gate of the FET 12 through the matching device 11. Consequently, when the input signal level is excessive, the gate bias voltage of the FET 12 is made deeper to change the linear operation direction of the FET, and flow of the gate current is suppressed. Thus, the long-time reliability of the FET is secured without damaging the multiplication efficiency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency multiplier used in a wireless communication system, for example.

Generally, when a signal with high stability and high frequency is required, the output of an oscillator with low frequency but high stability is multiplied by a frequency multiplier to obtain a signal of a desired frequency. As the multiplication element, a three-terminal element such as a GaAs FET or HEMT is used in addition to a two-terminal element such as a varactor diode or a step recovery diode which has been conventionally used.

Since the three-terminal element has characteristics that the two-terminal element does not have, such as having an amplifying function and a certain degree of isolation between input and output, recently, instead of the two-terminal element, various frequencies have been used. It is used in obi.

Therefore, as a FET, which is a three-terminal element,
It is necessary to ensure long-term reliability without degrading the multiplication efficiency.

[0005]

2. Description of the Related Art FIG. 3 is a configuration diagram of a conventional example, FIG. 4 is an operation explanatory diagram of FIG. 3, (a) is a V _GS -I _DS characteristic diagram of an FET, (b) is an input level vs. gate current characteristic diagram Is.

The operation of FIG. 3 will be described below with reference to FIG. 4, but the multiplication order is 2. First, the gate of FET 12 has a bias voltage (−V ₁ ) of resistance R ₁ and high frequency choke c.
h ₁ is a high-frequency choke applied to the input side matching part 11 and has a voltage V ₂ at the drain ch ₂ , a filter / matching part consisting of an output side matching part and a filter part for extracting the second harmonic.
It has been added through 13.

Now, for example, when a signal of 10 GHz is applied to the gate of the FET via the terminal IN, the capacitor C ₁ and the input side matching portion 11, the nonlinear characteristics of V _GS -I _DS shown in FIG. The distortion signal appears on the drain side. Then, after extracting the 20 GHz component from the distortion signal in the filter part, it is taken out from the terminal OUT via the output side matching part and the capacitor C ₂ .

Here, in order to efficiently perform frequency multiplication, it is necessary to generate a larger distortion signal in the FET, so the gate bias voltage of the FET is usually 0 V or the pinch-off voltage (V at the point where I _DS is 0). It is set near _GS ).

[0009]

[Fig. 4 (a)] is a FET
Shows the static characteristics of gate voltage versus drain current, between the gate and source of the FET, is superimposed voltage by the high-frequency signal input to the gate bias voltage supplied from the outside (-V ₁₎ from terminal IN Join.

Now, when the gate bias voltage is near 0, -V ₁
When the input level is low, the peak value of the gate voltage does not exceed 0V and there is no particular problem, but when the input level increases and the peak value exceeds 0V (Fig. 4).
In (a), the voltage applied to the gate is positive with respect to the source, and a gate current flows from the gate to the source.

This gate current is a forward current when the gate-source is regarded as a diode, and once the gate current flows, the gate current rapidly increases due to a slight increase in the input level. As a result, the FET deteriorates, so it is necessary to suppress this gate current. One of the methods is to insert a resistor R ₁ in the gate bias circuit as shown in FIG. As shown in, the increase in the gate current is suppressed by increasing the resistance value, but it cannot be completely suppressed.

That is, since it is impossible to completely suppress the gate current, it is difficult to secure the long-term reliability of the FET. An object of the present invention is to make it possible to ensure long-term reliability of a FET.

[0013]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 2 indicates that when the level of the input signal is equal to or higher than the threshold value, the detection voltage of a predetermined polarity corresponding to the difference between the level of the input signal and the threshold value is output, but the level of the input signal is equal to or lower than the threshold value When, the detection part that does not output the detection voltage, 3
Is a superimposing portion for superimposing the applied external bias voltage of the predetermined polarity and the detection voltage and sending the superposed voltage as the bias voltage, and 12 is a field effect transistor.

[0014]

According to the present invention, when the level of the input signal is equal to or higher than the threshold value in the detection portion, a detection voltage of a predetermined polarity corresponding to (input signal level-threshold value) is generated and sent to the superposition portion.
Since the gate bias voltage from the outside is also applied to the superposed portion, the voltage obtained by superposing the detection voltage of the same polarity on the gate bias voltage is applied to the gate of the FET as the bias voltage.

As a result, even when the level of the input signal is equal to or higher than the threshold value, that is, even when the input signal is at an excessive level, the long-term reliability of the FET is secured without the gate current flowing.

[0016]

FIG. 2 is a block diagram of an embodiment of the present invention. Where coupler 21, diode D ₁ , capacitors C ₃ , C ₄ , resistance
R ₂ and high frequency choke ch ₃ are the components of the detection part 2 and the resistance.
R ₃ and R ₄ are constituent parts of the overlapping part 3. The same reference numerals denote the same objects throughout the drawings. The operation of FIG. 2 will be described below, but the parts described in detail above will be briefly described, and the part of the present invention will be described in detail.

In the figure, the signal of frequency f ₀ input via the terminal IN is a combiner, a part of which passes through the detector D ₁ and the remaining part of which passes through the capacitor C ₁ and the input side matching portion 11 and the gate of the FET 12. Added to each. The detector D ₁ detects the detected voltage corresponding to the difference between the applied signal voltage and the threshold value (−V ₃ ).
Output (−v) across resistor R ₂ .

Since (-V ₄ ) is applied as the external bias voltage, the detection voltage (-v) is superimposed on the external bias voltage (-V ₄ ) via the resistors R ₄ and R ₃ . A bias voltage − (v + V ₄ ) that is more negatively shifted than the external bias voltage (−V ₄ ) is applied to the FET 12 via the choke ch ₁ and the input side matching section 11.

Therefore, if the detected voltage does not overlap, the condition shown in FIG.
The place where the gate current should flow like the shaded area in (a) shifts to the negative side, so that the flow of the gate current is suppressed.

That is, if the level of the signal applied to the FET increases for some reason, the gate voltage flows and the output of the multiplier also tends to increase. However, as described above, the detection voltage (-v) is superimposed on the external bias voltage (-V ₄ ) and shifts to the more negative side, so the gate current does not flow and the FET changes in the direction of linear operation. Distortion is reduced, and the level fluctuation of the multiplied wave output as the frequency multiplier is suppressed.

As described above, the gate bias voltage can be deepened only when the input high frequency signal becomes excessive, and the reliability of the FET can be secured without impairing the multiplication efficiency.

[0022]

As described in detail above, according to the present invention, it is possible to ensure long-term reliability of the FET.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a configuration diagram of a conventional example.

4 is an operation explanatory diagram of FIG. 3, (a) is a V _GS -I _DS characteristic diagram of the FET, and (b) is an input level-gate current characteristic diagram.

[Explanation of symbols]

 2 Detection part 3 Superposition part 12 Field effect transistor

Claims (1)

[Claims] 1. A frequency multiplier that multiplies an input signal by using a field effect transistor (12) to which a bias voltage is applied and extracts a signal of a desired frequency as an output signal, wherein the level of the input signal is a threshold value. In the above case, a detection voltage of a predetermined polarity corresponding to the difference between the level of the input signal and the threshold value is output, but when the level of the input signal is below the threshold value,
A detection part (2) that does not output a detection voltage, and a superimposition part (3) that superimposes the external bias voltage of the predetermined polarity to be applied and the detection voltage, and sends it as the bias voltage are provided. Frequency multiplier.