JPH06149941A - Substrate design device - Google Patents

Abstract

PURPOSE:To surely detect the errors of design by automatically inspecting a substrate by the substrate designing device itself after the layout of the substrate is designed by the substrate design device. CONSTITUTION:This device is provided with a keyboard 1, main storage part 2, CRT 3 and CPU 4 or the like and the main storage part 2 stores various data at the time of substrate design and a substrate inspection module (c) or the like. The CPU 4 reads the substrate inspection module and the data from the main storage part 2, judges whether plural clearance holes arranged on the substrate are mutually overlapped or not, and classifies the coordinate data of overlapped clearance holes into sets A and B or the like. Next, the CPU 4 reads the coordinate data of the outline of a wiring pattern from the main storage part 2, compares them with the coordinate data of the respective sets A and B and detects the mutual cross position. Corresponding to this detected result, the CPU 4 judges the quality of layout design and displays the result on the display screen of the CRT 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a board designing apparatus for designing a multilayer printed wiring board or the like, which is constructed by laminating a plurality of boards.

[0002]

2. Description of the Related Art When a layout design of a wiring pattern of each layer of a multilayer printed wiring board is carried out by using a board designing apparatus, a design mistake, for example, a disconnection of inner layer wiring due to a via, may occur. It is desired to construct an inspection technique that can inspect all the items.

Now, a conventional board designing apparatus will be described with reference to FIG.

Generally, a multi-layer printed wiring board has a plurality of substrates, for example, two-layer substrates 41 and 42, as shown in FIG.
The wiring patterns 43, 44, and 45 are laminated in three layers. Wiring patterns 43, 44, 45 of each layer
Are connected by vias 46 and 47. The via 47
Is insulated from the wiring pattern 44 in the inner layer. Each wiring pattern 43, 44, 45 is divided into a signal system and a power supply system in each layer, and in particular, the power supply system has a wide area in the inner layer due to the current flow, and in this case, the wiring pattern 44 has an island shape. Often formed.

With the conventional board designing apparatus, for example, the wiring pattern 44 and the vias 46, 4 are formed on the board 42 of the inner layer.
In the case of layout designing 7, wiring patterns 44 are first laid out, and then vias 46 and 47 are laid out.

In this case, the wiring pattern 44 is formed on the substrate 42.
Since a large proportion is occupied, a large number of through holes (via holes) are also arranged in the wiring pattern 44.

By the way, when the via 47 which is not connected to the wiring pattern 44 is provided on the wiring pattern 44, the via 4 is used.
In order to insulate it from the wiring 7, a clearance hole 48 which is one size larger than the diameter of the via hole provided in the wiring pattern 44.
Therefore, the wiring pattern 44 is removed by this amount.

On the other hand, the designer also uses this device to design the layout of the other layers.
If 47 is increased or the layout is changed, the clearance holes 48 of the wiring pattern 44 in the inner layer are overlapped and connected due to a layout error, and the wiring pattern 44 is connected.
May be divided.

Therefore, when the layout design by the board design device is completed, the designer must inspect the completed pattern diagram.

However, this inspection is performed visually by checking the positions of the vias 46 and 47 in the upper and lower layers with the outlines of the wiring pattern 44 in the inner layer and the positions of the clearance holes 48 and the like and visually checking all the details. It takes a lot of time to do so. In such visual inspections, sometimes design mistakes cannot be discovered and may be leaked. It is only after actually creating a multilayer printed wiring board that it is discovered, for example, that the inner layer wiring pattern is divided. It may be done.

[0011]

As described above, in the conventional board designing apparatus, there is a problem that it is necessary to visually inspect the completed pattern diagram, the inspection takes time, and there is a possibility that the inspection may be missed. .

The present invention has been made to solve the above problems, and an object of the present invention is to provide a board design apparatus capable of reliably detecting a design error in a board after layout design in a short time.

[0013]

In order to achieve the above-mentioned object, the board designing apparatus of the present invention provides coordinate data of outlines of wiring patterns provided on the board and coordinate data of center points of a plurality of via holes. A data storage unit in which data of the size of the radius of the clearance portion for insulating the wiring pattern from each of the via holes is stored, respectively,
A means for determining whether the center points of the via holes and the radius size of the clearance portion are read from the data storage unit and determining whether or not the clearance portions overlap each other, and a determination result of the determination means. Based on
A classifying unit that classifies the overlapping clearance sections for each group, and coordinate data of the outline of the wiring pattern is read from the data storage section and compared with the data indicating the group of each classified clearance section to cross each other. And a notifying means for notifying that the wiring pattern is divided based on the detection result of the detecting means. Further, the classification means of this board designing device, based on the determination result of the determination means, means for setting a table for each collection of overlapping clearance portions, and the via hole corresponding to each clearance portion in the set table. And means for assigning an identifier.

Further, the notifying means of this board design apparatus is
Based on the detection result of the detection means, when an intersection with the wiring pattern is detected in a collection of certain clearance parts, a corresponding via hole is obtained from the position of each intersection, and the identifier of the wiring pattern is given to the via hole in the table. It has an allocating means and a means for notifying that the wiring pattern is divided when the same wiring pattern identifier is allocated to two or more different via holes in the table by the allocating means.

[0015]

According to the present invention, when the clearance portions provided on the substrate overlap, a table is set for each collection of the overlapping clearance portions, and the identifier of the via hole corresponding to the overlapping clearance portion is set in each table. Allocate. Then, the coordinate data of the outline of the wiring pattern provided on the substrate is compared with the coordinate data of the outline of the clearance portion that overlaps, and the coordinate data at which the outlines intersect each other are detected. When an intersection exists in a certain clearance group, a corresponding via hole is obtained from the position of the intersection, and a wiring pattern identifier is assigned to the via hole in the table. As a result,
When the same wiring pattern identifier corresponds to two or more different via holes in the table, it is notified that the wiring pattern is divided.

That is, after the board layout is designed by using the board design device, the board can be automatically inspected by using each data stored in the data storage unit at that time, resulting in a design error. For example, it becomes possible to reliably detect the disconnection of the wiring pattern due to the defective placement of the via holes in a short time.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a hardware configuration of a board designing apparatus according to an embodiment of the present invention, and FIG. 2 is a view showing an inner layer board of a multilayer printed wiring board designed using the board designing apparatus of FIG. is there.

In FIG. 1, reference numeral 1 is an input unit such as a keyboard and a mouse. 2 is various data on the board design, for example, coordinate data of the outline of the wiring pattern, data of the radius of the clearance portion provided in each wiring pattern, coordinate data of the center points of a plurality of via holes, and the board design. The main storage unit is a data storage unit that stores software such as modules and board inspection modules. Reference numeral 3 is an output unit such as a CRT and a printer. Reference numeral 4 denotes a CPU that performs writing and reading processing of data, software, and the like to the main storage unit 2 through a bus, and controls the above-mentioned units based on the software read from the main storage unit 2 to execute various processes. .

When a multilayer printed wiring board is designed using this board designing device, when the keyboard 1 is operated in a predetermined manner, the CPU 4 reads the board designing module from the main memory 2 and executes the processing operation of this module. Then, a processing screen for board design appears on the CRT 3 and the board can be designed. In this case, the substrate layout can be performed for each layer.

In this embodiment, as shown in FIG. 2, a case where the layout design of the substrate 21 located in the inner layer is performed will be described.

As shown in the figure, first, the keyboard 1 is operated to lay out the inner layer substrate 21 on the display screen of the CRT 3 by drawing a contour line at an arbitrary position on the display screen. The outline of the wiring pattern of the power supply system, for example, the outline of the wiring pattern 22 that supplies + 3V is substantially square inside the wiring pattern 23, and the wiring pattern 23 that supplies + 5V is provided so as to avoid the wiring pattern 22 of + 3V. Draw the outlines of each island independently. In addition, a through hole that is insulated from each of the wiring patterns 22 and 23, that is, a via hole 24 for providing a via that is not connected to the wiring patterns 22 and 23 is drawn with a predetermined radius, and the via hole 24 is arranged on the wiring patterns 22 and 23. In this case, a clearance portion (hereinafter referred to as a clearance hole) 25 that is concentric with the via hole 24 is formed at a predetermined radius in the via hole 2
I drew one size larger than 4, and finished the layout design.

In this embodiment, a large number of via holes 24a to 24h and clearance holes 25 are provided on the wiring pattern 23 side.
And the via holes 24a, 24b, 24
The layout design example in which the wiring pattern 22 is divided by a clearance hole 25 concentric with c, 24d, and 24g is shown.

The data of the wiring patterns 22 and 23, the layout of which is designed in this way, the plurality of via holes 24a to 24h, the clearance hole 25, and the like are stored in the CPU 4
Are respectively stored in predetermined areas in the main storage unit 2.
In addition, the coordinate data of the outlines of the wiring patterns 22 and 23,
In the coordinate data of the center points of the via holes 24a to 24h, an identification code for individually reading the coordinate data,
For example, the wiring patterns 22 and 23 are assigned identification codes “a” and “b”, respectively, and the via holes 24a to 24h are assigned identification codes “to” and the like, and then stored in the main storage unit 2.

In this board designing apparatus, the wiring patterns of the upper and lower boards are also subjected to the layout design by repeating the above-described operation, and the data is stored in the main memory 2.

The operation of the board inspection by the board designing apparatus will be described below.

When the layout design of the board is completed,
First, when the keyboard 1 is operated in a predetermined manner to inspect the board, the CPU 4 reads out the board inspecting module from the main storage unit 2, and the display screen of the CRT 3 is ready for the board inspecting process. In this case, since the inspection can be performed for each layer, when the keyboard 1 is operated to perform a start operation for performing an inspection on the substrate 21 of the inner layer, for example,
As shown in the flowchart of FIG. 3, the CPU 4 executes the inspection process of the substrate 21.

In this case, first, the CPU 4 reads the coordinate data of the center points of the via holes 24a to 24h and the radius size data of the clearance hole 25 from the main memory 2 (step 301). And
The size of each clearance hole 25 is calculated (step 302), and it is determined whether or not the clearance holes 25 overlap each other (step 303). The overlap determination at this time is performed by, for example, two adjacent via holes 24.
Distance between center points a to 24h (calculated from each coordinate data)
Is shorter than the diameter of each clearance hole 25 concentric with them (calculated by doubling the radius).

As a result of this determination, as shown in FIG. 4, a table is set for each collection of only the clearance holes 25 that overlap in the work area of the main memory 2 (step 304).
), The identification code of the via hole concentric with the overlapping clearance hole 25 is assigned to each table. In this embodiment, the identification code of the via hole 24h is eliminated by this determination, and the remaining identification code """"
Of the """""""""", one table X to which the identification code """""""""" is assigned is set, and another identification code ""
One table Y to which "" is assigned is set.
By allocating the identification code to each table in this way, as shown in FIG. 5, the overlapping clearance holes 25 are classified into a group A and a group B in which the respective outlines are connected (step 305). ), Multiple clearance holes 25 for each group A, B
The coordinate data of can be compared.

Next, from the main memory 2 to each wiring pattern 2
The coordinate data of the outlines 2 and 23 are read by the CPU 4 (step 306). Then, the coordinate data of each outline is sequentially compared with the coordinate data of the above-mentioned groups A and B, and when the coordinate data match each other, the position where the outline intersects each other is detected (step 307). .

As a result of this detection, a certain clearance hole 2
If there is an intersection in the group of 5 (step 308),
A corresponding via hole is obtained from each coordinate data, and the table X to which this via hole is assigned,
The identification codes of the compared wiring patterns 22 and 23 are assigned to Y in correspondence with the identification codes of the via holes 24a to 24g in the respective tables X and Y.

In this embodiment, since the two wiring patterns 22 and 23 are provided on the substrate 21, the coordinate data of the wiring pattern 22 is first read by the CPU 4,
The wiring pattern 2 is compared with the coordinate data of the gathering A.
Since the via hole is not provided in No. 2, there is no intersecting coordinate data, and the identification code "b" of the wiring pattern 22 is not assigned to each table X, Y. continue,
The coordinate data of the wiring pattern 22 is compared with the coordinate data of the group B, but not allocated in the same manner as above.

Next, the coordinate data of the wiring pattern 23 is read out and compared with the coordinate data of the group A. As a result of this comparison, there are four intersection coordinates, the clearance hole 25 is detected based on these coordinate data, and the identification code of the via hole concentric with the clearance hole 25, here, the via hole 24a in the table X shown in FIG. Identification code "" and the identification code "" of the via hole 24g
The identification code “a” of the wiring pattern 23 is assigned to.

Subsequently, the coordinate data of the wiring pattern 23 is compared with the coordinate data of the group B. In this result, there is no intersection coordinate and nothing is assigned to the tables X and Y.

Finally, in each of the tables X and Y, when the identification code of the same wiring pattern is assigned to the identification codes of two or more different via holes, the CPU 4 informs that the wiring pattern 23 is divided. (Step 309).

That is, in Table X, since the identification code "a" of the wiring pattern 23 corresponds to the identification code "" of the via hole 24a and the identification code "" of the via hole 24g, the wiring pattern 2
The fact that 3 is divided is displayed on the display screen of the CRT 3. As for this notification method, the area on the display screen where the wiring pattern 23 is divided may be colored so as to indicate a defect, and the identification code of the via holes 24a and 24g intersecting with the outline of the wiring pattern 23 is """ Is C
It may be displayed on RT3.

On the other hand, if there is no overlap between the clearance holes 25 in the judgment of step 303,
In the judgment of 308, if the outlines of the wiring pattern 23 intersect only in the same clearance hole 25, the CPU 4 displays on the display screen of the CRT 3 in a predetermined format that there is no problem in the design of the board. (Step 310).

As described above, according to the board designing apparatus of this embodiment, after the layout of the board 21 is designed, the input section 1 is operated in a predetermined manner so that the board 21 is inspected.
Since it is possible to have the board design apparatus itself perform the processing based on various data stored in, the inspection time can be drastically shortened as compared with the visual inspection by the designer.

Further, there is a design mistake of the substrate 21, for example, a layout mistake of the via holes 24a to 24h and the wiring patterns 22 and 23. As in this example, clearance holes concentric with the via holes 24a, 24b, 24c, 24d and 24g. 25, it is possible to reliably detect that the wiring pattern 23 is divided.

This board inspection module can be modified so that if the outline of a collection of overlapping clearance holes and the outline of a wiring pattern intersect at even one place, it is considered defective.

[0041]

As described above, according to the board designing apparatus of the present invention, after the layout design of the board, the board can be automatically inspected by using various data stored in the data storage unit. The mistake can be detected reliably in a short time.

[Brief description of drawings]

FIG. 1 is a diagram showing a hardware configuration of a board designing apparatus according to an embodiment of the present invention.

FIG. 2 is a plan view showing a board designed by the board designing apparatus of FIG.

FIG. 3 is a flowchart showing an inspection operation of the board designing apparatus in this embodiment.

FIG. 4 is a table set in a main storage unit of the board design apparatus in this embodiment.

FIG. 5 is a diagram showing an example of a contour line comparing operation of the board designing apparatus in this embodiment.

FIG. 6 is a cross-sectional view of a general multilayer printed circuit board.

[Explanation of symbols]

1 ... Keyboard, 2 ... Main memory, 3 ... CRT, 4 ... CP
U, 21 ... Substrate, 22, 23 ... Wiring pattern, 24a ...
24h ... via hole, 25 ... clearance hole.

Claims (3)

[Claims] 1. The coordinate data of the outline of a wiring pattern provided on a substrate, the coordinate data of the center points of a plurality of via holes, and the size of the radius of a clearance portion for insulating the wiring pattern from each of the via holes. The data storage unit that stores the data and the respective data of the size of the radius of the center point of each of the via holes and the clearance unit are read from the data storage unit, and it is determined whether or not the clearance units overlap each other. Determining means, a classifying means for classifying the overlapping clearance portions for each group based on the determination result of the determining means, and reading the coordinate data of the outline of the wiring pattern from the data storage section, and classifying each of the above. Means for detecting the intersections of the clearances by comparing with the data indicating the collection of the clearance portions, and Based on the results, the substrate design apparatus characterized by comprising a notification means for notifying that the wiring pattern is divided. 2. The board design apparatus according to claim 1, wherein the classifying unit sets a table for each set of overlapping clearance portions based on the determination result of the determining unit, and sets the table. And a means for allocating the identifier of the via hole corresponding to each clearance portion. 3. The board design apparatus according to claim 2, wherein when the notifying unit detects an intersection with the wiring pattern in a set of clearances based on the detection result of the detecting unit, A means for allocating the corresponding via hole from the position and allocating the identifier of the wiring pattern to the via hole in the table, and the case where the allocating means allocates the same wiring pattern identifier to two or more different via holes in the table, A board designing device comprising: means for notifying that the wiring pattern is divided.