JPH06149930A - Logic circuit replacement propriety judging method and technology mapping device - Google Patents

Abstract

PURPOSE:To provide the logic circuit replacement propriety judging method and the technology mapping device using the same so that the propriety of replacement can be judged at high speed and even a composite library cell composed of plural gate circuits can be efficiently replaced as well. CONSTITUTION:An encoding prime factor is allocated for each basic gate circuit, code values are respectively calculated as the products of encoding prime factors concerning the partial logic circuits of tree structure which does not branch any output in the middle, and the circuit replacement propriety is judged from the integral dividing relation between both of these code values. On the other hand, the desired logic circuit is inputted from a logic circuit information input/ output part 1, this is divided into partial logic circuits by a partial circuit extraction part 2, the library cell enabling the replacement of this partial logic circuit is selected by a cell selection part 3, further, the selected cell is made suitable by a cell suiting part 4, and the divided logic circuits are reconstituted by a circuit reconstitution part 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic layout design method for a semiconductor integrated circuit, which is a method for determining whether or not a desired logic circuit can be replaced with a logic function block prepared in advance. , And a technology mapping device based on this determination method.

[0002]

2. Description of the Related Art In semiconductor integrated circuits, it has been emphasized that the development cost and the development period are shortened in response to the recent demand for a wide variety of small quantities. Various logic function blocks prepared by dividing the circuit (hereafter called library cells)
, And various layout design methods such as a standard cell method and a gate array method of wiring between these library cells have been put to practical use. Further, various technology mapping methods have been proposed as a method for automatically and efficiently allocating desired logic circuits to library cells.

As one of conventional technology mapping methods, the input / output relationship in a logic circuit, that is, a logic function is expressed by a bit string such as a cube, outputs are calculated for all possible input combinations, and this is calculated as desired. There is a method of determining whether or not mapping is possible by comparing the logic circuit and the library cell. Another example of the technology mapping method is a method of simply comparing each basic gate circuit forming a logic circuit without considering the logic function.

[0004]

In such a conventional technology mapping method, the former is to calculate the outputs of all the input combinations and compare the results. As the number of logic increases exponentially, the processing time becomes enormous, which is not practical as a technology mapping method for a particularly large logic circuit. The latter is
Since the comparison is simply performed for each basic gate circuit, the tree structure matching is required as the comparison process, so the processing time is relatively long, and even if the library cell can realize a desired logic circuit, the logic function However, there is a problem in that mapping (assignment) fails due to a difference in the configuration such as the number of inputs of the gate circuit, which is determined as a mismatch.

The present invention is intended to solve such a problem, and it is possible to determine whether or not replacement is possible at high speed, and whether or not replacement is possible for a logic circuit that can efficiently replace even a complex library cell composed of a plurality of gate circuits. It is an object to provide a determination method and a technology mapping device using the determination method.

[0006]

In order to achieve such an object, a method for determining whether or not a logic circuit can be replaced according to the present invention is
A prime number or a prime number and -1 are assigned as coding prime factors for each of various basic gate circuits such as ND, OR, and NOT.
A code value as a product of the coding prime factors is calculated for each of the first and second partial logic circuits of the tree structure configured from these gate circuits and the output of the gate circuit in the middle does not branch, and the first and second partial logic circuits are calculated according to the division relation of these two code values. Whether or not circuit replacement is possible between the first and second partial logic circuits is determined. Also, when a partial logic circuit is expressed by a logical function, the one represented by the sum of terms consisting of the product of the logical variables is the product-sum system, and the one represented by the product of the terms consisting of the sum of the logical variables is the sum-product As a system, at least a coding sum factor for each product gate system or a sum product system is assigned to each basic gate circuit, and a code value is calculated based on a coding prime factor corresponding to each system into which both partial logic circuits are classified. To do.

Further, as the technology mapping device of the present invention, means for dividing a desired logic circuit into a partial logic circuit according to claim 1 or a partial logic circuit classified into each system according to claim 2, and the above-mentioned logic circuit. Cell selection means for selecting a library cell in which the partial logic circuit can be replaced based on the replacement possibility determination method, and the quotient of the division in the logic circuit replacement availability determination method are decomposed into prime factors, and predetermined adaptation processing is performed based on each prime factor. It is provided with a cell adapting means for performing and a circuit reconfiguring means for reconfiguring the divided and replaced partial logic circuits as desired logic circuits. Further, as the cell selection means, a code value is calculated in advance for each library cell based on the above-mentioned logic circuit replacement possibility determination method, and a library cell having a code value equal to or greater than the code value of the partial logic circuit is selected. On the other hand, a cell selection unit is provided for performing replacement possibility determination in order from the smallest code value, and selecting the library cell first determined to be replaceable.

[0008]

Therefore, the code value is calculated for each of the partial logic circuits to be compared based on the prime factor table, and the division is performed between both code values. As a result, when the division is performed, it is determined that the two partial logic circuits can be replaced. Also,
The partial logic circuits are classified into each system according to their connection form, and the code value is calculated according to the prime factor table based on that system. Further, the input desired logic circuit is divided into partial logic circuits, a replaceable library cell is selected for each partial logic circuit, and the selected cells are subjected to adaptation processing to obtain the desired logic circuit. Reconfigured into. Further, replacement possibility determination is performed in ascending order for library cells having a code value equal to or greater than the code value of the partial logic circuit.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a technology mapping device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 is a logic circuit information input / output unit for inputting information about a desired logic circuit, and 2 is a portion for dividing the logic circuit input by the logic circuit information input / output unit 1 into partial logic circuits not including branch outputs. The circuit extracting unit 3 is a cell selecting unit that selects a library cell corresponding to the partial logic circuit extracted by the partial circuit extracting unit 2 based on the logic circuit replacement availability determination. Further, 4 is a cell matching unit that performs a matching process for matching one of the library cells selected by the predetermined cell selecting unit 3 with the partial circuit extracted by the partial circuit extracting unit 2. Is a circuit reconfiguring unit that reconfigures the divided and replaced circuit based on the outputs from the partial circuit extracting unit 2, the cell selecting unit 3, and the cell adapting unit 4, and outputs the mapping result for a desired logic circuit.

Further, 6 is a library information input section for inputting logic circuit information of a library cell prepared in advance, 7
Is a product-sum system prime factor table showing the correspondence between each basic logic gate circuit in the product-sum system and the coding prime factor, and 8 is a sum-product system prime factor table showing the correspondence between each basic logic gate circuit in the sum-product system and the prime factors . Further, 9 is a product-sum system library code value table in which each library cell input from the library information input unit 6 is represented as a product of prime factors based on the product-sum system prime factor table 7.
Reference numeral 0 is an addition product library code value table in which each library cell input from the library information input unit 6 is represented as a product of prime factors based on the addition product prime factor table 8.

When a logic function value is input from the logic circuit information input / output unit 1 as circuit information indicating a desired logic circuit, the partial circuit extraction unit 2 divides the logic function value into partial logic circuits based on this information. FIG. 2 shows a partial logic circuit divided and extracted from a desired logic circuit by the partial circuit extraction unit 2.
This division processing is performed in order to facilitate selection of library cells in the cell selection unit 3, and each system, for example, AND (logical product) is performed according to the connection form of the basic logic gate circuit that constitutes the partial logic circuit. There are provided classification patterns such as a product-sum system in which the output of the gate is connected to an OR (logical sum) gate, or a sum-product system in which the output of the OR gate is connected to an AND gate. In the above, the system is divided into units that are compatible with these systems and do not include branch outputs to other circuits between the basic logic gate circuits. Information necessary for reconfiguring a desired logic circuit is sent to the circuit reconfiguring unit 5 as the circuit is divided.

The partial logic circuits divided by the partial circuit extracting unit 2 are sent to the cell selecting unit 3 one by one, and the most suitable cell is selected from the library cells input in advance. Below, the product-sum system partial logic circuit of FIG. 2 will be described as the logic circuit replacement availability judgment for this library cell. When the partial circuit extracting unit 2 extracts a product-sum system partial logic circuit in which the outputs of the 3-input AND gate and the 2-input AND gate are input to the 2-input OR gate as shown in FIG. The sign value of the partial logic circuit is calculated with reference to the product-sum system prime factor table 7 shown in FIG.

The product-sum system prime factor table 7 of FIG. 3 shows a product term pattern in a logical function, that is, an AND gate, a gate circuit to be replaced by this AND a prime number or a prime number and "-1" as an encoding prime factor. The partial logic circuit is coded and expressed as a product of these prime factors. In addition, when the output of the output stage gate circuit is a negative logic, “−1” is added to the calculated code value. It is possible to assign other prime numbers,
By assigning "-1", it is possible to easily judge whether or not the partial logic circuit is a negative logic output depending on the presence or absence of- (minus sign) in the code value of the partial logic circuit. The processing speed can be increased.

Therefore, not only is this code value unique to a logic circuit, but the circuit configuration is grasped by factorizing it, and by comparing these prime factors, it is possible to determine whether or not replacement is possible between two logic circuits. Judgment is possible. That is, when the remainder obtained by calculating the code value unique to each logic circuit and dividing the larger code value by the smaller code value is "0", that is, the remainder, the logic circuit having the smaller code value is obtained. Indicates that replacement is possible with a logic circuit having a large code value.

Now, the partial logic circuit shown in FIG. 2 is constituted by a 3-input AND gate and a 2-input AND gate as an input stage, and corresponds to each AND gate from the product-sum system prime factor table 7 of FIG. The prime factors “13” and “5” are referred to, and “13” × is obtained as the code value of this partial logic circuit.
“5” = “65” is calculated. When the input side of each gate circuit forming the partial logic circuit includes a negative logic, for example, when a NOT gate is connected instead of the two-input AND gate in FIG. 2, a code corresponding to the NOT gate "3" is referred to as a prime factor. Further, in the same figure, when there is no 2-input AND gate and one signal is directly input to the 2-input OR gate,
Reference is made to "2" corresponding to simple input.

Next, the code value of the partial logic circuit calculated in this way is sequentially compared with the code value of each library cell prepared in advance, based on the idea of the logic circuit replacement availability judgment based on the aforementioned prime factors. . The logic circuit information of each library cell is input from the library information input unit 6,
After being classified into each system based on the connection form of the logic gate circuit described above, the code value of the library cell, that is, the product of prime factors is calculated with reference to the prime factor tables 7 and 8 of the corresponding system,
It is assumed that the values are stored in advance in the library code value table in the order of code values for each system.

Now, assume that a library cell including a plurality of gate elements is provided as shown in FIG.
In the figure, A to G indicate input terminals and X indicates output terminals. When this library cell is encoded by a logic circuit symbol, a 3-input AND gate and two 2-input AND gates are obtained as shown in the circuit of FIG. , And a 3-input NOR gate that receives the outputs of these AND gates as an input.

In this library cell, a code value "-325" is calculated as a product of "13", "5", "5" and "-1" from the product-sum system prime factor table 7 of FIG. It is assumed that it is stored in the Japanese system code value table 9. Therefore, as the logic circuit replacement availability determination, the code value "-325" of this library cell is calculated from the product-sum system code value table 9.
Is read out and is divided by the code value “65” of the partial logic circuit. The result of the division is “−325” ÷ “65” = “−
5 "and the remainder is" 0 ", that is, it is divided, so that it is determined that the partial logic circuit of FIG. 2 can be replaced by the library cell of FIG. 4, that is, an equivalent logic circuit can be realized by this library cell. .

Here, as the order in which the code values of the library cells stored in the library code value tables 9 and 10 are compared and referred to, reference is made to the library cells having a code value equal to or larger than the absolute value of the calculated code value. As a result, the processing speed in cell selection is further improved, and the efficiency of use of the gate element can be increased by referring to the ascending order of the code value and outputting the first remaining "0" as the selection result. it can. If a prime number (a positive integer) is assigned instead of "-1" as the prime factor corresponding to the negative logic output of the output stage, the absolute value conversion process of the code value is unnecessary. Further, if there is no circuit or replacement candidate whose code value cannot be calculated in the cell selection unit 3 due to overflow or some other reason, it is directly output to the circuit reconfiguration unit 5 as a non-replaceable partial logic circuit.

The library cell selected based on the above logic circuit replacement possibility judgment is subjected to the following adaptation processing in the cell adaptation unit 4. First, it is determined whether or not the adaptation processing is necessary, that is, whether or not the logic circuit configurations of the partial logic circuit and the library cell are the same by comparing the code values of both calculated by the cell selection unit 3. To be done. When the partial logic circuit and the library cell have the same code value, it is determined that the logic circuit configurations of the two are the same, and the adaptation processing is not performed.

If the code values of the two are not equal, it is judged that the adaptation process is necessary, and the quotient obtained by dividing the code value of the library cell by the code value of the partial logic circuit is factored into a prime factor "-". If "1" is included, a NOT gate is added to the output stage as the adaptation processing of the output unit. For other prime factors, the input stage of the gate circuit corresponding to each prime factor is applied with a predetermined logic constant, that is, the power supply voltage or the ground voltage, by referring to the prime factor table of each system as the adaptation process of the input unit. .

Therefore, the quotient obtained by dividing the code value of the library cell of FIG. 5 by the code value of the partial logic circuit of FIG.
25 ”÷“ 65 ”=“ − 5 ”=“ − 1 ”ד 5 ”, the library cell of FIG. 5 has a NOT gate added to the output stage, and one input of the two-input AND gate is grounded. And is adapted to a logic circuit as shown in FIG. A circuit surrounded by a dotted line in the figure shows a library cell, and A to E in the figure correspond to the respective inputs a to e in FIG. 2, and F and G are connected to the ground voltage by the adaptation process, and X
Is also the x output of FIG. 2 via the NOT gate added by the adaptation process.

Further, in the circuit reconfiguring section 5, connection information necessary for circuit reconfiguration from the partial circuit extracting section 2 and the cell selecting section 3
Also, a desired logic circuit is reconfigured according to the library cell replacement / adaptation information from the cell adaptation unit 4, and is output from the logic circuit information input / output unit 1 as a result of technology mapping.

In addition, in the above logic circuit replacement possibility determination method and the technology mapping device using the same,
Although the partial logic circuit of the product-sum system is described as an example, the logical circuit of the product-sum system is similarly implemented based on the product-system prime factor table 8 and the product-system library code value table 10. . Further, if necessary, the product-sum system and the systems other than the sum-product system described in the embodiment can be implemented in the same manner as the embodiment by providing a prime factor table and a library code value table corresponding to the system.

[0025]

As described above, according to the present invention, a prime number or a prime number and "-1" are assigned as encoding prime factors for each basic gate circuit such as AND, OR, and NOT as a logic circuit replacement possibility determination method. In advance, for a partial logic circuit of a tree structure in which the output does not branch in the middle, it is expressed by a code value unique to the logic circuit configuration consisting of products of coding prime factors,
Whether or not replacement is possible is determined based on the division relation of the code values. Further, a product-sum system or a sum-product system is provided as a system based on the connection form of the basic gate circuits of the partial logic circuits, and a prime factor corresponding to the system is set, and based on the prime factors of the system into which the partial logic circuits to be compared are classified. The code value is calculated.

As a technology mapping device,
Divide the desired logic circuit, select a replaceable library cell based on the logic circuit replacement possibility determination method, adapt this library cell based on the prime factor included in the quotient between code values, and re-create the desired logic circuit. It is designed to be configured. Further, the code value of each library cell is calculated and stored for each system, and when selecting a cell, it is possible to replace a library cell having a code value greater than or equal to the code value of the partial logic circuit in order from the smallest code value. The decision is made.

Therefore, in the logic circuit replacement feasibility determination method, the replacement feasibility can be determined by performing the integer remainder calculation once for each code value of the partial logic circuits to be compared, and by classifying the connection form of the basic logic gate circuit. In addition, the determination as to whether or not replacement is possible is speeded up. Further, in the technology mapping device, by using this logic circuit replacement possibility determination method, the processing time is markedly shortened and the replacement is efficiently performed even for the composite library cell including a plurality of basic logic gate circuits. Further, the required time and the replacement efficiency are further improved by performing the permission / prohibition determination in a predetermined order based on the library code value table provided in advance.

[Brief description of drawings]

FIG. 1 is a block diagram of a technology mapping device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a partial logic circuit divided by a partial circuit extraction unit 2.

FIG. 3 is a prime factor table 7 in a sum-of-products system.

FIG. 4 is an actual circuit diagram of a library cell.

5 is an encoding circuit diagram of the library cell of FIG.

FIG. 6 is a circuit diagram of an adapted library cell.

[Explanation of symbols]

 1 logic circuit information input / output unit 2 partial circuit extraction unit 3 cell selection unit 4 cell adaptation unit 5 circuit reconstruction unit 6 library information input unit 7 sum-of-products prime factor table 8 sum-of-products prime factor table 9 sum-of-products library code value Table 10 Sum product library code value table

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takeshi Oguro 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (4)

[Claims] 1. A prime number or a prime number and -1 are assigned as coding prime factors for each of various basic gate circuits such as AND, OR, and NOT, and a tree structure is formed from these gate circuits so that an intermediate gate circuit output does not branch. A code value as a product of the coding prime factors is calculated for each of the first and second partial logic circuits, and whether or not circuit replacement is possible between the first and second partial logic circuits is determined based on the division relation between these code values. Judgment method of logic circuit replacement availability. 2. The logic circuit replacement feasibility determination method according to claim 1, wherein when the partial logic circuit is expressed by a logical function, a sum of terms consisting of products of logical variables is expressed as a sum of products system or a logic. What is expressed by the product of terms consisting of the sum of variables is defined as a sum product system, and at least each of the various basic gate circuits is assigned with a coding prime factor for the product sum system or the sum product system, A logic circuit replacement possibility determination method for calculating the code value based on the coding prime factor corresponding to each system into which the logic circuit is classified. 3. A technology for designing an LSI by replacing a desired logic circuit composed of various basic gate circuits such as AND, OR and NOT with one of a plurality of library cells composed of logic function blocks prepared in advance. In the mapping device, a means for dividing the desired logic circuit into a partial logic circuit according to claim 1 or a partial logic circuit classified into each of the systems according to claim 2, and the possibility of replacing the logic circuit according to claim 1 or 2. Cell selection means for selecting a library cell in which the partial logic circuit is replaceable based on the determination method, and a quotient of the division in the logic circuit replacement availability determination method are decomposed into prime factors, and predetermined adaptation processing is performed based on each prime factor. Cell adapting means for performing and a circuit reconfiguring hand for reconfiguring the divided and replaced partial logic circuit as a desired logic circuit. A technology mapping device comprising: a step. 4. The technology mapping device according to claim 3, wherein as the cell selecting means, a code value is calculated in advance for each of the library cells based on the logic circuit replacement availability determination method according to claim 1 or 2. Every time, the logic circuit replacement possibility judgment is performed in order from the smallest code value for the library cells having a code value greater than or equal to the code value of the partial logic circuit, and the library cell determined to be replaceable first is selected. A technology mapping device comprising cell selection means.