JPH06149197A - Display controller - Google Patents

Abstract

PURPOSE:To increase the number of display rows in the vertical direction without addition of any excess memory. CONSTITUTION:This device is constituted to be provided with a memory 5 storing image data and a display memory control circuit 1 controlling the input/ output of the image data for displaying the image data on a display device 6, and a row address generation circuit 2 outputting a row address for a memory 5, the row address generation circuit 3 outputting a column address for the memory 5 and an EXOR circuit 4 inputted with the most significant bit 101m of the row address outputted from the row address generation circuit 2 and the most significant bit 102m of the column address outputted from the column address generation circuit 3 and executing logical operation are provided in the display memory control circuit 1, and the image data is outputted to be displayed by prescribing the row address excepting the most significant bit of the row address as the row address 101 for the memory 5 and by precribing the column address excepting the most significant bit of the column address and the output of the EXOR circuit 4 as the column address 104 to the memory 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device, and more particularly to a display control device used for display in a personal computer or the like.

[0002]

2. Description of the Related Art A display control device using a memory, which is used in a conventional personal computer or the like,
As shown in FIG. 3, a display memory control circuit 1 including a row address generation circuit 2 and a column address generation circuit 3 and a memory 5 are provided corresponding to the display device 6.
The memory 5 includes an address decoder 7, a memory cell array 8, a serial data register 9, a serial counter 10, and a serial output buffer 11, as shown in FIG.

In FIG. 3, when the predetermined data is displayed on the display device 6, the row address generating circuit 2 outputs the row address 101 excluding the most significant bit, which is input to the memory 5 and the column. From the address generation circuit 3, the column address 102 excluding the most significant bit and the column address 104 including the most significant bit 102 _m of the column address are similarly input to the memory 5. Then, the clock signal 105 is also input to the memory 5. In the memory 5 shown in FIG. 5, the row address 101 input from the outside is used.
Is input to the memory cell array 8 via the address decoder 7, and the data 207 in the memory cell array 8 corresponding to the row line selected by the row address 101 is transferred to the serial data register 9. On the other hand, the column address 104 externally input to the serial counter 10 sets the input / output start point in the serial counter 10, and the serial data register 9 is also input to the serial data register 9 via the clock signal 105 also input to the serial counter 10. The data being transferred is the serial output buffer 11
, And is output from the serial output buffer 11 as a display data signal 106 for display. In this case, the data 207 of the memory cell array 8 corresponding to the row line selected by one row address signal is a value obtained by adding one address to the row address as soon as the display of the data for one row on the display screen is completed. As the next row address, the display corresponding to all the addresses is performed by sequentially repeating the above operation.

Next, regarding the operation of the conventional display control device of FIG. 3, FIG. 4A is referred to as an example of the configuration of the memory 5 corresponding to the display memory control circuit 1, and as an example of the display screen, FIG. This will be described with reference to (b). The memory configuration 201 shown in FIG. 4A includes 1024 bits of data that can be stored in the memory cell 202 corresponding to the row line of row address 0, and FIG. As shown, the display screen 205 displayed using a memory having a row address of 256 rows is
Only 512 bits are used as the data necessary for displaying the row. In this case, in the display memory control circuit 1, when the row address output from the row address generation circuit 2 is 0 and the column address output from the column address generation circuit 3 is 0, it is shown in FIG. The head data 203 in the memory cell 202 is used for displaying the head position 206 of the first row on the display screen 205, and the head data 203 in the memory cell 202 corresponding to the row line of the row address 0 of the memory configuration 201.
From then on, 512 bits of data are sequentially displayed on the display screen 205 of FIG. And the column address 513
The data after the second data 204 is not used for display. Similarly, when the entire screen of the display screen 205 is used for display, the row address 1 output from the row address generation circuit 2 in FIG.
01 is sequentially added one by one to generate a row address for display, and when the row address 101 exceeds the row address of the memory, the row address is returned to 0.

As described above, in the conventional display control device, since the data of the memory cell corresponding to the row line of one row address is used as the data of one row of the display screen, it is used for display. Although the required memory capacity is sufficient, there is a situation in which the number of display lines in the vertical direction cannot be supported.

[0006]

In the above-described conventional display control device using the memory, the data of the memory cell selected by one row address is 1 of the display screen.
Since it is used as data for a row, even if it has a sufficient memory capacity, there is a drawback that an additional memory capacity must be added for vertical display.

[0007]

A display control device of the present invention controls a memory for storing predetermined image data and an input / output of the image data in order to display the image data on a predetermined display device. In a display control device including a display memory control circuit, a row address generation circuit that generates and outputs a row address for the memory, a row address generation circuit that generates and outputs a column address for the memory, and the row address generation circuit. A logic circuit for performing logical operation processing by inputting the most significant bit of the row address output from the circuit and the most significant bit of the column address output from the column address generating circuit is provided at least in the display memory control circuit. The row address excluding the most significant bit of the row address is defined as a row address for the memory, and the column address is provided. The output of the column address and the logic circuit except for the most significant bit, and defined as the column address for the memory, is characterized in that the image is displayed and output data of the memory.

The logic circuit may be formed by a 2-input EXOR circuit.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, this embodiment includes a display memory control circuit 1 including a row address generation circuit 2, a column address generation circuit 3 and an EXOR circuit 4, and a memory 5 corresponding to a display device 6. Consists of In addition, the memory 5 includes an address decoder 7 as shown in FIG.
, Memory cell array 8 and serial data register 9
, Serial counter 10 and serial output buffer 1
1 and 1.

In FIG. 1, when displaying predetermined data on the display device 6, the row address generating circuit 2 outputs the row address 101 excluding the most significant bit and the most significant bit 101 _m of the row address. , The row address 101 is directly input to the memory 5, and the most significant bit 101 _m of the row address is input to the EXOR circuit 4. Similarly, the column address generation circuit 3 outputs the column address 102 excluding the most significant bit and the most significant bit 102 _m of the column address, the column address 102 is directly input to the memory 5, and the most significant bit 10 of the column address is also output.
2 _m is input to the EXOR circuit 4. In this case, the row address generated in the row address generation circuit 2 is prepared by one bit more than the row address in the memory 5,
An address twice the row address of the memory 5 is generated. The row address input to the memory 5 is, as described above, the most significant bit 1 of the row address.
Input the row address 102 excluding 02 _m . EXOR
In the circuit 4, the most significant bit 101 _m of the row address and the most significant bit 102 _m of the column address are exclusive ORed, and the output of the EXOR circuit 4 is the column address of the most significant bit. Column address 10 as 103
It is defined as a column address 104 together with 2, and is input to the memory 5.

Most significant bit 102 of the column address
_m indicates that the start point of serial input / output in the memory 5 is located in the first half or the second half of the serial data register 9 in FIG. According to the EXOR circuit 4, when the most significant bit 101 _m of the row address is 0, the column address 104 becomes the value itself generated in the column address generating circuit 3, and when the most significant bit 101 _m of the row address is 1, The most significant bit 102 _m of the column address is inverted so that the most significant bit 1 of the column address is
It becomes 03. As described above, the number of display rows in the vertical direction can be increased by dividing the memory 5 into two and using the most significant bit 101 _m of the row address.

Next, the operation of this embodiment will be described with reference to the memory configuration and the maximum display screen shown in FIGS. 2 (a) and 2 (b), respectively. As shown in FIG. 2A, when a memory having 256-bit row address and 1024-bit column address is used, the horizontal width of the display screen is 512 bits, and the data 203 of 0 is set to both the row address and the column address of the memory. If the display is started, 512 bits of data are used from the data 203 for horizontal display, and the latter half of the 1024 bits of data in the memory cell 202 corresponding to the row address 0 is Not used Similarly, when displaying 256 rows, the most significant bit 101 _m of the row address additionally output by the row address generation circuit 2 in FIG. 1 becomes 1 and all the lower bits become 0. Further, the most significant bit 102 _m of the column address is inverted so that the column address becomes 51
The data becomes 2, and 512 bits of data are displayed from the position of the data 204. Similarly, the number of lines in the vertical direction can be increased by displaying the subsequent lines.

In the embodiment shown in FIG. 1,
Although the display memory control circuit 1 is configured using the EXOR circuit 4, it includes other gate circuits other than the EXOR circuit, such as an AND circuit, a NAND circuit, an OR circuit, a NOR circuit, an EXNOR circuit, and a selection circuit. Even if the circuit configuration of is used, the function equivalent to that of the EXOR circuit 4 can be obtained. Further, the memory connected to the display memory control circuit is not limited to the method of separately inputting the row address and the column address as shown in this embodiment, and both of these addresses can be input to the same signal line. The present invention is also realized by a memory that is input more. Furthermore, in the memory shown in FIG. 5, it goes without saying that if the serial output buffer 11 is replaced with a memory capable of inputting / outputting, the same function is obtained. In this case, not only the data is displayed but also the video is displayed. The same effect can be obtained when writing data in the memory.

[0015]

As described above, the present invention is applied to a display control device using a memory, and logical operations are performed on the most significant bits of the addresses output from the row address generating circuit and the column address generating circuit. By adding the column address obtained through the processing as the column address for the memory, it is possible to increase the number of display rows in the vertical direction without adding an extra memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a memory configuration and a display screen in the one embodiment.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a diagram showing a memory configuration and a display screen in a conventional example.

FIG. 5 is a diagram showing a configuration of a memory.

[Explanation of symbols]

 1 display memory control circuit 2 row address generation circuit 3 column address generation circuit 4 EXOR circuit 5 memory 6 display device 7 address decoder 8 memory cell array 9 serial data register 10 serial counter 11 serial output buffer

Claims (2)

[Claims] 1. A memory for storing predetermined image data,
In a display control device, comprising: a display memory control circuit for controlling input / output of the image data in order to display the image data on a predetermined display device; a row address generation circuit for generating and outputting a row address for the memory. A row address generation circuit for generating and outputting a column address for the memory; a most significant bit of a row address output by the row address generation circuit; and a most significant bit of a column address output by the column address generation circuit. A logic circuit that inputs a bit and performs a logical operation process, and a row address excluding the most significant bit of the row address as a row address for the memory, The column address excluding the most significant bit of the address and the output of the logic circuit are added to the column add to the memory. A display control device, characterized in that the image data in the memory is displayed and output. 2. The display control device according to claim 1, wherein the logic circuit is formed by a two-input EXOR circuit.