JPH0614614B2 - Error correction method for digital-analog converter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for correcting an error in a digital-analog converter, and particularly to a method for accurately correcting a linearity error thereof.

[Prior art and its problems]

Conventionally, a digital-analog converter (D
AC) is used for high-precision power supplies.

For example, "18-bit High Precision DC Measurement System" (Robert B. Craven and E. Rachel Morris, 1982.
The error correction method described in a document called Teradyne Incorporated, Inc. (March, 2013) uses the following procedures with respect to three items of linearity, offset and gain.

First, correction of linearity will be described. Considering now that the DAC used inside the voltmeter is an 8-bit DAC, the output voltage E ₀ (N) of the DAC is E ₀ (N) = (d (0) · ²⁷ + d ( 1) ・ 2 ⁶ +… + d (7) ・ 2 ⁰・ E _NFS / 2 ⁸ (1) where d = d (0) d (1)… d (7) d (0 ) Is the MSB and d (7) is an 8-bit binary number with LSB.) E _NFS = nominal full-scale voltage E _NFS / 2 ⁸ = 1 LSB nominal voltage.

Therefore, when only d (i) in the code N input to this DAC is 1 and the other digit positions are 0, the output voltage E ₀ (d (i)), that is, the weight of the bit d (i) is (Assuming the DAC works without error):

E ₀ (d (0)) ＝ E ₀ (10000000) ＝ E _NFS / 2 (2) E ₀ (d (1)) ＝ E ₀ (01000000) ＝ E _NFS / 4 (3) ・ ・ ・ ・ ・ ・ ・E ₀ (d (7)) ＝ E ₀ (00000001) ＝ E _NFS / 256 (4) Also, the binary value carry value C (0), which is the voltage change at the time of the main (half scale) carry, is , here, Therefore, C (0) = (E _NFS / 2 ⁸ ) {2 ⁷ − (2 ⁷ −1)} = E _NFS / 2 ⁸ × 1 = 1LSB (7) That is, when a major carry occurs, All the bits of the 8-bit code N change its value, but the change in voltage stops at 1 LSB. Similarly, a quarter-scale carry value
C (1), the octal scale carry value C (2), ..., The 256th minute carry value C (7) can also be expressed as follows.

When the bit weight E ₀ (d (i)) of the bit d (i) is calculated from the equations (1) to (10), That is, From Equations (12) to (15), if the bit weights are expressed as carry values C (0) to C (7), Becomes This allows the carry values C (0) to C (7) to be
The actual bit weights E ₀ (d (0)) to E ₀ (d (7)) of the DAC can be determined. The linearity correction value of the DAC is obtained by using the actual bit weight thus obtained.

Next, the offset correction value is obtained by short-circuiting the input terminals of the voltmeter. The gain correction value is determined from the reference voltage measurement value in each voltmeter range. In the calibration of the voltmeter, each correction value obtained as described above is used, and after the measurement, the calculation processing unit (CPU) corrects it by calculation.

However, in the above-described linearity correction method in the prior art, as is clear from the equations (16) to (20), as the number of bits increases, the higher bits such as d (0) and d (1) The weight has a drawback in that the errors contained in the carry values C (0) to C (7) are accumulated, and the errors become extremely large.

The drawback of this error accumulation will be described more specifically. Since each carry value C (0) to C (7) is an actually measured value, it always contains a measurement error. Letting δ be the maximum value of these measurement errors, the maximum error e (i) brought to the bit weight E ₀ (d (i)) is evaluated based on the equations (15) to (20). become.

Therefore, the error introduced into the bit weight due to the carry value measurement error increases in a snowball fashion as it goes to higher bit positions. This error directly becomes an error when correcting the linearity.

[Object of the Invention]

It is an object of the present invention to provide an error correction method for a DAC that prevents an increase in error due to the accumulation of carry value errors as described above.

[Outline of Invention]

According to the embodiment of the present invention, the correction value of each bit position regarding the linearity of the DAC is determined based on the bit position and a carry value higher than the bit position. According to this, the carry value of the bit position on the upper side affects the correction value of the bit position only in the form in which a small coefficient is applied, so that there is no error accumulation as described above.

〔Example〕

FIG. 1 is a block diagram of a digital-analog conversion circuit that corrects an error based on the error correction method of the present invention. In the figure, the highly stable DAC 3 has a desired stability and the bit superposition error can be ignored, but the required accuracy is not satisfied. The latter-stage amplifier 4 and the like satisfy the desired stability and linearity, but do not satisfy the gain and offset. First, at the time of calibration, the linearity, the gain, and the offset error of the circuit including the DAC 3, the amplifier 4, and the variable resistor 5 are individually obtained. Based on this, the correction data recombined for each bit pattern of DAC3 is stored in RAM1. Digital input signal V
_{When i} is input, the DAC 3 outputs an analog signal containing an error corresponding to the bit pattern of the digital input signal bit. On the other hand, RAM1 outputs the correction data corresponding to this bit pattern and gives it to DAC2, and DAC2 outputs a correction output signal in response to it.

The output signal of the DAC 3 and the corrected output signal of the DAC 2 are added and output as an analog output signal V ₀ of desired accuracy via the amplifier 4. The correction data is obtained as follows.
The bit length of the input of DAC3 is assumed to be m bits.

Hereinafter, a method of obtaining a correction value for correcting the linearity error will be described.

Here, the bit position is 0,1, ..., m-1 from the most significant bit (MSB).
Number.

The correction value ΔCE _i of the i-th bit for linearity is defined as follows.

ΔCE _i = W _ideal (i) -W _real (i) where W _ideal (i) is the ideal weight of the i-th bit W _real (i) is the actual weight of the i-th bit. That is, the correction value of bit i is an error from the ideal value of the weight of bit i.

The following relational expressions are derived from the description of the conventional technique using the expressions (1) to (20).

W _ideal (i) ＝ W _ideal (i-1) / 2 W _real (i) ＝ C (i) + W _real (i + 1) + W _real (i + 2) +… ＋ W _real (m-1) W _real (i-1) ＝ C (i-1) + W _real (i) + W _real (i + 1) ＋ W _real (i + 2) +… + W
_real (m-1) Using these relational expressions, the above definition of the bit correction value can be transformed as follows.

ΔCE _i ＝ W _ideal (i) -W _real (i) ＝ W _ideal (i-1) / 2-W _real (i) ＝ {W _ideal (i-1) -W _real (i-1)} / 2 ＋ {W _real (i-1) -W _real (i)} / 2 −W _real (i) / 2 ＝ {ΔCE _i-1 + C (i-1) + W _real (i) -C (i) } / 2 −W _real (i) / 2 = {ΔCE _i-1 + C (i-1) -C (i)} / 2 Thus, the bit correction value ΔCE _i is carried to C (i-1), Bit correction value ΔCE _{i-1 for} C (i) and the bit position one level higher
The recurrence formula represented by is obtained.

Here, ΔCE ₀ = 0, that is, the correction value of MSB is 0. This means that the MSB bit weight is adopted as a reference. By using this initial value and the recurrence formula above, each bit correction value can be obtained for:

Obtaining the linearity correction value in this manner has the following advantages as compared with the method given as the prior art.

Since the carry value is a value that is actually measured, there is always a measurement error. Letting δ be the maximum error of these carry values, the upper limit of the error of the correction value ΔCE _i for each bit is
These correction values can be evaluated as follows from the above equations, which represent carry values and correction values for the upper bits.

Error of ΔCE ₁ (upper limit of error of C (0) + upper limit of error of C (1)) / 2 = δ Error of ΔCE ₂ (upper limit of error of C (1) + upper limit of error of C (2)) / 2 + ΔCE ₁ error upper limit / 2 = δ + δ / 2 ΔCE ₃ error (C (2) error upper limit + C (3) error upper limit) / 2 + ΔCE ₂ error upper limit / 2 = δ + δ / 2 + δ / 4 The same applies hereinafter.

From this, it is clear that the error of the correction value ΔCE _i for any bit position is 2 no matter how many bits are increased.
δ, that is, twice the maximum value of the measurement error of the carry value at each bit position is not exceeded.

From the correction value ΔCE _i obtained in this way, 2 of the DAC input
Correction value ΔCEB _p for each of the ^m bit patterns
(Where p = 0, 1, 2, ..., 2 ^m −1) can be obtained by the following equation.

The correction value corresponding to each bit pattern thus obtained is stored in the RAM 1 as described above.

As described above, the DAC error includes a gain error and an offset error in addition to the linearity error. When it is necessary to correct these errors as well, the correction value for that is, for example, [Prior Art]. And its problems].

〔The invention's effect〕

As described above in detail, according to the error correction method of the digital-analog converter of the present invention, the carry value is used.
In correcting the linearity of the DAC, there is a great effect that the magnitude of the correction error for each bit position is kept at a substantially constant small value regardless of the bit position.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital-analog conversion device capable of performing error correction by applying the present invention. 1: RAM 2, 3: DAC 4: Amplifier 5: Variable resistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-53-120378 (JP, A) JP-A-58-222616 (JP, A) JP-A-55-100744 (JP, A)

Claims (2)

[Claims] 1. When obtaining a correction value which is an error of an actual weight of each bit of an input digital value at an output of a digital-analog converter from an ideal weight, a correction value ΔCE _{i at} each bit position _i is The correction value ΔCE _{i-1 of the} next higher bit position i-1, the bit position and 1
Measured carry value C at the next higher bit position
Based on the fact that there is a relationship of ΔCE _i = ΔCE _i-1 / 2 + {C (i-1) −C (i)} / 2 between (i) and C (i-1), A value is obtained from the carry value of the bit position and a bit position higher than the bit position, a correction value for each bit pattern of the input digital value is obtained from the correction value for each bit, and the input Error correction of a digital-analog converter, characterized by storing in a storage means addressed by a digital value, converting an output of the storage means into a corresponding analog output and adding the output to the digital-analog converter. Method. 2. The error correction method for a digital-analog converter according to claim 1, wherein the correction value at the most significant bit position is 0.