JPH0614536B2 - Bipolar integrated circuit - Google Patents
Bipolar integrated circuitInfo
- Publication number
- JPH0614536B2 JPH0614536B2 JP60203328A JP20332885A JPH0614536B2 JP H0614536 B2 JPH0614536 B2 JP H0614536B2 JP 60203328 A JP60203328 A JP 60203328A JP 20332885 A JP20332885 A JP 20332885A JP H0614536 B2 JPH0614536 B2 JP H0614536B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- base region
- junction
- integrated circuit
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 claims description 14
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 229920006395 saturated elastomer Polymers 0.000 claims description 4
- 230000007704 transition Effects 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 33
- 230000003071 parasitic effect Effects 0.000 description 19
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 16
- 239000012535 impurity Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910018885 Pt—Au Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明はエミッタ領域とベース領域との接合をヘテロ接
合とするヘテロ接合バイポーラトランジスタで非飽和型
論理回路を構成するバイポーラ集積回路に関する。Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a bipolar integrated circuit that constitutes a non-saturation type logic circuit with a heterojunction bipolar transistor in which a junction between an emitter region and a base region is a heterojunction.
バイポーラトランジスタのエミッタ領域をベース領域よ
りバンドギャップの広い物質で形成するヘテロ接合バイ
ポーラトランジスタは、エミッタ領域とベース領域をホ
モ接合としたホモ接合バイポーラトランジスタに比べ、
多くの利点を有することが知られている。それらの利点
を要約すると以下の様になる。A heterojunction bipolar transistor in which the emitter region of the bipolar transistor is formed of a material having a wider bandgap than the base region is compared to a homojunction bipolar transistor in which the emitter region and the base region are homojunction,
It is known to have many advantages. The advantages are summarized below.
(1)エミッタ領域の不純物濃度対ベース領域の不純物濃
度の比が小さくてもバンドギャップの違いを利用するこ
とによりエミッタ注入効率を高くすることができる。(1) Even if the ratio of the impurity concentration of the emitter region to the impurity concentration of the base region is small, the emitter injection efficiency can be increased by utilizing the difference in band gap.
(2)(1)の結果、ベース不純物濃度を高く設定できるため
ベース抵抗を低減できる。(2) As a result of (1), since the base impurity concentration can be set high, the base resistance can be reduced.
(3)エミッタ領域の不純物濃度を低くできるためにエミ
ッタ接合容量を低減できる。(3) Since the impurity concentration in the emitter region can be lowered, the emitter junction capacitance can be reduced.
これらの利点のために、ヘテロ接合バイポーラトランジ
スタはホモ接合バイポーラトランジスタに比べ、高周波
特性，スイッチング特性が優れており、マイクロ波用ト
ランジスタ，高速論理回路用トランジスタとして極めて
有望である。Due to these advantages, the heterojunction bipolar transistor is superior to the homojunction bipolar transistor in high-frequency characteristics and switching characteristics, and is extremely promising as a microwave transistor and a high-speed logic circuit transistor.
第２図に従来の論理回路に使われているヘテロ接合バイ
ポーラトランジスタの簡単な構造断面図を示す。ベース
電極をとりだすためには図のような構造となり、ベース
電極をとりだし部分に領域ｂに示すような寄生のダイオ
ードが存在する。この寄生ダイオードのためベース領域
とコレクタ領域との接合面積が増し、その結果、ベース
領域とコレクタ領域との間の接合容量が増大する。スイ
ッチング速度を決める主要要素はベース領域・コレクタ
領域の接合容量と負荷抵抗の積であり、ベース領域・コ
レクタ領域との間接合容量が大きいことはこの素子で構
成された論理回路の高速性を損うことになる。即ち従来
構造の論理回路ではトランジスタのコレクタ領域側にこ
の寄生外部ベース領域（領域ｂ）が存在するため、領域
ａの真性トランジスタのベース領域とコレクタ領域との
接合の数倍以上の容量をコレクタ領域側に持つことにな
り、ヘテロ接合バイポーラトランジスタが本来持合ち得
る高速性を十分には引き出していないものであった。FIG. 2 shows a simple structural sectional view of a heterojunction bipolar transistor used in a conventional logic circuit. In order to take out the base electrode, the structure is as shown in the figure, and a parasitic diode as shown in the region b exists in the portion where the base electrode is taken out. This parasitic diode increases the junction area between the base region and the collector region and, as a result, increases the junction capacitance between the base region and the collector region. The main factor that determines the switching speed is the product of the junction capacitance of the base region / collector region and the load resistance, and the large junction capacitance between the base region and collector region impairs the high speed operation of the logic circuit composed of this element. It will happen. That is, since the parasitic external base region (region b) exists on the collector region side of the transistor in the logic circuit of the conventional structure, the collector region has a capacitance several times or more the junction between the intrinsic transistor base region and the collector region. However, the heterojunction bipolar transistor has not sufficiently brought out the high speed that the heterojunction bipolar transistor originally has.
本発明は上述した従来技術の問題点に鑑みて成されたも
のであり、ヘテロ接合バイポーラトランジスタの持つ高
速性を十分に生かせる論理回路を構成したバイポーラ集
積回路提供することを目的とする。The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide a bipolar integrated circuit that constitutes a logic circuit that can make full use of the high speed of the heterojunction bipolar transistor.
既に述べたように従来構造のヘテロ接合バイポーラトラ
ンジスタでは、ベース領域・コレクタ領域間に寄生外部
ベース領域が存在するため高速性を十分発揮できない。
このベース領域・コレクタ領域間の寄生外部ベース領域
を小さくすることがこの問題の解決策である。しかし、
寄生外部ベース領域を小さくするとベース領域のコンタ
クトの形成が難しく、歩留りが著しく低下するなどの種
々の悪影響が生じる。従ってベース領域・コレクタ領域
の間の寄生外部ベース領域を小さくし、なおかつ容易に
ベース領域のコンタクトがとれる構造のもので論理回路
を形成すれば、ヘテロ接合バイポーラトランジスタの本
来の高速性を十分生かせると考えられる。As described above, the heterojunction bipolar transistor having the conventional structure cannot sufficiently exhibit high speed because the parasitic external base region exists between the base region and the collector region.
The solution to this problem is to reduce the parasitic extrinsic base region between the base region and the collector region. But,
If the parasitic extrinsic base region is made small, it is difficult to form a contact in the base region, and various adverse effects such as a significant decrease in yield occur. Therefore, if the parasitic external base region between the base region and the collector region is made small and a logic circuit is formed with a structure in which the base region can be easily contacted, the original high speed of the heterojunction bipolar transistor can be fully utilized. Conceivable.
本発明はこの基本的な考察に基いたもので、ベース領域
・エミッタ領域の接合面積をベース領域・コレクタ領域
の接合面積より広くし、ベース領域のコンタクトの直下
はベース領域とエミッタ領域の接合になるように形成し
たヘテロ接合バイポーラトランジスタで構成し、このト
ランジスタを配線接続して非飽和型論理回路を構成した
バイポーラ集積回路である。本発明の論理回路を構成す
るトランジスタではベース領域・コレクタ領域間の寄生
外部ベース領域がない代りにベース領域・エミッタ領域
間の寄生外部ベース領域が形成される。しかし、ヘテロ
接合バイポーラトランジタでは先に述べた好くドーピン
グ濃度を任意に選定することができるため、ベース領域
とエミッタ領域の接合容量は比較的小さくすることが可
能である。また回路を非飽和型にすることによって、ス
イッチング時のベース領域とエミッタ領域間の電圧変化
を小さく抑えることができるため、ベース領域とエミッ
タ領域の寄生外部ベース領域の影響は、ベース領域・コ
レクタ領域間に形成された寄生外部ベース領域の影響よ
り著しく小さい。The present invention is based on this basic consideration. The junction area of the base region / emitter region is made wider than the junction area of the base region / collector region, and the region directly below the contact of the base region is the junction region of the base region and the emitter region. It is a bipolar integrated circuit in which a heterojunction bipolar transistor formed as described above is connected, and the transistors are connected by wiring to form a non-saturation type logic circuit. In the transistor constituting the logic circuit of the present invention, the parasitic external base region between the base region and the collector region is not formed, but the parasitic external base region between the base region and the emitter region is formed. However, in the heterojunction bipolar transistor, the preferable doping concentration described above can be arbitrarily selected, so that the junction capacitance between the base region and the emitter region can be made relatively small. Also, by making the circuit non-saturated, the voltage change between the base region and the emitter region during switching can be suppressed to a small level. Significantly less than the effect of parasitic extrinsic base regions formed in between.
上記のことは以下に示すことにより明らかである。寄生
外部ベース領域が、(1)エミッタ領域側にある場合と、
(2)コレクタ領域側にある場合のスイッチング時間を計
算機を用いたスイッチングシミュレーションにより評価
した。(1)，(2)それぞれの場合について、５段のリング
発振シミュレーションにより伝播遅延時間tpdをみつも
った結果を第３図に示す。(1)のエミッタ領域側に寄生
外部ベース領域がある場合、トランジスタのベース領域
・エミッタ領域の接合が順バイアスされると寄生外部ベ
ース領域も順バイアスされる。しかし寄生外部ベース領
域の接合をワイドギャップ同志のホモ接合することによ
り真性トランジスタのベース領域・エミッタ領域接合よ
りビルトイン電圧が増すため、寄生外部ベース領域を流
れる電流は直流特性では無視できる程小さくできる。第
３図のたて軸は(1)のtpdと(2)のtpdの比tpd(1)／tpd(2)
であり、これが１のとき寄生外部ベース領域はエミッタ
領域側でもコレクタ領域側でも影響が同じであるという
ことである。図から明らかなようにいずれの場合も、外
部ベース面積が増すとtpd(1)／tpd(2)が小さくなりエミ
ッタ領域側に外部ベース領域がある方が高速動作できる
ことがわかる。非飽和動作の代表的なNTL，CMLゲート等
は飽和動作するDCTLゲートに比べ、tpd(1)／tpd(2)が明
らかに小さく、エミッタ領域側に外部ベース領域をもっ
てくる効果が顕著である。(1)の場合、オン・オフ共ま
ず外部ベース領域に電流が流れ、または電流が先に切
れ、真性トランジスタのエミッタ電流の立ち上り立ち下
がりはそれだけ遅れる。(2)の場合、エミッタ電流はす
ぐに立ち上がるが、コレクタ側についている外部ベース
領域のため負荷に流れる電流のスイッチングが遅れる。
特にオフの場合、外部ベース領域部分の電流の立ち下が
りが非常に遅く、スイッチングが遅れる原因となる。飽
和動作では動作電圧範囲が広く、エミッタ電流のオン・
オフ時間も無視できない程大きいため、(1)と(2)の場合
の差がでにくい。それに対し非飽和動作ではエミッタ充
放電時間のスイッチングに占める割合は非常に小さく、
スイッチング時間は主にコレクタキヤパシタンスの放電
できまるため、(1)(2)の差が大きく、(1)の方がずっと
有利になる。従って、本発明のように寄生外部ベース領
域をエミッタ領域側に形成したヘテロ接合バイポーラト
ランジスタを用いて非飽和型論理回路を構成することに
より、超高速動作が可能な論理回路を提供することがで
きる。The above is clear from the following. When the parasitic extrinsic base region is (1) on the emitter region side,
(2) The switching time on the collector side was evaluated by switching simulation using a computer. Fig. 3 shows the results of observing the propagation delay time tpd by a 5-stage ring oscillation simulation in each of the cases (1) and (2). When the parasitic extrinsic base region is present on the side of the emitter region in (1), when the junction between the base region and the emitter region of the transistor is forward biased, the parasitic extrinsic base region is also forward biased. However, since the junction of the parasitic extrinsic base region is a homojunction of wide gaps, the built-in voltage is higher than that of the junction of the base region and the emitter region of the intrinsic transistor. The vertical axis in Fig. 3 is the ratio of tpd of (1) to tpd of (2) tpd (1) / tpd (2)
When this is 1, it means that the parasitic extrinsic base region has the same influence on both the emitter region side and the collector region side. As is clear from the figure, in any case, as the external base area increases, tpd (1) / tpd (2) becomes smaller, and it is understood that the external base region on the emitter region side allows higher speed operation. Typical non-saturated NTL and CML gates have a significantly smaller tpd (1) / tpd (2) than the saturated DCTL gate, and the effect of bringing the external base region to the emitter region side is remarkable. In the case of (1), a current flows in the external base region first in both on and off, or the current is cut off first, and the rise and fall of the emitter current of the intrinsic transistor are delayed accordingly. In the case of (2), the emitter current rises immediately, but the switching of the current flowing to the load is delayed due to the external base region on the collector side.
Especially when it is off, the fall of the current in the external base region is very slow, which causes a delay in switching. In saturation operation, the operating voltage range is wide and the emitter current
Since the off-time is too large to be ignored, the difference between cases (1) and (2) is less likely to occur. On the other hand, in non-saturated operation, the ratio of emitter charge / discharge time to switching is very small,
Since the switching time can mainly discharge the collector capacitance, the difference between (1) and (2) is large, and (1) is much more advantageous. Therefore, by constructing a non-saturation type logic circuit using the heterojunction bipolar transistor in which the parasitic external base region is formed on the emitter region side as in the present invention, it is possible to provide a logic circuit capable of ultra-high speed operation. .
上記のようにヘテロ接合バイポーラトランジスタで非飽
和型回路を構成した本発明のバイポーラ集積回路によれ
ば、寄生外部ベース領域が存在してもヘテロ接合バイポ
ーラトランジタ本来の高速性能を十分に生かすことがで
きる。According to the bipolar integrated circuit of the present invention in which the non-saturation type circuit is constituted by the heterojunction bipolar transistor as described above, the original high speed performance of the heterojunction bipolar transistor can be sufficiently utilized even if the parasitic external base region exists. it can.
以下本発明の一実施例を第１図(a)(b)を参照して説明す
る。An embodiment of the present invention will be described below with reference to FIGS. 1 (a) and 1 (b).
本実施例におけるヘテロ接合バイポーラトランジスタは
最上層がコレクタ領域で構成されるコレクタトップ型の
ものであって、ベース領域はGaAsエミッタ領域（ベース
領域と接合をなす部分）はベース領域より広いバンドギ
ャップとなるAl0.3Ga0.7Asで構成されている。また本実
施例においてはこのコレクタトップ型のヘテロ接合バイ
ポーラトランジスタを配線接続し、非飽和型論理回路の
CML（Current Mode Logic）を構成している。そしてこ
のヘテロ接合バイポーラトランジスタを用いた論理回路
を製造するには、半絶縁性基板の上に順次導電層をエピ
タキシアル成長させることが必要である。エピタキシア
ル層の成長法としてはMBE法（分子線エピタキシー法）
かMOCVD法（有機金属気相成長法）が適している。第１
図(a)はMBE法を用いた例であり、この製造のトランジス
タは以下の手順で作られる。まず、半絶縁性GaAs基板１
上に厚さ5000Å，不純物（Si）濃度２×1018cm-3のｎ+
型GaAs層２、厚さ3300Å，不純物（Si）濃度３×1017cm
-3のｎ型Al0.3Ga0.7As層３、厚さ２００Å、不純物（S
i）３×1017cm-3で、成長方向に対してAlの組成ｘが０
から０．３迄連続又は段階的に変化するｎ型AlxGa1-xAs
層（遷移領域）４を順次形成し、ｎ型エミッタ領域２０
を構成する。なおｎ型エミッタ領域２０全体をこの領域
上に形成するベース領域よりもバンドギャップの広い第
１種半導体即ちAlGaAsで構成しても良いが、AlGaAsは不
純物濃度を高くできない為、本実施例ではベース領域と
ｐｎ接合を構成する付近以外を第２種半導体即ちGaAsで
構成している。したがって特許請求の範囲第１種半導体
で構成したエミッタ領域とは、少なくともベース領域と
ｐｎ接合を構成する付近の構成材料のことであって、エ
ミッタ領域全体を第１種半導体で構成するという意味で
はない。次に上記遷移領域４畳にベース領域となる厚さ
1000Å，不純物濃度３×1018cm-3のｐ+型GaAs６を形成
し、エミッタ領域２０とｐｎのヘテロ接合を構成する。
このベース領域のｐ型不純物としてBeを用いた。次いで
このベース領域上に厚さ3500Å，不純物濃度１×1017cm
-3のｎ型GaAs層７及び厚さ1000Å，不純物濃度２×1018
cm-3のｎ+型GaAs層８を形成する。このｎ型GaAs層７と
ｎ+層８とでコレクタ領域３０を構成し、ベース領域ｐ
ｎ接合が形成される。これでウエハ形成工程は完了す
る。次にCMLゲートを形成する工程に移る。まず選択イ
オン注入によりベース領域のコンタクトを取る為に外部
ベース領域６ａを形成する。このイオン注入は例えばMg
が用いられドーズ量２×1014cm-2、加速電圧２００KeV
で行われる。またこのイオン注入はエミッタ領域を構成
するｎ型AlGaAs層３の表面迄達する程度に行われる。次
にトランジスタ内部のベース領域・エミッタ領域間及び
素子間の分離を行う。これは分離領域１０，９にたとえ
ばＨ+，Ｂ+等を選択的にイオン注入ことにより実現でぎ
る。この後外部ベース領域６ａの表面をエッチングし、
外部ベース領域６ａとエミッタ９領域のｎ+型６ａAs層
８が接触しないようにする。次いで、イオン注入で形成
した素子分離領域９上にNiCr等を蒸着パターニングして
負荷抵抗１７となる層を形成する。次にエミッタ領域の
コンタクトを形成するためにウエハ表面からエミッタ領
域のｎ+型GaAs層１に達する迄エッチングを行ない、そ
の部分に薄いAuGeを形成し、そのAuGe層の上にAu層を形
成してエミッタ電極１２を形成する。The heterojunction bipolar transistor in this embodiment is a collector-top type in which the uppermost layer is composed of a collector region, and the base region has a GaAs emitter region (a part forming a junction with the base region) having a wider bandgap than the base region. It consists of Al0.3Ga0.7As. In addition, in this embodiment, the collector-top type heterojunction bipolar transistor is connected by wiring to form a non-saturation type logic circuit.
It constitutes CML (Current Mode Logic). In order to manufacture a logic circuit using this heterojunction bipolar transistor, it is necessary to sequentially epitaxially grow conductive layers on a semi-insulating substrate. MBE method (molecular beam epitaxy method) as a growth method for the epitaxial layer
The MOCVD method (metal organic chemical vapor deposition method) is suitable. First
Figure (a) is an example using the MBE method, and the transistor of this manufacture is manufactured by the following procedure. First, the semi-insulating GaAs substrate 1
N + with a thickness of 5000Å and impurity (Si) concentration of 2 × 10 18 cm -3
Type GaAs layer 2, thickness 3300Å, impurity (Si) concentration 3 × 10 17 cm
-3 n-type Al0.3Ga0.7As layer 3, thickness 200Å, impurities (S
i) 3 × 10 17 cm −3 , Al composition x is 0 in the growth direction
N-type Al x Ga 1-x As varying continuously or stepwise from 1 to 0.3
Layers (transition regions) 4 are sequentially formed, and n-type emitter regions 20 are formed.
Make up. Although the entire n-type emitter region 20 may be formed of a first-type semiconductor having a wider bandgap than that of the base region formed on this region, that is, AlGaAs, AlGaAs cannot have a high impurity concentration, so in this embodiment the base is used. The region other than the vicinity forming the pn junction with the region is formed of the second type semiconductor, that is, GaAs. Therefore, the term "emitter region formed of the first type semiconductor" means a constituent material at least in the vicinity of the pn junction with the base region, and does not mean that the entire emitter region is formed of the first type semiconductor. Absent. Next, in the transition area 4 tatami, the thickness to be the base area
A p + type GaAs 6 of 1000 Å and an impurity concentration of 3 × 10 18 cm -3 is formed to form a heterojunction between the emitter region 20 and pn.
Be was used as a p-type impurity in this base region. Then, on this base region, a thickness of 3500Å and an impurity concentration of 1 × 10 17 cm
-3 n-type GaAs layer 7 and thickness 1000Å, impurity concentration 2 × 10 18
A cm -3 n + type GaAs layer 8 is formed. The n-type GaAs layer 7 and the n + layer 8 constitute a collector region 30 , and the base region p
An n-junction is formed. This completes the wafer forming process. Next, the step of forming a CML gate is performed. First, an external base region 6a is formed to make contact with the base region by selective ion implantation. This ion implantation is for example Mg
Is used with a dose of 2 × 10 14 cm -2 and an acceleration voltage of 200 KeV
Done in. Further, this ion implantation is performed to such an extent that it reaches the surface of the n-type AlGaAs layer 3 forming the emitter region. Next, isolation is performed between the base region / emitter region and the element inside the transistor. This can be achieved by selectively implanting H + , B + or the like into the isolation regions 10 and 9. After this, the surface of the external base region 6a is etched,
The external base region 6a and the n + type 6a As layer 8 in the emitter 9 region are prevented from contacting each other. Then, NiCr or the like is vapor-deposited and patterned on the element isolation region 9 formed by ion implantation to form a layer to be the load resistor 17. Next, in order to form a contact in the emitter region, etching is performed from the wafer surface until the n + type GaAs layer 1 in the emitter region is reached, a thin AuGe is formed in that portion, and an Au layer is formed on the AuGe layer. To form the emitter electrode 12.
次いで表面エッチングした外部ベース領域上にAuZnを蒸
着、パターニングしベース電極１３を形成する。更にコ
レクタ領域のｎ+型GaAs層８上にAuGe層を形成し、その
上にAu層を形成してコレクタ電極１４を形成する。その
後にエミッタ電極、ベース電極及びコレクタ電極上にTi
−Pt−Au層を形成して一層配線１５を行う。その上にSi
O2等の層間絶縁膜１１を形成する。これはCVD法等によ
り実現できる。Next, AuZn is vapor-deposited and patterned on the externally etched base region to form the base electrode 13. Further, an AuGe layer is formed on the n + type GaAs layer 8 in the collector region, and an Au layer is formed thereon to form the collector electrode 14. After that, Ti on the emitter electrode, base electrode and collector electrode
The -Pt-Au layer is formed and the single-layer wiring 15 is performed. Si on it
An interlayer insulating film 11 such as O 2 is formed. This can be realized by the CVD method or the like.
次いでエッチグにより一層目の配線１５と二層目の配線
１６を接続するためのコンタクトホールを形成し、その
上に二層目の配線１６をTi-Pt-Au等を用いて形成する。
この２層目の配線によって第１図(b)に示すようなCML回
路（１ゲート）を構成する。Next, a contact hole for connecting the wiring 15 of the first layer and the wiring 16 of the second layer is formed by etching, and the wiring 16 of the second layer is formed thereon by using Ti-Pt-Au or the like.
The second layer wiring constitutes a CML circuit (1 gate) as shown in FIG. 1 (b).
次に、本発明の実施例のベース領域・エミッタ領域接合
がベース領域・コレクタ領域の接合より広く、ベース領
域のコンタクトはベース領域・エミッタ領域の接合の一
部の上に形成されたヘテロ接合バイポーラトランジスタ
で構成されたCMLゲートと、従来のベース領域・コレク
タ領域の接合がベース領域・エミッタ領域の接合より広
いヘテロ接合バイポーラトランジスタから成るCMLゲー
トのスイッチング特性を、それぞれ５段リング発振シミ
ュレーションにより評価した結果を第４図に示す。真性
トランジスタの面積が４×10-7， ４×10−８ｃｍ2いずれの場合も付から明らかなように
実施例の法が従来例に比べて外部ベース面積が増加して
も、伝播遅延時間tpdの増加率は非常に小さい。通常外
部ベース面積は真性トランジスタ面積の２倍程度はある
と考えらるので、本発明を使うと、tpdが従来例の2/3〜
1/2程度に改善される。さらにそのと消費電力は本発明
も従来例もほとんど変わらない。従って本発明を用いる
ことにより消費電力を増すことなく、伝播遅延時間を大
巾に改善できる。Next, the base region / emitter region junction of the embodiment of the present invention is wider than the base region / collector region junction, and the base region contact is formed on a part of the base region / emitter region junction. The switching characteristics of a CML gate composed of a transistor and a CML gate composed of a heterojunction bipolar transistor in which the junction between the base region and the collector region is wider than the junction between the base region and the emitter region are evaluated by a 5-stage ring oscillation simulation. Results are shown in FIG. As can be seen from the accompanying drawings , in both cases where the area of the intrinsic transistor is 4 × 10 −7 or 4 × 10 −8 cm 2 , even if the external base area of the method of the embodiment is larger than that of the conventional example, the propagation delay time is increased. The rate of increase in tpd is very small. Normally, it is considered that the external base area is about twice as large as the intrinsic transistor area. Therefore, when the present invention is used, the tpd is 2/3 that of the conventional example.
It will be improved to about 1/2. Further, the power consumption is almost the same in the present invention and the conventional example. Therefore, by using the present invention, the propagation delay time can be greatly improved without increasing the power consumption.
以上述べてきた実施令はベースをGaAs，エミッタをAl
0.3Ga0.7Asで形成した場合であるが、エミッタのＡｌの
モル非が０．３以外の場合はもちろんベース領域・エミ
ッタ領域を他の半導体の組合せ、例えば、InGaAsとIn
p，InGaAsとInAlAs，GeとGaAs，SiとGaP等で形成する場
合にも本発明は同様に適用されるものである事は言うま
でもない。The implementation order described above uses GaAs for the base and Al for the emitter.
This is a case of forming with 0.3 Ga 0.7 As, but when the mole ratio of Al of the emitter is other than 0.3, of course, the base region / emitter region is combined with another semiconductor such as InGaAs and In.
It goes without saying that the present invention is similarly applied to the case of forming with p, InGaAs and InAlAs, Ge and GaAs, Si and GaP and the like.
また回路形式についてはCMLについて述べてきたが、他
の非飽和型の回路形成例えば第５図に示すNTL（Non-Thr
eshhold logic）、第６図に示すCMLにエミッタフォロワ
（Trf及びＲEF）がついた回路形式等を用いても同様な
効果があることは言うまでもない。なお第５図及び第６
図において、ＲLは負荷抵抗である。As for the circuit type, CML has been described, but other non-saturation type circuit formation such as NTL (Non-Thr
It is needless to say that the same effect can be obtained by using a circuit form in which the emitter follower (Trf and R EF ) is added to the CML shown in FIG. 6). 5 and 6
In the figure, R L is a load resistance.
第１図は本発明一実施例を説明するための図、第２図は
従来構造のヘテロ接合バイポーラトランジスタを示す
図、第３図は寄生外部ベース面積が変化したときの従来
例と本発明の伝播遅延時間tpdを関係を示す図、第４図
は寄生外部ベース面積が変わった場合のtpdと外部ベー
ス面積の関係を従来例と実施例の比較した示した図、第
５図及び第６図は本発明の他の実施例を説明するための
図である。 １……半絶縁性基板、 ２……ｎ+型GaAs層、 ３……ｎ型AlGaAs層、２０ ……エミッタ領域、 ４……ｎ型AlxGa1-xAs層（遷移領域）、 ５……ｐ+型AlGaAs層、 ６……ｐ+型GaAsベース層、 ７……ｎ型GaAs層、 ８……ｎ+GaAs層、３０ ……ベース領域、 ６ａ……外部ベース領域、 ９……素子間分離領域、 １０……ベース領域とエミッタ領域間の分離領域、 １１……層間絶縁膜、 １２……エミッタ電極、 １３……ベース電極、 １４……コレクタ電極、 １５……１層目の配線、 １６……２層目の配線、 １７……負荷抵抗。FIG. 1 is a diagram for explaining one embodiment of the present invention, FIG. 2 is a diagram showing a heterojunction bipolar transistor having a conventional structure, and FIG. 3 is a conventional example when the parasitic external base area is changed and the present invention. FIG. 4 is a diagram showing the relationship of the propagation delay time tpd, FIG. 4 is a diagram showing the relation between the tpd and the external base area when the parasitic external base area is changed, comparing the conventional example with the example, FIG. 5, and FIG. FIG. 8 is a diagram for explaining another embodiment of the present invention. 1 ... semi-insulating substrate, 2 ... n + type GaAs layer, 3 ... n type AlGaAs layer, 20 ... emitter region, 4 ... n type Al x Ga 1-x As layer (transition region), 5 ...... p + type AlGaAs layer, 6 …… p + type GaAs base layer, 7 …… n type GaAs layer, 8 …… n + GaAs layer, 30 …… base region, 6 a …… external base region, 9 …… Isolation region between elements, 10 ... Isolation region between base region and emitter region, 11 ... Interlayer insulating film, 12 ... Emitter electrode, 13 ... Base electrode, 14 ... Collector electrode, 15 ... First layer Wiring, 16 ... Second layer wiring, 17 ... Load resistance.
Claims (7)
このエミッタ領域とｐｎ接合を構成し、且つい前記エミ
ッタ領域よりバンドギャップの狭い第２種半導体で構成
したベース領域と、このベース領域とｐｎ接合を構成
し、且つ前記第１種半導体又は第２種半導体で構成した
コレクタ領域とを有し、前記ベース領域と前記エミッタ
領域間のｐｎ接合面積を前記ベース領域と前記コレクタ
領域間のｐｎ接合面積より広く形成したヘテロ接合バイ
ポーラトランジスタを、基板上で素子分離して複数設
け、各トランジスタを配線接続して非飽和型論理回路を
構成したことを特徴とするバイポーラ集積回路。1. An emitter region made of a first type semiconductor,
A base region which forms a pn junction with the emitter region and which is made of a second type semiconductor having a bandgap narrower than that of the emitter region; and a pn junction which forms a pn junction with the base region, and the first type semiconductor or the second type semiconductor. A heterojunction bipolar transistor having a collector region formed of a seed semiconductor and having a pn junction area between the base region and the emitter region wider than a pn junction area between the base region and the collector region is formed on the substrate. A bipolar integrated circuit characterized in that a plurality of elements are provided separately and each transistor is connected by wiring to form a non-saturated logic circuit.
徴とする特許請求の範囲第１項記載のバイポーラ集積回
路。2. The bipolar integrated circuit according to claim 1, wherein the substrate is made of a semi-insulating semiconductor.
ランジスタを、基板側からエミッタ領域，ベース領域，
コレクタ領域の順に形成して構成することを特徴とする
特許請求の範囲第１項記載のバイポーラ集積回路。3. A heterojunction bipolar transistor provided on a substrate, which comprises an emitter region, a base region, and
The bipolar integrated circuit according to claim 1, wherein the bipolar integrated circuit is formed by forming collector regions in this order.
なくともベース領域とｐｎ接合を構成する部分であるこ
とを特徴とする特許請求の範囲第１項記載のバイポーラ
集積回路。4. The bipolar integrated circuit according to claim 1, wherein the first-type semiconductor forming the emitter region is at least a portion forming a pn junction with the base region.
ミッタ領域の第１種半導体はAlGaAsであることを特徴と
する特許請求の範囲第４項記載のバイポーラ集積回路。5. The bipolar integrated circuit according to claim 4, wherein the first-type semiconductor in the emitter region of the portion forming the pn junction with the base region is AlGaAs.
ミッタ領域の第１種半導体はAlGaAsであって、そのAlGa
AsのAlの組成が変化する遷移領域とAlの組成が固定して
いる領域の２層で構成した特徴とする特許請求の範囲第
４項記載のバイポーラ集積回路。6. A first-type semiconductor of an emitter region of a portion forming a pn junction with a base region is AlGaAs, and AlGa
5. A bipolar integrated circuit according to claim 4, wherein the bipolar integrated circuit is composed of two layers of a transition region where the Al composition of As changes and a region where the Al composition is fixed.
クで構成したことを特徴とする特許請求の範囲第１項記
載のバイポーラ集積回路。7. The bipolar integrated circuit according to claim 1, wherein the non-saturation type logic circuit is constituted by a current mode logic.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60203328A JPH0614536B2 (en) | 1985-09-17 | 1985-09-17 | Bipolar integrated circuit |
| US06/878,661 US4739379A (en) | 1985-09-17 | 1986-06-26 | Heterojunction bipolar integrated circuit |
| EP86305164A EP0218319B1 (en) | 1985-09-17 | 1986-07-03 | Heterojunction bipolar integrated circuit |
| DE8686305164T DE3672029D1 (en) | 1985-09-17 | 1986-07-03 | BIPOLAR INTEGRATED CIRCUIT WITH HETEROU TRANSITIONS. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60203328A JPH0614536B2 (en) | 1985-09-17 | 1985-09-17 | Bipolar integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6265357A JPS6265357A (en) | 1987-03-24 |
| JPH0614536B2 true JPH0614536B2 (en) | 1994-02-23 |
Family
ID=16472189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60203328A Expired - Fee Related JPH0614536B2 (en) | 1985-09-17 | 1985-09-17 | Bipolar integrated circuit |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4739379A (en) |
| EP (1) | EP0218319B1 (en) |
| JP (1) | JPH0614536B2 (en) |
| DE (1) | DE3672029D1 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2590842B2 (en) * | 1986-10-29 | 1997-03-12 | ソニー株式会社 | Heterojunction bipolar transistor |
| JPS63156367A (en) * | 1986-12-20 | 1988-06-29 | Fujitsu Ltd | Level shift diode |
| JPS63224358A (en) * | 1987-03-13 | 1988-09-19 | Toshiba Corp | High frequency power amplifier |
| US4984048A (en) * | 1987-07-10 | 1991-01-08 | Hitachi, Ltd. | Semiconductor device with buried side contact |
| US5124270A (en) * | 1987-09-18 | 1992-06-23 | Kabushiki Kaisha Toshiba | Bipolar transistor having external base region |
| US5063427A (en) * | 1987-10-13 | 1991-11-05 | Northrop Corporation | Planar bipolar transistors including heterojunction transistors |
| JPH03218681A (en) * | 1989-11-24 | 1991-09-26 | Toshiba Corp | Hetero-junction bipolar transistor |
| JP2553723B2 (en) * | 1989-12-25 | 1996-11-13 | 三菱電機株式会社 | Compound semiconductor integrated circuit device |
| JP3123940B2 (en) * | 1997-03-27 | 2001-01-15 | 日本電気株式会社 | Field effect transistor and method of manufacturing the same |
| JPH10294491A (en) * | 1997-04-22 | 1998-11-04 | Toshiba Corp | Semiconductor light-emitting element, manufacture thereof and light-emitting device |
| DE19912950B4 (en) * | 1999-03-23 | 2006-05-24 | Kasper, Erich, Prof. Dr.rer.nat. | Semiconductor device, with three successive layers of alternating doping type integrated circuit with such a semiconductor device and method for producing such a semiconductor device |
| US6833277B2 (en) * | 2002-01-24 | 2004-12-21 | Massachusetts Institute Of Technology | Method and system for field assisted statistical assembly of wafers |
| US20040224473A1 (en) * | 2003-05-06 | 2004-11-11 | Lucent Technologies Inc. | Using metal peatures to align etches of compound semiconductors |
| JP2018142562A (en) * | 2017-02-24 | 2018-09-13 | 株式会社村田製作所 | Semiconductor device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3638202A (en) * | 1970-03-19 | 1972-01-25 | Bell Telephone Labor Inc | Access circuit arrangement for equalized loading in integrated circuit arrays |
| US4063271A (en) * | 1972-07-26 | 1977-12-13 | Texas Instruments Incorporated | FET and bipolar device and circuit process with maximum junction control |
| US4236294A (en) * | 1979-03-16 | 1980-12-02 | International Business Machines Corporation | High performance bipolar device and method for making same |
| US4573064A (en) * | 1981-11-02 | 1986-02-25 | Texas Instruments Incorporated | GaAs/GaAlAs Heterojunction bipolar integrated circuit devices |
| US4586071A (en) * | 1984-05-11 | 1986-04-29 | International Business Machines Corporation | Heterostructure bipolar transistor |
| US4570330A (en) * | 1984-06-28 | 1986-02-18 | Gte Laboratories Incorporated | Method of producing isolated regions for an integrated circuit substrate |
| US4649411A (en) * | 1984-12-17 | 1987-03-10 | Motorola, Inc. | Gallium arsenide bipolar ECL circuit structure |
-
1985
- 1985-09-17 JP JP60203328A patent/JPH0614536B2/en not_active Expired - Fee Related
-
1986
- 1986-06-26 US US06/878,661 patent/US4739379A/en not_active Expired - Lifetime
- 1986-07-03 EP EP86305164A patent/EP0218319B1/en not_active Expired
- 1986-07-03 DE DE8686305164T patent/DE3672029D1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0218319B1 (en) | 1990-06-13 |
| EP0218319A1 (en) | 1987-04-15 |
| JPS6265357A (en) | 1987-03-24 |
| US4739379A (en) | 1988-04-19 |
| DE3672029D1 (en) | 1990-07-19 |
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