JPH0614349B2 - Real-time video processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a real-time signal processor that realizes digital signal processing such as digital filtering and high-efficiency coding with software for moving picture signals such as television signals.

(Prior art and its problems) The advantage of real-time digital signal processing is that it is possible to realize a filter and modulator / demodulator with high accuracy or high stability, which cannot be realized by analog technology. The time-varying adaptive filter can be easily realized. Furthermore, by incorporating the results of digital LSI technology, which has been rapidly developing in recent years, it is possible to reduce the size and power consumption of real-time digital signal processing circuits, and gradually replace analog circuits and apply them to higher functionality. Is progressing to. For further details on the advantages of digital signal processing, see the December 1982 issue of the Institute of Electronics and Communication Engineers, 1280 to 1284 (Reference 1).
Please refer to.

Digital signal processing, which has many advantages in this way, also has the drawback of requiring a huge amount of calculation. In order to perform real-time signal processing, it is necessary to perform digital signal processing given within one sampling period per one sampled input signal sample. For example, for telephone speech (8 KHz sampling) When the cyclic digital filter processing is performed, 8 multiplications and 8 additions are required in 125 microseconds. Therefore, the frequency bandwidth is 1 compared to telephone voice.
A circuit that is 1000 times or more faster than a telephone voice signal processing circuit is required to perform signal processing on a moving image signal that is as wide as 000 times or more and therefore has a sampling period of 1/1000 or less.

For the above reasons, high-level digital signal processing can be performed only for signals in the audio region at present, and moving image signals are currently limited to very simple processing.

Regarding digital signal processing for signals in the voice domain, we want to perform high-speed digital signal processing.
Often, various parameters are changed or part of the signal processing algorithm is changed. Therefore, there is a strong demand for a signal processing device whose algorithm and parameters can be changed by software. Conventional hardware for performing digital signal processing by software is the IEEE Journal of Solid States Circuit.
s) There are signal processors, etc., described in SC-16 Vol. 4, No. 4 (August 1981), pages 372 to 376 (reference 2), and a typical application example of this signal processor is EE. Proceedings of International Confere published on Proceedings of International Confere
nce on Acoustics Speech of Signal Processing) 9
32 kbps A published on pages 60 to 963 (reference 3)
There is DPCM, but it is still targeted for telephone voice processing.

In such a conventional processor format, it is not possible to easily expect a speedup of 1000 times or more even if the speed of the arithmetic circuit is increased. Therefore, it is possible to perform a high-level digital signal processing such as that which can be performed with a voice signal on a moving image. A processor that can be controlled by software could not be realized.

(Object of the Invention) An object of the present invention is to provide a software-controlled circuit capable of performing advanced digital signal processing on a moving image signal such as a television signal.

(Structure of the Invention) A structure of the present invention is a control unit for generating a predetermined input partial screen position signal and output partial screen position signal from a sync signal for notifying the beginning of one screen of a moving picture signal such as a television signal, Section, which receives an input partial screen position signal from the input section, and which receives the partial screen signal designated by the input partial screen position signal of the separately input moving image signal, and the capturing section which is connected to the capturing section. The processing unit that performs signal processing until the start of capturing of the next screen, and the output side of the processing unit that is connected to the output side of the processing unit for the moving image signal captured in A plurality of unit processors, each of which is composed of an output unit which outputs the stored processing result at a partial screen position designated by the output partial screen position signal input from the control unit; An input bus for supplying the sync signal and the moving image signal to each of them, and an output bus for transmitting the output partial image signal output from each of the plurality of unit processors, By making sure that the output partial screen does not overlap between each unit processor, and allowing the predetermined input partial screen to overlap,
It is characterized by eliminating the information exchange between each unit processor and realizing signal processing with a delay of one screen.

(Principle of the Invention) According to the principle of the present invention, one screen (frame) is divided into a plurality of partial screens, and one unit signal processor is allocated to each partial screen, whereby a moving image is displayed by a plurality of unit signal processors. Is to be processed.

First, if it is treated as a one-dimensional signal suitable for transmission of a moving image signal, it is necessary to sample at about 10 MHz as described above. If a moving image signal is treated as a two-dimensional signal called a screen, for example, a television signal only sends 30 screens per second. In other words, if one screen can be processed in 33 milliseconds, a delay of one screen occurs, but the real-time property is maintained.

A plurality of unit signal processors are prepared to process the sampled signal for one screen, an area to be processed is preset between the unit signal processors, and each unit signal processor is assigned an assigned process. The moving image signal required for the partial screen area is selectively fetched.
In this case, the capture partial screen is generally larger than the processing partial screen.

For example, a two-dimensional sampling signal at coordinates (i, j) is x (i, j
j) and consider passing this two-dimensional signal through a filter of impulse response {h (i, j)}. Here, it is assumed that the output y (i, j) belongs to the sub-screen O defined below, and the impulse response h (i, j) belongs to the section P.

O = {(i, j):-NiN, -NjN} P = {(i, j):-i, -j} (1) The filter operation at this time follows the following formula.

Therefore, the input signal {x
The interval Q of (i, j)} is Q = {(i, j): − (M + N) i (M + N), − (M + N) j (M + N)} from Expression (1) and Expression (2) (3) Becomes FIG. 2 shows the relationship between the data capture screen Q and the processing screen O, and shows a square capture image section Q on one side 2 (M + N) and a square processed image section O on one side 2N.

The expression (2) is called a convolution operation, but other than this, the correlation operation can be expressed almost like the expression (2), and the relationship between the captured image and the processed image can be expressed as shown in FIG.

As described above, in the convolution and the correlation calculation, which are basic operations in digital signal processing, the areas of the captured image and the processed image are different, but if the area of the processed image is fixed, the information of the entire screen becomes unnecessary. Therefore, one screen is divided into a plurality of partial screens, a plurality of unit signal processors that process each partial screen are assigned, and each unit signal processor acquires the signals for the acquired partial screens, and the signal processing is performed individually. Can be done independently with the unit signal processor.
That is, in each unit signal processor, the processing of the assigned partial screen is one frame sampling period 33 described above.
Processing can be performed in milliseconds, and real-time video processing can be performed by operating many unit signal processors in parallel.

(Example) Next, the Example of this invention is described, referring drawings.

FIG. 1 shows an embodiment of the present invention when four unit signal processors are used. The synchronizing signal input terminal 1, the moving image signal input terminal 2, the unit signal processors 3, 4, 5, 6, and the synchronizing signal output terminal 7 are shown. , A video signal output terminal 8,
The unit signal processors 3, 4, 5 and 6 each have an acquisition unit 1
0, a processing unit 11, a reading unit 12, and a control unit 13. The capturing unit 10 and the reading unit 12 are storage circuits, and the details of the processing unit 11 and the control unit 13 will be described later.

The synchronization signal input from the terminal 1 is input to the control unit 13 of each of the unit signal processors 3, 4, 5 and 6. The control unit 13 identifies the time when a signal belonging to a pre-assigned capture partial screen area is input to the terminal 2 from the input synchronization signal, and notifies the capture unit 10 as a capture signal. Capture part
Reference numeral 10 captures and stores the moving image signal input to the terminal 2 by the capture signal transmitted from the control unit 13.

The control unit 13 also transmits an execution signal to the processing unit 11 when the signal of the predetermined capture partial screen area is input based on the synchronization signal input from the terminal 1, and the processing unit 11 is input from the control unit. Predetermined digital signal processing by the execution signal, for example, the convolution calculation of the above-described formula (2) is performed on the captured moving image signal stored in the capturing unit 10, and the calculation result is written to the reading unit 12. .

The control unit 13 further detects a predetermined processing partial screen area output time point from the synchronization signal input from the terminal 1, and when the processing partial screen area is reached, transmits an output command signal to the output unit 12, and the output unit 12 controls the control unit. The processed data written and processed by the processing unit 11 is sequentially output from the output command signal from 13.

FIG. 3 shows the take-in signal, the execution signal, and the output command signal used in the unit signal processors 3 and 4 in the moving picture processor having the configuration of FIG. In order to simplify the explanation, it is considered that the moving image signal used in FIG. 3 has undergone the scanning line conversion in which the scan signal over the entire screen is rearranged for each partial screen.

The sync signal (FIG. 3 (a)) applied to the terminal 1 signals the start of one screen. In the unit signal processor 3 that processes the first first divided screen, the capture signal 1 generated by the control unit 13 (Fig. 3 (b)) rises at the same time as the synchronization signal, and continues to instruct the acquisition until the acquisition area ends. Further, the control unit 13 sends the execution signal 1 to the processing unit 11 after the end of the acquisition.
Communicate (Fig. 3 (c)). As a result, the processing unit 11 may perform signal processing from the rising edge of the execution signal 1 to the next rising edge of the fetch signal 1. The control unit 13 also transmits the output command signal 1 (FIG. 3 (d)) to the output unit 12. This output command signal is also considered as a position signal of the processing partial screen of the unit signal processor 3. As described in FIG. 2, since the acquisition partial screen is generally larger than the processing partial screen, the acquisition signal 1 is turned on in the corresponding signals in FIGS. 3 (b) and 3 (d). The time during which it is present is longer than the output command signal 1.

The signals shown in FIGS. 3 (b '), (c'), and (d ') are a take-in signal, an execution signal, and an output command signal of the unit processor 4 which processes the second divided screen, respectively. The relationship between FIGS. 3 (b ') and 3 (d') comes from the difference between the capture partial screen and the processing partial screen shown in FIG. The processing time allowed for the processing unit 11 of the unit processor 4 is from the rising of the signal in FIG. 3 (b ') to the rising of the output command signal, and this length is the same as the time allowed for the processing unit 11 of the unit processor 3. is there.

Although the control signals for only the unit processors 3 and 4 have been described above with reference to FIG. 3, the same applies to the unit processors 5 and 6. Since the output time of each unit processor is only when each output command signal is on, the processed moving image signal is output to the output terminal 8 of FIG. 1 in the format shown in FIG. 3 (e). However, here, in FIG. 3 (e), A, B,
The portions marked C and D are unit signal processors 3 and 3, respectively.
It means the output from 4, 5, and 6. Therefore, the processed moving image signal is continuously output from the terminal 8.

FIG. 4 shows an embodiment of the control unit 13 used in the unit signal processors 3, 4, 5 and 6, and the synchronization signal input terminal 2
0, clock signal input terminal 21, capture signal output terminal 22, execution signal output terminal 23, output command signal output terminal 24, column counter 25, row counter 26, read-only memories 27, 28, gate circuits 29, 30, 31. It consists of

The read-only memory 27 is a 3-bit output. The first bit is programmed to output 1 if the value of the input address matches the line number of the capture screen, and to output another zero. Is programmed to output 1 when the value of the input address is the line number on the screen at the time when you want to output the execution command, and 0 for the other, and the third bit is the processing screen 1 that matches the line number of
, And others are programmed to output zero.

Similarly, the read-only memory 28 has a 3-bit output,
Bits are programmed to output 1 if the input address value matches the column number on the capture screen, and 0 for the others, and the 2nd bit indicates the time when the input address value outputs the execution command. 1 for the column number on the screen,
The others are programmed to output zero, and the third bit is programmed to output 1 when the value of the input address matches the column number of the processing screen and the other outputs zero.

When the synchronizing signal is input from the terminal 20, the column counter 25 and the row counter 26 are reset and both output zero.
Assuming that the control unit of the unit processor 3 for processing the first section in FIG. 1 is considered, the read-only memory 28 indicates the first bit indicating the capture screen and the output screen by the value 0 of the column counter. Output "1" in the 3rd bit,
The second bit is "0". Further, when the value of the row counter is 0, the read-only memory 27 outputs "1" at the first bit indicating the capture screen and the third bit indicating the output screen, and the second bit is "0". For this reason, the gates 29, 30, and 31 are respectively "1" at the acquisition signal output terminal 22 and the execution signal output terminal.
“0” is output to 23 and “1” is output to the output command output terminal 24.

Every time a sampled moving image signal is applied to the terminal 2 in FIG. 1, a signal is applied to the clock terminal 21 in FIG. 4 to advance the column counter 25, and when the column counter 25 completes one column of the entire screen, the row counter is counted. Step 26 forward and the row counter 25 will return to zero. Therefore, the first bit of the read-only memories 28 and 27 outputs "1" as long as the column counter 25 and the row counter 26 indicate the columns and rows belonging to the capture screen, and the gate 29 captures the capture screen. “1” is output to the terminal 22 with respect to the sample position belonging to.

Similarly, the read-only memory 28, only when the column counter 25 and the row counter 26 indicate the values of the column and the row to instruct the start of processing
27 outputs "1", and at this time, the gate 30 outputs "1" to the terminal 23 as an execution signal.

Similarly, when the column counter 25 and the row counter 26 indicate the columns and rows corresponding to the output screen, the read-only memories 28 and 27 each output "1", and as a result, the gate 31 outputs "1" to the terminal 24 as an output command signal. 1 ”is output.

FIG. 5 shows the unit signal processors 3, 4, 5 of FIG.
6 is an example of a processing unit in 6 and includes a signal processor 40, a register 41, a gate 42, and an input terminal 4 from the capturing unit.
3, address output terminal 44 to the capture section, output terminal 45 to the output section, address output terminal 46 to the output section, write signal output terminal 47 to the output section 47 execution signal input terminal 48 capture section output disable signal It is composed of the output terminal 49. It is assumed that the signal processor 40 uses the μPD7720 manufactured by NEC described in Reference 2. The μPD7720 is a signal processing processor that has a unique bus configuration and has a multiplier and an adder inside, but the details are given in Reference 2. μPD772
0 is designed so that the interrupt processing can be operated when a signal arrives at the interrupt input terminal (INT), and further has programmable output bits P1 and P2. Input / output is done via a bidirectional parallel bus (D), and when a signal is coming to the write terminal (W), it is used as an input direction bus, and when a signal is not coming to the write terminal (W), it is output direction. Used as a bus.

Now, the execution signal from the control unit 13 in FIG. 1 is the terminal in FIG.
Upon joining 48, the signal processor 40 starts digital signal processing as an interrupt processing. For this reason, the capture part of FIG.
Input data from 10 is required. First, the required address is prepared in the port D and "1" is output from the bit output port P1. At this time, the gate 42 outputs "0", the data of the port D can be output from the signal processor 40 to the outside, and the address is stored in the register 41. Then P
When 1 is set to "0", the content of the register 41 is transmitted to the capturing unit 10 via the terminal 44, and the corresponding data is input from the terminal 43 to the port "D".

Similarly, in order to transfer the data processed by the signal processor 40 to the output unit 12, the address of the output unit 12 is specified. Therefore, the required address is prepared in the port D and the bit output port P1 outputs “1”. Is output and the address is written in the register 41. This address is transmitted to the output unit 12 via the output terminal 46. Next, the processed data is prepared in the port D and "1" is output from the bit output port P2. At this time, the gate 42 outputs "0", the port D is in a state of being output from the signal processor 40 to the outside, and the input unit is informed of the output inhibition via the output terminal 49.
The data on the port is transmitted to the output section via the terminal 45. In addition, "1" of the bit output port P2 is transmitted to the output section through the terminal 47, and commands the writing of the data transmitted from the terminal 45 to the output section.

The present invention can be implemented as described above.

In the above-described embodiment, the read-only memory is used for the control unit, but it is possible to dynamically change the positions of the predetermined captured partial image and processed partial image by replacing the read-only memory with a random access memory or the like. This is part of the present invention.

Although the signal generated by the control unit is set at the end of the capture signal, it may be set in the middle of the capture signal by a program, and such a change is also included in the present invention.

Further, in the present invention, the control unit for designating the positions of the captured partial image and the processed partial image is dispersedly provided in each unit signal processor, but these are centralized and only the control signal is supplied to each unit signal processor. The method of dispensing is also within the invention.

(Effect of the present invention) As has been seen above, according to the present invention, a plurality of unit signal processors do not communicate a moving image signal with each other, and have no effect on digital signal processing at the boundary between unit signal processors. It is possible to realize digital signal processing without giving.

Therefore, real-time digital signal processing can be applied to a moving image signal by using many unit signal processors.

Also, the unit signal processors placed in parallel differ only in the designation of the capture screen and the processing screen, and the processing section of each unit signal processor should be processed by the same digital / signal processing program, so program development is simple. It is sufficient to perform only one unit signal processor, and the programs of the other unit signal processors may be copies of the developed program, so that the program work becomes easy.

Further, since only the areas of the capture screen and the processing screen are different between the unit signal processors, many unit signal processors are provided in parallel to prohibit the output of the unit signal processor in which a failure has occurred, and Since the failure can be recovered by changing only the definitions of the capture screen and the processing screen, it can be used as a highly reliable signal processor.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the principle of the present invention, FIG. 3 is a diagram showing operation timing of FIG. 1, and FIG. 4 is a part of FIG. FIG. 5 is a diagram showing a part of FIG. 1. In the figure, 1 ... Sync signal input terminal, 2 ... Video signal input terminal,
3, 4, 5, 6 ... Unit signal processor, 8 ... Moving image output terminal, 10 ... Capture section, 11 ... Processing section, 12 ... Read section, 13 ... Control section.

Claims (1)

[Claims] 1. A control unit for generating a predetermined input partial screen position signal and output partial screen position signal from a sync signal for notifying the beginning of one screen of a moving image signal such as a television signal, and the input partial screen from the control unit. A position signal is input, and a capturing unit that captures the partial screen signal designated by the input partial screen position signal of the separately input moving image signal; and a capturing unit that is connected to the capturing unit and captured by the capturing unit. A processing unit that performs signal processing until the start of capturing the next screen for the moving image signal, and an output side of the processing unit that is connected to store the processing result of the processing unit and separately input from the control unit. A plurality of unit processors each including an output unit that outputs the accumulated processing result at a partial screen position designated by the output partial screen position signal; and the synchronization signal to each of the plurality of unit processors. And an input bus for supplying the moving image signal, and an output bus for transmitting the output partial image signal output from each of the plurality of unit processors, and the output partial screen supplied to the plurality of unit processors. A real-time moving image processor characterized in that the position signals do not overlap between the unit processors, and the input partial screen position signals allow overlap.