JPH0614012A - Data transmission system - Google Patents
Data transmission systemInfo
- Publication number
- JPH0614012A JPH0614012A JP16661292A JP16661292A JPH0614012A JP H0614012 A JPH0614012 A JP H0614012A JP 16661292 A JP16661292 A JP 16661292A JP 16661292 A JP16661292 A JP 16661292A JP H0614012 A JPH0614012 A JP H0614012A
- Authority
- JP
- Japan
- Prior art keywords
- data
- transmission
- latch
- data transmission
- transmitted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、伝送誤りを少なくする
データ伝送方式に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system which reduces transmission errors.
【０００２】[0002]
【従来の技術】機器の動作を任意に設定可能なユーザプ
ログラムに従ってシーケンシャルに制御するプログラマ
ブルコントローラでは、プログラマブルコントローラ同
士あるいは周辺機器との間でデータ伝送が行われる。2. Description of the Related Art In a programmable controller that sequentially controls the operation of devices according to a user program that can be arbitrarily set, data transmission is performed between programmable controllers or peripheral devices.
【０００３】[0003]
【発明が解決しようとする課題】この種のデータ伝送に
際して、データ伝送路では電磁ノイズなどにさらされ、
伝送途中でデータに誤りを生じ、機器を誤動作させると
いう問題が生じる。本発明は上述の点に鑑みて為された
ものであり、その目的とするところは、伝送誤りを少な
くできるデータ伝送方式を提供することにある。During this type of data transmission, the data transmission line is exposed to electromagnetic noise,
There is a problem that an error occurs in the data during the transmission and the device malfunctions. The present invention has been made in view of the above points, and an object thereof is to provide a data transmission method capable of reducing transmission errors.
【０００４】[0004]
【課題を解決するための手段】本発明では、上記目的を
達成するために、データの送信側に送信データを夫々ラ
ッチするＦＩＦＯ型の記憶手段を設け、データ送信時に
各記憶手段に夫々同一の伝送データをラッチさせ、受信
側からの要求に応じて各記憶手段のラッチデータを夫々
パラレル伝送し、受信側で受信データの比較を行い、受
信データが一致する場合に受信データを有効とし、不一
致の場合には受信データを無効とする。According to the present invention, in order to achieve the above object, a FIFO type storage means for latching transmission data is provided on the data transmission side, and the same storage means is provided for each storage means at the time of data transmission. The transmission data is latched, and the latch data of each storage means is transmitted in parallel in response to the request from the receiving side, and the receiving data is compared on the receiving side. If the receiving data match, the receiving data is validated and does not match. In case of, the received data is invalid.
【０００５】なお、上記記憶手段の代わりにデータラッ
チ手段を用いてもよく、データをシリアル伝送する場合
にも適用できる。A data latch means may be used in place of the above storage means, and can be applied to the case of serially transmitting data.
【０００６】[0006]
【作用】本発明は、上述のように構成することにより、
同一データを繰り返し伝送し、そのデータの一致判定に
より伝送誤りがないことを検知して、そのデータを取り
込むようにし、例えばプログラマブルコントローラなど
に用いた場合に、データ伝送路が電磁ノイズなどにさら
されてデータに誤りが生じても、機器を誤動作させると
いう問題が生じないようにする。The present invention has the above-mentioned configuration,
The same data is repeatedly transmitted, and it is detected that there is no transmission error by matching the data, and the data is taken in.For example, when used in a programmable controller, the data transmission line is exposed to electromagnetic noise. Even if an error occurs in the data, the problem of malfunctioning the device does not occur.
【０００７】[0007]
【実施例】図１に本発明の一実施例を示す。本実施例で
もプログラマブルコントローラ同士あるいは周辺機器と
の間でデータ伝送を行う場合の方式を示す。本実施例で
は、送信側のプログラマブルコントローラに複数のＦＩ
ＦＯ型の記憶部１1 ，１2を設け、この記憶部１1 ，１
2 に他のプログラマブルコントローラや周辺機器（例え
ば、制御される機器としてのモータを駆動する駆動回路
など）にデータ伝送を行う場合に、同一の伝送データを
記憶させる。なお、このＦＩＦＯ型の記憶部１1 ，１2
としては、ＣＰＵが備えるレジスタの一種のＦＩＦＯス
タックなどを用いることができ、本実施例の場合に２個
の記憶部１1 ，１2 を用いてある。但し、記憶部１は必
ずしも２個である必要はなく、２個以上であってもよ
い。FIG. 1 shows an embodiment of the present invention. This embodiment also shows a method for performing data transmission between programmable controllers or peripheral devices. In this embodiment, a plurality of FIs are provided in the programmable controller on the transmission side.
FO-type memory 1 1, 1 2 arranged in this storage unit 1 1, 1
When data is transmitted to another programmable controller or a peripheral device (for example, a drive circuit that drives a motor as a controlled device), the same transmission data is stored in 2. In addition, the FIFO type storage units 1 1 and 1 2
For this, a kind of FIFO stack of registers included in the CPU can be used, and in the case of this embodiment, two storage units 1 1 and 1 2 are used. However, the number of storage units 1 is not necessarily two, and may be two or more.
【０００８】受信側のプログラマブルコントローラある
いは周辺機器側には、上記送信側のプログラマブルコン
トローラからの繰り返し伝送されるデータを夫々ラッチ
すると共に、夫々のデータの比較を行うデータ比較器２
を設け、このデータ比較器２による一致判定が行われた
ときに、そのデータをラッチするラッチ回路３を備えて
いる。ここで、データ比較器２は送信側に対してデータ
を送信させるための信号を送信器側に送信する機能を備
え、上記ラッチ回路３に記憶されたデータを用いて受信
側のプログラマブルコントローラあるいは周辺機器によ
る処理が開始される。The receiving side programmable controller or peripheral device side latches the data repeatedly transmitted from the transmitting side programmable controller, and compares the respective data with each other.
And a latch circuit 3 for latching the data when the data comparator 2 makes a coincidence determination. Here, the data comparator 2 has a function of transmitting a signal for transmitting data to the transmitter side to the transmitter side, and uses the data stored in the latch circuit 3 to program the programmable controller on the receiver side or peripherals. The processing by the device is started.
【０００９】本実施例では、送信データを一旦２つの記
憶部１1 ，１2 に同時に記憶させ、受信側からの信号に
応じて記憶部１1 のデータを受信側に送信し、次い受信
側から与えられる信号に応じて記憶部１1 のデータを受
信側に送信する。これら受信側ではデータ比較器２でデ
ータを比較し、一致しておればラッチ回路３にラッチす
る。逆に、不一致であれば、そのデータは無効としてラ
ッチ回路３にはラッチしない。このようにすれば、デー
タ伝送路が電磁ノイズなどにさらされてデータに誤りが
生じても、機器を誤動作させるという問題が生じない。In this embodiment, the transmission data is temporarily stored in the two storage units 1 1 and 1 2 at the same time, the data in the storage unit 1 1 is transmitted to the reception side according to the signal from the reception side, and the next reception is performed. The data in the storage unit 1 1 is transmitted to the receiving side according to the signal given from the side. On the receiving side, the data comparator 2 compares the data, and if they match, the data is latched in the latch circuit 3. On the contrary, if they do not match, the data is invalid and is not latched in the latch circuit 3. In this way, even if the data transmission line is exposed to electromagnetic noise or the like and data has an error, the problem of malfunctioning the device does not occur.
【００１０】ところで、本実施例のように繰り返しデー
タの伝送を行うと、伝送時間が長くなるが、プログラマ
ブルコントローラなどの場合にはさほどに高速のデータ
伝送は要求されないので、システム動作を信頼性を高め
ることが重要であり、伝送時間の遅れはさほどに問題と
はならない。ところで、上述の場合にはＦＩＦＯスタッ
クなどのＦＩＦＯ型の記憶部１1 ，１2 を用いた場合に
ついて説明したが、図２に示すようにデータラッチ回路
１1’，１2 ’を用いてよく、さらにデータがシリアル
伝送される場合には、図３に示すようにシリアル伝送可
能なデータラッチ回路１1 ”，１2 ”を用いればよい。By the way, when data is repeatedly transmitted as in the present embodiment, the transmission time becomes long, but in the case of a programmable controller or the like, very high speed data transmission is not required, so that the system operation is made reliable. It is important to increase, and the delay of transmission time is not so problematic. By the way, in the above-mentioned case, the case where the FIFO type storage sections 1 1 and 1 2 such as the FIFO stack are used has been described. However, as shown in FIG. 2, the data latch circuits 1 1 ′ and 1 2 ′ may be used. When data is further transmitted serially, data latch circuits 1 1 ″ and 1 2 ″ capable of serial transmission as shown in FIG. 3 may be used.
【００１１】[0011]
【発明の効果】本発明は上述のように、データの送信側
に送信データを夫々ラッチするＦＩＦＯ型の記憶手段を
設け、データ送信時に各記憶手段に夫々同一の伝送デー
タをラッチさせ、受信側からの要求に応じて各記憶手段
のラッチデータを夫々パラレル伝送し、受信側で受信デ
ータの比較を行い、受信データが一致する場合に受信デ
ータを有効とし、不一致の場合には受信データを無効と
しているので、同一データを繰り返し伝送し、そのデー
タの一致判定により伝送誤りがないことを検知して、そ
のデータを取り込むことができ、例えばプログラマブル
コントローラなどに用いた場合に、データ伝送路が電磁
ノイズなどにさらされてデータに誤りが生じても、機器
を誤動作させるという問題が生じない。As described above, according to the present invention, the data transmission side is provided with the FIFO type storage means for latching the transmission data respectively, and the same transmission data is latched in each storage means at the time of data transmission, and the reception side is provided. In parallel, the latch data in each storage unit is transmitted in parallel according to the request from the storage device, and the received data is compared on the receiving side. If the received data match, the received data is validated, and if they do not match, the received data is invalidated. Therefore, the same data can be transmitted repeatedly, and it is possible to detect that there is no transmission error by the coincidence judgment of the data and take in the data. For example, when used for a programmable controller, the data transmission path is electromagnetic. Even if an error occurs in the data due to exposure to noise or the like, the problem of malfunctioning the device does not occur.
【図１】本発明の一実施例の要部の回路図である。FIG. 1 is a circuit diagram of a main part of an embodiment of the present invention.
【図２】他の実施例の要部の回路図である。FIG. 2 is a circuit diagram of a main part of another embodiment.
【図３】さらに他の実施例の要部の回路図である。FIG. 3 is a circuit diagram of a main part of still another embodiment.
１1 ，１2 記憶部 １1 ’，１2 ’，１1 ”，１2 ” データラッチ回路 ２ データ比較器1 1 , 1 2 storage unit 1 1 ', 1 2 ', 1 1 ", 1 2 " data latch circuit 2 data comparator
Claims (3)
チするＦＩＦＯ型の記憶手段を設け、データ送信時に各
記憶手段に夫々同一の伝送データをラッチさせ、受信側
からの要求に応じて各記憶手段のラッチデータを夫々パ
ラレル伝送し、受信側で受信データの比較を行い、受信
データが一致する場合に受信データを有効とし、不一致
の場合には受信データを無効として成ることを特徴とす
るデータ伝送方式。1. A FIFO type storage means for latching each transmission data is provided on a data transmission side, each storage means is made to latch the same transmission data at the time of data transmission, and each storage is stored in response to a request from a reception side. The latch data of the means are transmitted in parallel respectively, the received data is compared on the receiving side, the received data is validated when the received data match, and the received data is invalidated when they do not match. Transmission method.
段を用いて成ることを特徴とする請求項１記載のデータ
伝送方式。2. The data transmission method according to claim 1, wherein a data latch means is used instead of the storage means.
徴とする請求項１記載のデータ伝送方式。3. The data transmission system according to claim 1, wherein the data is transmitted serially.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16661292A JPH0614012A (en) | 1992-06-25 | 1992-06-25 | Data transmission system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16661292A JPH0614012A (en) | 1992-06-25 | 1992-06-25 | Data transmission system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0614012A true JPH0614012A (en) | 1994-01-21 |
Family
ID=15834541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16661292A Pending JPH0614012A (en) | 1992-06-25 | 1992-06-25 | Data transmission system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0614012A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100249171B1 (en) * | 1997-03-12 | 2000-03-15 | 김영환 | Method for detecting error in non-syncronus type data transmit and receive device |
| JP2013057525A (en) * | 2011-09-07 | 2013-03-28 | Seiko Epson Corp | Decryption method and decryption apparatus |
-
1992
- 1992-06-25 JP JP16661292A patent/JPH0614012A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100249171B1 (en) * | 1997-03-12 | 2000-03-15 | 김영환 | Method for detecting error in non-syncronus type data transmit and receive device |
| JP2013057525A (en) * | 2011-09-07 | 2013-03-28 | Seiko Epson Corp | Decryption method and decryption apparatus |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20010313 |