JPH06139179A - Logical semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the overhead of a CPU in a host at the time of inputting data and to remove an useless procedure. CONSTITUTION:When a semiconductor sets up a value in a data outputting use data register 2o from its own internal bus 1, the writing processing of the semiconductor device is detected by a read permission flag setting circuit 3R and a read permission flag in the circuit 3R is set up. When a CPU in an external host activates a chip selecting signal input terminal 9 and a read strobe terminal 10RSI in order to read out the contents of the register 2o, an access detecting circuit 5 in the semiconductor device detects an access from the CPU in the host, reads out the contents S7 of the read permission flag in the circuit 3R and outputs the read contents to a reading stand-by request signal output terminal 7. The terminal 7 is connected to a READY input terminal included in the CPU in the host to insert a wait cycle into the CPU in the host.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic semiconductor integrated circuit, and more particularly to a logic semiconductor integrated circuit which is connected to a central processing unit (hereinafter abbreviated as CPU) which operates as an external host to form an interface circuit.

[0002]

2. Description of the Related Art A block diagram for outputting data from a semiconductor device to an external circuit of a conventional example shown in FIG. 3 shows a read permission flag 18 indicating whether data can be output from the semiconductor device to the external circuit. It has in the register 17a.

Specifically, the read permission flag 18 is set by the interface circuit in the semiconductor device when the semiconductor device sets a value in the data register 2o for data output.

When the semiconductor device outputs data to an external circuit, the external host CPU first inputs the address for the status register 17 to the address input terminal 20 and then the chip select terminal 9 and the read strobe terminal. The contents of the status register 17a inside the semiconductor device are read by activating 10RSI.

Next, a program in the CPU of the host tests the value of the permission flag 18 contained in the read status register 17a, and if the semiconductor device cannot output data, the status read is repeated. .

If data can be output, the chip select terminal 9 and the read strobe terminal 10RSI are made active while the address indicating the data register 2o for data output is input to the address input terminal 20.
The value of the data register 2o for data output is read, and the output data from the semiconductor device is transferred to the CPU of the external host via the data output terminal 8o.

The block diagram for inputting data to the semiconductor device from the external circuit of another conventional example shown in FIG. 4 shows a permission register 21 which indicates whether data can be input from the external circuit to the semiconductor device. Hold in 17b.

Specifically, this permission flag 21 is set by the interface circuit in the semiconductor device when the semiconductor device reads the value of the data register 2i for data input therein.

When data is input to the semiconductor device from an external circuit, the external host CPU first inputs the address for the status register 17 to the address input terminal 20 and then the chip select terminal 9 and the write strobe terminal 10WSI. Is activated to read the contents of the status register 17b in the semiconductor device.

Next, the value of the permission flag 21 included in the status register 17b read by the program inside the CPU of the host is tested, and if the semiconductor device is in a state in which data cannot be input, status reading is repeated.

If data can be input, the chip select terminal 9 and the write strobe terminal 10WSI are activated while the address of the data register 2i for data input is input to the address input terminal 20 for data input. The value is written in the data register 2i, and the input data from the host CPU is transferred to the semiconductor device.

In the case of the semiconductor device shown in the example of FIG. 5, when the semiconductor device sets a value in the data register 2o for data output from the internal bus 1 of itself, the write processing of this semiconductor device is interrupted by the interrupt signal generating circuit 24. Is detected and the read request signal S25 to the CPU of the host is output from the interrupt output terminal 25.

Interrupt request signal S25 activated
Is a read process of the semiconductor device executed by the host CPU in the interrupt process, that is, a transfer between the data output data register 2o and the host CPU executed by activating the chip select terminal 9 and the read strobe terminal 10RSI. It becomes inactive by processing.

In the case of the semiconductor device shown in the example of FIG. 6, when the semiconductor device reads the value of the data register 2i for data input to its own internal bus 1, the interrupt signal generation circuit 24 detects the read processing of this semiconductor device. Host CPU
A write request signal S25 for the write is output from the interrupt output terminal 26.

Interrupt request signal S25 activated
Is a write process of the semiconductor device executed by the host CPU in the interrupt process, that is, a transfer between the data register 2i for data input and the host CPU, which is executed by activating the chip select terminal 9 and the write strobe terminal 10WSI. It becomes inactive by processing.

[0016]

In the conventional logic semiconductor integrated circuit shown in FIGS. 3 and 4, the semiconductor device is in a state capable of data input / output during data transfer processing between the CPU of the host and the semiconductor device. The contents of the status register indicating whether or not it is once read to the host CPU, and the host CP
U had to check with its own program, which had the drawback of increasing the overhead of data transfer.

Further, the conventional logic semiconductor integrated circuits shown in FIGS. 5 and 6 require an interrupt control circuit and an interrupt processing routine in the host CPU at the time of data transfer processing between the host CPU and the semiconductor device. There is a drawback that the amount of wear increases and the overhead of data transfer increases.

It is an object of the present invention to provide a logic semiconductor integrated circuit which reduces the overhead of the CPU of the external host when data is input and eliminates unnecessary procedures.

[0019]

A logic semiconductor integrated circuit according to the present invention is connected to a central processing unit which operates as a host placed outside to form an interface circuit, and the central processing unit controls the control. In a privileged logic semiconductor integrated circuit, a permission flag setting circuit that stores a permission flag that notifies whether internal data input / output can be performed, and the state of the permission flag is changed by an access signal from the external circuit. And a terminal for outputting to.

[0020]

1 is a block diagram of an interface circuit for outputting data in a semiconductor device to an external circuit according to a first embodiment of the present invention. In this embodiment,
When the semiconductor device sets a value in the data register 2o for data output from its own internal bus 1, the read permission flag setting circuit 3R detects the write processing of this semiconductor device, and the read permission flag in the read permission flag setting circuit 3R is detected. Set.

When the CPU of the host activates the chip select signal input terminal 9 and the read strobe signal input terminal 10RSI in order to read the contents of the data register 2o for data output inside the semiconductor device, the access detection circuit inside the semiconductor device. 5 detects the access from the external host CPU, and outputs the content S7 of the read permission flag inside the read permission flag setting circuit 3R to the read standby request signal output terminal 7.

The read standby request signal output terminal 7 is
Connected to the READY input terminal of the host CPU, a wait cycle is inserted into the host CPU.

With the read permission flag set,
When the host CPU accesses the data output data register 2o, the wait cycle is not inserted in the host CPU and the semiconductor device immediately outputs the contents of the data output data register 2o to the data output terminal 8o.

When the CPU of the host accesses the data register 2o for data output while the read enable flag is reset, the standby request signal S7 is output from the read standby request signal output terminal 7 to the READY input terminal of the host CPU, and the host CPU executes a wait cycle.

The read standby request signal output terminal 7 is made inactive by the setting of the read enable flag which is implemented by the semiconductor device setting a value in the data register 2o for data output from the internal bus 1, and the host CPU
Reads the contents of the data register 2o for data output, which is output to the data output terminal 8 after returning from the wait cycle.

In the block of inputting data from the external circuit to the semiconductor device of the second embodiment shown in FIG.
When the semiconductor device reads the value of the data register 2i for data input to its own internal bus 1, the write permission flag setting circuit 3W detects the read processing of this semiconductor device,
The write permission flag in the write permission flag setting circuit 3W is set.

When the CPU of the host activates the chip select terminal 9 and the write strobe terminal 10WSI in order to write a value to the input data register 2i in the semiconductor device, the access detection circuit 5 in the semiconductor device is transferred from the host CPU. Access is detected, and the content of the write permission flag in the write permission flag setting circuit 3W is output to the write standby request signal output terminal 7.

The write standby request signal output terminal 7 is connected to the READY input terminal of the external host CPU to insert a wait cycle into the host CPU.

With the write permission flag set,
When the host CPU accesses the data input data register 2i, a wait cycle is not inserted in the host CPU, and the semiconductor device immediately writes the value input to the data input terminal 8i to the data input data register 2i.

When the host CPU accesses the data register 2i for data input while the write enable flag is reset, a standby request S7 is output from the write standby request signal output terminal 7 to the READY input terminal of the host CPU, and the host CPU Implements a weight cycle.

The write standby request signal output terminal 7 is made inactive by the write enable flag set which is executed when the semiconductor device reads the value of the data register 2i for data input to the internal bus 1.

In response to this, the host CPU returns from the wait cycle to complete the writing process to the semiconductor device, and at the same time, in the semiconductor device, the value input to the data input terminal 8i is transferred to the data register for data input. Write to 2i.

[0033]

As described above, in the logic semiconductor integrated circuit of the present invention, the availability of data input / output between external circuits inside the semiconductor device is output to the access standby request signal output terminal, and this is output to the host of the semiconductor device. R of the external CPU
By connecting to the EADY input terminal, there is an effect that data input / output can be performed in a non-procedural manner without the overhead of the host CPU due to the status check of the semiconductor device and the interrupt processing.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of a first example of a conventional logic semiconductor integrated circuit.

FIG. 4 is a block diagram of a second example of a conventional logic semiconductor integrated circuit.

FIG. 5 is a block diagram of a third example of a conventional logic semiconductor integrated circuit.

FIG. 6 is a block diagram of a fourth example of a conventional logic semiconductor integrated circuit.

[Explanation of symbols]

 1 internal bus 2i input data register 2o output data register 3R read enable flag setting circuit 3W write enable flag setting circuit 4 output buffer 5 access detection circuit 6i data input buffer 6o data output buffer 7 standby request signal output terminal 8i data Input terminal 8o Data output terminal 9 Chip select signal input terminal 10RSI Read strobe signal input terminal 10WSI Write strobe signal input terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akio Nakajima 1-3403 Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa NEC Corporation

Claims (1)

[Claims] 1. In a logic semiconductor integrated circuit, which is connected to a central processing unit externally located and operates as a host to form an interface circuit, and the central processing unit has the initiative of control, internal data input is performed. A permission flag setting circuit for storing a permission flag for notifying whether output is possible, and a terminal for outputting the state of the permission flag to the external circuit in response to an access signal from the external circuit are provided. Logic semiconductor integrated circuit.