JPH06139141A - Memory card device - Google Patents

Abstract

PURPOSE:To efficiently execute data erasing processing and to shorten time required for erasing processing by writing one digital data in each of plural semiconductor chips when the number of digital data to be written is less than the number of semiconductor memory chips. CONSTITUTION:Data A are written in the blocks 13a to 13c of block numbers (1) to (3) (physical addresses), data B are written in the blocks 14a to 14c of block numbers (5) to (7) (physical addresses) and data C are written in the blocks 15a to 15c of block numbers (9) to (11) (physical addresses). Since chip erasing can be executed by distributing and recording respective data A to C in respective EEPROM chips 13 to 15 even in the case of erasing any data A, B or C, data erasing processing can be efficiently executed, time required for erasing processing can be shortened and rapid data rewriting can be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a memory card device using an EEPROM (electrically erasable and programmable read only memory) as a semiconductor memory.

[0002]

As is well known, EEPROMs are currently
It has attracted attention as a data recording medium that replaces magnetic disks, and it does not require a backup battery for holding data and can reduce the cost of the chip itself. SRAM (static random access memory) ) Or D (dynamic) RAM has a unique advantage that it does not have, and therefore, development for use as a memory card is particularly active.

In this memory card, for example, an optical image of a photographed subject is converted into an electric image signal by using a solid-state image pickup device, the image signal is converted into digital image data, and recorded in a semiconductor memory. A memory card that is suitable for use in still cameras, etc., and has an EEPROM built into a card-shaped case that can be attached to and detached from the camera body so that it can be handled in the same way as a film in a normal camera. I am able to

By the way, in the EEPROM, the memory cell deteriorates depending on the number of times data is written, read, erased, etc., and the number of times of use (tens of thousands to millions) is shorter than that of SRAM. However, there is an inconvenience that defective writing of data easily occurs. Therefore, conventionally, a relief measure has been considered in which data to be written in a memory cell in which a write failure has occurred is written in another normal memory cell to be relieved (for example, Japanese Patent Application No. 3-3171).
69). Specifically, this relief measure is shown in FIG.
As shown in, when a write failure occurs at the address B of the data storage area, the data b to be written at the address B is written to the address C having another normal memory cell to be relieved.

On the other hand, in the EEPROM, when new data is written in an area where data has already been written, new data cannot be written unless the previously written data is erased (erased). The erase process is always executed when writing the data. This erase processing includes batch erase (or chip erase) for collectively erasing all data recorded in one-chip EEPROM, and 1
There are two types: block erase in which the data storage area of the EEPROM of the chip is divided into a plurality of reference areas (blocks) having the same storage capacity, and a desired block is designated to erase data in block units.

In the case of an electronic still camera, in order to record the data of one still image taken in the EEPROM, 10
.About.20 blocks are used, but generally, the time required for chip erase and the time required for block erase are substantially equal, and block erase cannot be performed simultaneously for a plurality of blocks in one EEPROM chip. When erasing data in multiple blocks, it is necessary to perform block erase one by one for each block to be erased. Therefore, data for one still image is erased. The chip erase requires a shorter time than the block erase.

Further, when a defective writing of data occurs in the EEPROM, if the erasing process is performed on the defective memory cell, the defectiveness may be enlarged to cause a defect in other normal memory cells. Therefore, the block including the defective memory cell is prohibited from being erased. Therefore, the defective EEPR
Since the OM chip cannot perform the chip erase, the block other than the block including the defective memory cell is erased only by performing the block erase.

In the electronic still camera, the time required for the erase process performed before writing the data and the E
Since the interval of continuous shooting is determined by the apparent data writing time including the time required for actually writing data in the EPROM, it is an important issue to shorten the time required for the erase process.

Here, FIG. 7 schematically shows the structure of a conventional memory card using an EEPROM. That is, the memory card body 11 is a connector 1 for connecting to a host device (not shown) such as an electronic still camera.
2 and 4 EEPROM chips 13, 14, 15, 1
6 and these EEPROM chips 13, 14, 15, 1
6, a controller 17 for performing data writing / reading processing for the data 6 and the above-described defect relief processing, and these connectors 12, EEPROM chips 13, 14, 1
5, 16 and a bus line 18 for connecting the controller 17.

Then, each EEPROM chip 13, 1
4, 15 and 16 are four blocks 13a to 1 respectively.
3d, 14a to 14d, 15a to 15d, 16a to 16
The blocks are divided into blocks 13a to 13d, 14
Consecutive block numbers 1 to 16 are assigned to a to 14d, 15a to 15d, and 16a to 16d.

Here, the host device sequentially supplies three data A, B, C consuming three blocks per data to the connector 12, and the EEPROM chip 1
When it is requested to write to 3, 14, 15, 16
The controller 17 transfers the data A to block numbers 1, 2,
The data B is written in the blocks 13a, 13b, and 13c of the block No. 3, and the blocks 13d and 14 of the block numbers 4, 5, and 6
a, 14b, the data C is block number 7,
The data A, B, and C are controlled so as to be sequentially written from the block 13a having the block number 1 at the beginning, such as writing to the blocks 14c, 14d, and 15a of 8 and 9.

Therefore, for example, the data B is replaced with another data D.
If it is attempted to rewrite it, the blocks 13d, 14a, 14b of the block numbers 4, 5, 6 will be erased, but in this case, other data A, C are also written in the EEPROM chips 13, 14. Therefore, since chip erase cannot be performed, it is necessary to deal with all block erase, which causes a problem that erasing takes time.

Further, as shown in FIG. 8, data A is assigned to blocks 13a, 13b and 13c of block numbers 1, 2 and 3.
It is assumed that a write failure occurs in the block 13b when writing data to the block 13b, and the controller 17 rewrites the data to be written in the block 13b to the block 16d having the block number 16. When attempting to erase the data A in such a state, originally, since only the data A is written in the EEPROM chip 13, the EEP
If the chip erase is performed on the ROM chip 13, the time required for the erasing can be shortened. However, as described above, since the EEPROM erase on the EEPROM chip 13 in which the write failure occurs cannot be performed, all of the cases also occur. There is a problem in that block erase must be dealt with and it takes time to erase.

Then, after performing the defect remedy shown in FIG. 8, as shown in FIG. 9, the data B is written in the blocks 13d, 14a, 14b of the block numbers 4, 5, 6 and the data C is written. The data D is written in the blocks 14c, 14d, 15a of the block numbers 7, 8, 9 and the data D is written in the blocks 15b, 15c, 1 of the block numbers 10, 11, 12, respectively.
5d, write data E to block numbers 13, 14,
If the data E is to be erased while it has been written in the blocks 16a, 16b, 16c of 15,
EEPROM chip 1 because there is defect relief data in d
Since the chip erase cannot be performed for 6, the block erase must be dealt with in this case as well, which causes a problem that it takes time to erase.

[0015]

As described above, in the conventional memory card using the EEPROM as the semiconductor memory, the data erasing process is inefficient, time-consuming, and it is difficult to quickly rewrite the data. Have the problem of being.

Therefore, the present invention has been made in consideration of the above circumstances, and is extremely good in that the data erasing process can be efficiently performed and the time required for the erasing process can be shortened to realize rapid data rewriting. It is an object of the present invention to provide a simple memory card device.

[0017]

A memory card device according to the present invention includes a plurality of semiconductor memory chips having a chip erase function for collectively erasing data in a chip.
It is intended for sequentially writing a plurality of digital data having a predetermined data length. Further, when the number of digital data to be written in the plurality of semiconductor memory chips is equal to or less than the number of the semiconductor memory chips, a control means for controlling one digital data to be written in each of the plurality of semiconductor memory chips is provided. It was done.

Further, the memory card device according to the present invention sequentially writes a plurality of digital data having a predetermined data length to a plurality of semiconductor memory chips having a chip erase function for collectively erasing the data in the chip. In this case, the entire storage area formed by a plurality of semiconductor memory chips is divided into a plurality of reference areas having a certain capacity, and the data to be written in the reference area in which the write failure has occurred is written in another normal reference area for relief. It is intended for those equipped with means. Then, a control means is provided for controlling the data to be written in the reference area where the writing failure has occurred so as to search for an empty reference area in the semiconductor memory chip including the reference area where the writing failure has occurred and write the data. Is.

[0019]

According to the above configuration, first, when the number of digital data to be written in the plurality of semiconductor memory chips is equal to or less than the number of the semiconductor memory chips, one digital data is stored in each of the plurality of semiconductor memory chips. Since the data is written, when erasing any digital data, it is sufficient to perform the chip erase to the semiconductor memory chip in which the digital data is written,
It becomes possible to efficiently perform the erasing process of digital data, shorten the time required for the erasing process, and realize rapid data rewriting.

Further, since the data to be written in the reference area in which the write failure has occurred is searched for in the empty reference area in the semiconductor memory chip including the reference area in which the write failure has occurred, the failure remedy is performed. Even when erasing the applied digital data, it is sufficient to perform the chip erase to the semiconductor memory chip in which the digital data is written, and the erasing process of the digital data can be efficiently performed as well as the time required for the erasing process. It becomes possible to shorten the time and realize quick data rewriting.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. In FIG. 1, the same parts as those in FIG. 7 are designated by the same reference numerals. That is, in the controller 17, management tables as shown in FIGS. 2A and 2B are formed. First, FIG. 2 (a)
The management table shown in is the EEPR specified by the host device.
Addresses of OM chips 13, 14, 15 and 16 (hereinafter referred to as logical addresses) and actual EEPROM chip 1
3, 14, 15, and 16 addresses (hereinafter referred to as physical addresses) are associated with each other. In this example, both logical addresses and physical addresses are assigned block numbers 1 to 16.
It is represented by. In addition, the management table shown in FIG. 2B shows the usage states of the EEPROM chips 13, 14, 15, 16 in two states, in use and unused.

Here, from the host device, block numbers 1,
Blocks 13a and 13 of 2 and 3 (this is a logical address)
When the writing of the data A is requested to b and 13c, the controller 17 refers to the management table shown in FIG. 2A to refer to the blocks of block numbers 1, 2 and 3 (this is the physical address). 13a, 13b, 13c
Data A is written to the EEPROM chip 13 of the management table shown in FIG. 2B.

Next, the block number 4 from the host device
Blocks 13d and 14 of 5 and 6 (this is a logical address)
When the data B is requested to be written to a and 14b, the controller 17 refers to the management table shown in FIG. 2A to refer to the blocks of block numbers 5, 6 and 7 (this is the physical address). 14a, 14b, 14c
The data B is written to the EEPROM chip 14 of the management table shown in FIG. 2B.

Next, from the host device, block number 7,
Blocks 14c and 14 of 8 and 9 (this is a logical address)
When the writing of the data C is requested to the d and 15a, the controller 17 refers to the management table shown in FIG.
(This is a physical address) blocks 15a, 15b, 1
It is assumed that the data C is written in 5c and the EEPROM chip 15 of the management table shown in FIG. 2B is in use.
The management table shown in FIGS. 1 and 2B shows a state in which the data A, B, and C are written in this way.

In this way, data A is assigned to block number 1,
Blocks 13a and 13 of 2 and 3 (this is a physical address)
b, 13c, and data B is written in block number 5,
Blocks 14a and 14 of 6 and 7 (this is a physical address)
b, 14c, write data C to block number 9, 1
Blocks 15a, 1 of 0, 11 (this is a physical address)
Each data A, such as writing to 5b, 15c
By recording B and C dispersedly on the EEPROM chips 13, 14, and 15 respectively, the data A,
Since the chip erase can be performed even when B or C is erased, the data erasing process can be efficiently performed, and the time required for the erasing process can be shortened to realize rapid data rewriting. Like

From the host device, block number 10,
Blocks 15b of 11, 12 (this is a logical address),
When the writing of the data D is requested to 15c and 15d, the controller 17 refers to the management table shown in FIG.
Blocks 16a, 16 of 15 (this is a physical address)
Data D is written in b and 16c, and the EEPROM chip 15 of the management table shown in FIG. 2B is in use.

When the host device further requests the writing of the data E to the blocks 16a, 16b and 16c having the block numbers 13, 14 and 15 (this is a logical address), the controller 17 operates as shown in FIG. (B)
It is judged from the management table shown in FIG. 3 that there is no unused EEPROM chip, and the data E is set to block number 4,
Blocks 13d and 1 of 8 and 12 (this is a physical address)
4d and 15d are dispersed and written.

Next, in FIG. 3, three pieces of data A, B, and C, which consume three blocks per data, are distributed and written in the EEPROM chips 13, 14, and 15, respectively, and data D, which consumes two blocks, are written. Is EEPRO
Written in blocks 16a and 16b of the M chip 16,
Block 13 with block numbers 4, 8, 12, 15, and 16
It shows a state where d, 14d, 15d, 16c and 16d are empty blocks.

When further writing the data E which consumes 3 blocks in such a state, the controller 17 sets the data E to the block number 4, unlike the above example.
Blocks 13d of 15, 16 (this is a physical address),
It is controlled so as to be dispersed and written in 16c and 16d.
This is because when the data E is written in the blocks 13d, 14d and 15d of the block numbers 4, 8 and 12 (which are physical addresses), the data E has three EEPROM chips 13,
Block numbers 4, 1
Blocks 13d and 1 of 5, 16 (this is a physical address)
In 6c and 16d, two EEPROM chips 13 and 1 are used.
This is because it is only distributed to 6 and is effective in promoting the efficiency of the data erasing process.

Further, FIG. 4 shows each EEPROM chip 1
3, 14, 15, 16 are eight blocks 13a each
-13h, 14a-14h, 15a-15h, 16a-
It is divided into 16h, and each block 13a to 13h,
14a to 14h, 15a to 15h, 16a to 16h are shown as consecutive block numbers 1 to 32.

In this case, when 10 pieces of data A to J consuming 3 blocks per data are sequentially written, the blocks 13a and 13 of the block numbers 1, 2 and 3 are first written.
The data A is written in b, 13c, the data B is written in the blocks 14a, 14b, 14c of the block numbers 9, 10, 11 and the block numbers 17, 18, 19 are written next.
The data C is written in the blocks 15a, 15b, and 15c, and then the block 16 of the block numbers 25, 26, and 27.
a, 16b, 16c write data D, then write data E in blocks 13d, 13e, 13f of block numbers 4, 5, 6 and then block numbers 12, 13, 1
The data F is written in the blocks 14d, 14e, and 14f of No. 4, and then the block 1 of the block numbers 20, 21, and 22.
Data G is written in 5d, 15e, 15f, and then blocks 16d, 16e, of block numbers 28, 29, 30
Write data H to 16f, then block number 7,
Data I in blocks 13g, 13h, and 14g of 8 and 15
Is written, and finally the data J is written in the blocks 15g, 15h, and 16g of the block numbers 23, 24, and 31.
It is taken into consideration that data is not recorded across 3, 14, 15, and 16 with each other. The blocks 14h and 16h with the block numbers 16 and 32 are the remainder.

Further, FIG. 5 shows a case where a write failure occurs in the block 13b when the data A is written in the blocks 13a, 13b, 13c of the block numbers 1, 2, 3. In this case, the controller 17 controls so that the data to be written to the block 13b is relieved by writing it to the block 13d of the block number 4, that is, the empty block 13d of the EEPROM chip 13 itself in which a defect occurs at the time of writing the data A. . In this way, when the data A is erased, EEPRO
Only the chip erase is required for the M chip 13, and the efficiency of the erasing process is promoted. The present invention is not limited to the above-described embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[0033]

As described above in detail, according to the present invention,
It is possible to provide a very good memory card device in which the data erasing process is efficiently performed and the time required for the erasing process can be shortened to realize rapid data rewriting.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory card device according to the present invention.

FIG. 2 is a diagram for explaining details of a management table in the embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block configuration diagram showing a third embodiment of the present invention.

FIG. 5 is a block diagram showing a fourth embodiment of the present invention.

FIG. 6 is a diagram shown for explaining a defect relief measure for an EEPROM.

FIG. 7 is a block configuration diagram shown to explain a first problem of the conventional memory card.

FIG. 8 is a block configuration diagram shown for explaining a second problem of the conventional memory card.

FIG. 9 is a block configuration diagram shown for explaining a third problem of the conventional memory card.

[Explanation of symbols]

11 ... Memory card main body, 12 ... Connector, 13 to 16
... EEPROM chip, 17 ... controller, 18 ... bus line.

Claims (4)

[Claims] 1. A memory card device for sequentially writing a plurality of digital data having a predetermined data length to a plurality of semiconductor memory chips having a chip erase function for collectively erasing data in the chip. When the number of the digital data to be written in the memory chip is equal to or less than the number of the semiconductor memory chips, a control means is provided to control so that one digital data is written in each of the plurality of semiconductor memory chips. Characteristic memory card device. 2. The control means externally designates a logical address for all storage areas formed by the plurality of semiconductor memory chips and an actual physical address of all storage areas formed by the plurality of semiconductor memory chips. 2. The memory card device according to claim 1, further comprising: a management table that associates with each other, and controls to write one digital data to each of the plurality of semiconductor memory chips based on the management table. 3. The semiconductor device according to claim 3, wherein when it is necessary to write one digital data in a plurality of semiconductor memory chips in a dispersed manner, the number of semiconductor memory chips to which the digital data should be written is reduced. 2. The memory card device according to claim 1, wherein a memory chip is selected. 4. A plurality of semiconductor memory chips having a chip erase function for collectively erasing data in a chip are sequentially written with a plurality of digital data having a predetermined data length, and the plurality of semiconductor memory chips are provided. In a memory card device provided with a remedy unit that divides the entire storage area formed by the above into a plurality of reference areas of a fixed capacity and writes the data to be written in the reference area in which the write failure has occurred to another normal reference area to relieve And a control unit for controlling the data to be written in the reference area in which the write failure has occurred so as to search and write an empty reference area in the semiconductor memory chip including the reference area in which the write failure has occurred. A memory card device characterized by the above.