JPH0613913A - Data string rearrangement circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale and to quicken the operating speed by connecting storage means in cascade, using a selection means to select an output from a connecting point among plural storage means connected in cascade and outputting only one output. CONSTITUTION:The circuit is provided with a storage means (FF) receiving each input data string to latch the data and shifting the data stored in response to a prescribed signal and with a selection means 24 receiving plural input signals and selectively outputting only one signal among the plural input signals. Then plural FFs 211-21m are provided and connected in cascade and the selection means 24 selectively outputs the output from connecting points (including input output points) of the plural FFs 211-21m connected in cascade as plural input signals to rearrange the sequence of the input data strings. Thus, the plural FFs 211-21m implement the processing shifting only the data stored in terms of prescribed signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data string rearrangement circuit for rearranging the order of each data of an input data string in a desired order and outputting the same, and is suitable for use in, for example, compressing image data. The present invention relates to a data string rearrangement circuit.

[0002]

2. Description of the Related Art Conventionally, in the field of image data compression technology for compressing image data, for example, a two-dimensional DCT is used.
Image data compression processing may be performed using (discrete cosine transform) processing. In the two-dimensional DCT processing, for example, a circuit that performs one-dimensional DCT calculation is used to perform one-dimensional DCT in the row direction of an input data string of image data,
Rearrange the data sequence in row order into column order, and then use another one-dimensional D
It is often realized by performing one-dimensional DCT in the column direction by a circuit that performs CT calculation.

As a circuit for rearranging the input data string used when performing such two-dimensional DCT processing, for example, a circuit having a structure shown in FIG. 58 is usually used. In the configuration of FIG. 58, the input terminal 1 is supplied with a serial input data string composed of a group of data to be rearranged. This input data string is the changeover switch 2
Data is sequentially written to any one of the RAMs 3 and 4 having the same number of words as the number of data of the group of input data strings. The data written in the RAMs 3 and 4 is read according to the read address data RA. At this time, the read address data RA is an address at which the respective pieces of the input data are read in a desired order. Controlled by data. In this way, by controlling the read address data RA when the data is read from the RAM, the rearrangement of the data string is realized. That is,
When writing data to the RAM, for example, write address data WA is used so that data is sequentially written from address 0 of the RAM, and when reading data, for example, the address at the time of writing is used. Are read from different read addresses and the data is read in a desired read order to rearrange the data strings. The data string read from one of the RAMs 3 and 4 is output as an output data string from the output terminal 6 via the changeover switch 5.

Here, since the group of input data strings is sequentially supplied in series, in order to perform the rearrangement processing of the data strings in real time, while writing to one RAM, the other The data is read from the RAM. That is, for example, when the changeover switch 2 is changed over to the changed terminal a, each data of the input data string is sequentially stored in the RAM 3. At this time, the changeover switch 5 is changed over to the terminal b to be changed over, and each data of the previously stored data sequence is rearranged and read out from the RAM 4, and these become the output data sequence. On the contrary, when the changeover switch 2 is switched to the switched terminal b, the input data string is stored in the RAM 4, and the already stored data is rearranged and read out from the RAM 3. At this time, the selector switch 5 is switched to the switched terminal a. By repeating such switching of the switches and writing / reading of the RAM, rearrangement of each data of the input data string sequentially supplied is performed in real time. The switching control of the changeover switches 2 and 5 and the control of each address data to the RAMs 3 and 4 are performed by a control circuit (not shown). Further, if the input data string supplied to one RAM is an odd-numbered data string, the input data string supplied to the other RAM is an even-numbered data string.

[0005]

However, in the above-described data string rearrangement circuit of FIG. 58, in order to rearrange the order of each data of the input data string sequentially supplied in real time, the data of the input data string is processed. Since two RAMs with the same number of words as the number of RAMs are required, there is a drawback that the circuit scale becomes large. Moreover, since the RAM is used, the operation speed is slow.

Therefore, the present invention has been proposed in view of the above circumstances, and an object thereof is to provide a data string rearrangement circuit having a small circuit scale and a high operation speed.

[0007]

The data string rearrangement circuit of the present invention is proposed to achieve the above-mentioned object, and outputs the data by rearranging the order of each data of an input data string composed of a plurality of data. A data string rearrangement circuit for supplying each data of the input data string, holding the data, and shifting the stored data according to a predetermined signal, and a plurality of input signals are supplied. A selection means for selectively outputting only one signal from the plurality of input signals, a plurality of storage means are provided and each storage means is connected in cascade, and the selection means is connected in cascade. The outputs from the connection points (including the input / output points) of the plurality of storage means are selectively output as the plurality of input signals to rearrange the order of each data of the input data string. It is obtained by way.

Further, the data string rearrangement circuit of the present invention is
A data string rearrangement circuit for rearranging and outputting the order of each data of an input data string composed of a plurality of data, wherein each data of the input data string is supplied, and the data is held and stored in accordance with a predetermined signal. A plurality of input signals are supplied, and a selection means for selectively outputting only one signal from the plurality of input signals is provided, and a plurality of the storage means are provided. In addition, a plurality of first rearrangement means in which each storage means is connected in cascade are further provided to connect each first rearrangement means in cascade.
The selection means selectively outputs the outputs from the connection points (including the input / output points) of the first rearrangement means connected in cascade as the plurality of input signals, thereby ordering the respective data of the input data string. Is to be rearranged.

Further, it is also possible to provide a plurality of second rearranging means in which a plurality of the first rearranging means are connected in cascade to connect them in series, whereby a plurality of first rearranging means can be used. It is also possible to perform the rearrangement process several times in succession to perform a desired rearrangement.

[0010]

According to the data string rearranging circuit of the present invention, a plurality of storage means or a plurality of first rearranging means are connected in cascade, and the signal from each connection point is selected by the selecting means to save the data string. Since the rearrangement is performed and each storage unit performs only the process of shifting the data stored by the predetermined signal, the address for writing / reading is not required and the process can be performed at high speed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data string rearrangement circuit of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a first embodiment of a data string rearrangement circuit of the present invention. The data string rearrangement circuit of FIG.
Is a data string rearrangement circuit that rearranges the order of each data of the input data string supplied to the output terminal 25 and outputs it from the output terminal 25.

That is, this data string rearrangement circuit is
Each data of the input data string is supplied and held, and at the same time, as a predetermined signal, terminals 22 ₁ , 22 ₂ , ...
.., 22 _n-2 , 22 _n-1 , 22 _n , 22 _{n + 1} , 2
Flip-flops (FF) as storage means for shifting the stored data according to the enable signal supplied from 2 _{n + 2} , ... _, 22 _{m ,} and a plurality of switching selection terminals 24S ₀ , 24S ₁ , ..., 24S _n-2 , 24
_{S n-1, 24S n,} 24S n + 1, 24S n + 2, ···,
Outputs either only one one signal from among a plurality of input signals supplied to the plurality of the switching terminal 24S ₀ ~24S _m by selecting the switching selection terminal selectively of 24S _m And a plurality of flip-flops (for example, flip-flops 21 ₁ , 21 ₂ , ..., 21 _n-2 , 2).
1 _n-1 , 21 _n , 21 _{n + 1} , 21 _{n + 2} , ... _, 2
1 _m) each connected in cascade each flip-flop provided with, the switching selection switch 24 is the output from the connection point of the plurality of flip-flops 21 ₀ through 21 _m as described above cascaded (including input and output point) of the plurality Switched selection terminal 2
By selectively outputting as the input signal supplied to 4S _{0 to} 24S _m , the order of each data of the supplied input data string is rearranged and output. The changeover selection switch 24 is controlled by a changeover control signal from a control circuit (not shown) via the terminal 23. Further, each terminal 22 _{2 to} 22
_The enable signal supplied to _m is also supplied from the control circuit.

In the first embodiment of FIG. 1, each data of an input data string consisting of a plurality of data (a group of data) is serially input (x _d , ..., To the input terminal 20.
x _c , x _b , x _a , x _e , x _f , ..., X _g in this order). In this case, the terminal 2
All the enable signal supplied to the 2 ₁ through 22 _m O
By setting to N (for example, high level), each of the supplied data is sequentially shifted in each of the flip-flops 21 _{1 to} 21 _m . Therefore, when the next data x _h of the data x _g came to the input terminal 20 (time), the flip-flop 21 _m contains data x _d, the flip-flop 21 n _{+ 2} data x _c However, the data x _b is stored in the flip-flop 21 _{n + 1.
The} data x _a is stored in _n , the data x _e is stored in the flip-flop 21 _n-1 , and the data x _f is stored in the flip-flop 21 _n-2.
However, the data x _g is stored in the flip-flop 21 ₁ .

At this time, the data x _a in the flip-flop 21 _n is taken out. In this case, the terminal 22
Of the enable signals supplied to _{1 to} 22 _m , the enable signals to the terminals 22 _{1 to} 22 _n are turned on (for example, high level), and the remaining terminals 22 _{n + 1 to} 22 _m are turned off.
(Eg low level). Further, the changeover selection switch 24 selects the changeover selected terminal 24S _{n according} to the changeover control signal via the terminal 23. As a result, the data x _a stored in the flip-flop 21 _n and shifted later is output from the output terminal 25. Also, data x _e , x after this data x _a
Since the enable signals for the corresponding flip-flops are ON, _{f 1} , ..., X _g are shifted one by _one to the subsequent flip-flops, and the next data x _h is stored in the flip-flop 21 ₁ . At this time, the flip-flops 21 _{n + 1 to} 21 whose enable signal is OFF are
_{In m} , each of the above stored data is held as it is. As a result, the data x _a can be extracted from the input data string.

Here, as will be described below, the data strings can be rearranged by controlling each enable signal and the changeover selection switch. In the first embodiment, a specific example of the data string rearrangement process will be described with reference to FIGS.

FIG. 2 shows a specific example of the data string rearrangement circuit of the first embodiment shown in FIG. This Figure 2
The data string rearrangement circuit also rearranges the order of each data of the input data string supplied to the input terminal 10 and outputs the output terminal 1
5 is a data string rearrangement circuit to be output from 5.

That is, the data string rearrangement circuit of FIG. 2 has a flip-flop (FF) that shifts stored data according to an enable signal supplied from terminals 12 _{1 to} 12 ₄ and a plurality of switched selection terminals. 14a ~
A selection switch for selectively outputting only one signal from the plurality of input signals supplied to the plurality of switched terminals 14a to 14e by selecting any one of the switched terminals 14e. And a plurality of flip-flops (for example, flip-flops 11 _{1 to} 11).
₅ ) The flip-flops are provided and the flip-flops are connected in cascade, and the changeover selection switch 14 outputs the output from the connection point and the input / output point of the plurality of cascaded flip-flops 11 _{1 to} 11 ₅ to the plurality of selected selection terminals. 14a-1
By selectively outputting as the input signal supplied to 4e, the supplied input data sequence is rearranged and output. The changeover selection switch 14
Is switched and controlled by a switching control signal from a control circuit (not shown) via the terminal 13. The enable signal supplied to each of the terminals 12 _{1 to} 12 ₄ is also supplied from the control circuit.

The circuit of the concrete example of the first embodiment shown in FIG. 2 is configured to perform a rearrangement process of image data, which is carried out when the image data is compressed, for example. In FIG. 2, the input terminal 10, the data of the input data sequence consisting of the data of four rows and four columns as shown in the plurality of data, that FIG. 3, for example a serial input to the line sequential (A _0, A _1, A
₅ , A ₆ , A ₂ , A ₄ , A ₇ , A ₁₂ , A ₃ , A ₈ ,
A ₁₁ , A ₁₃ , A ₉ , A ₁₀ , A ₁₄ , and A ₁₅ are serially input in this order). The concrete circuit of the first embodiment shown in FIG. 2 has the following four-row-four-column data shown in FIG.
For example, the order of each data of the input data string is rearranged by the so-called zigzag scanning shown in FIG. 4 (A ₀ , A
₁ , A ₂ , A ₃ , A ₄ , A ₅ , A ₆ , A ₇ , A ₈ ,
_{A 9, A 10, A 11} , A 12, rearranges the order of _{A 13, A 14, A 15} ) is a data string rearranging circuit for serial output from the output terminal 15. That is, in the specific example of the first embodiment, the switching control signal and the enable signal are signals corresponding to the zigzag scanning of FIG.

Here, FIGS. 5 to 20 show the same structure as that of FIG. First, in FIG. 5, the data A ₀ , A ₁ , A ₅ , A ₅ ,
It is assumed that A ₆ , A ₂ , ... Are supplied in this row order. At this time, all the enable signals supplied to the terminals 12 _{1 to} 12 ₄ are turned on (for example, high level). As a result, in the flip-flops 11 _{1 to} 11 ₄ , the supplied data are sequentially shifted. Therefore, the data A next to the above data A ₂ is input to the input terminal 10.
The (time) when _{the 4} came, to the flip-flop 11 ₅ contains data A _0, data A ₁ in the flip-flop 11 ₄ receives the data in the flip-flop 11 ₃ A
₅ , the data A ₆ is stored in the flip-flop 11 ₂ , and the data A ₂ is stored in the flip-flop 11 ₁ . In this case, the changeover selection switch 14 is
By selecting the switched selection terminal 14a by the switching control signal via the terminal 13 (not shown), the output terminal 15 receives the data A ₀ stored in the flip-flop 11 ₅ and then shifted and taken out. Will be output.

Next, in FIG. 6, when the data A ₇ next to the data A ₄ comes to the input terminal 10 (time) as shown in FIG. 3, the flip-flop 11 ₅ receives the data A ₁ There are stored, the data A ₅ are the flip-flop 11 _4, the data A ₆ to the flip-flop 11 _3, the flip-flop 11 ₂ data A ₂ is, to the flip-flop 11 ₁ is stored data A ₄ Will be there. At this time, all the enable signals are also on. Further, in this case, by selecting the switched selection terminal 14a of the selection switch 14, the output terminal 15 outputs the data A _{1 which} is stored in the flip-flop 11 ₅ and then shifted and taken out. .

Further, in FIG. 7, at the time when the next data A ₁₂ after the data A ₇ comes to the input terminal 10 as shown in FIG. 3, the flip-flop 11 ₅ receives the data A ₅
Is stored, and the data A is stored in the flip-flop 11 _4.
6 , the data A ₂ is stored in the flip-flop 11 ₃ , the data A ₄ is stored in the flip-flop 11 ₂ , and the data A ₇ is stored in the flip-flop 11 ₁ .
Here, at this time, in order to perform data rearrangement such as the so-called zigzag scanning as shown in FIG. 4, the enable signals of the terminals 12 ₃ and 12 ₄ are turned off (for example, low level), and the remaining The enable signals at the terminals 12 ₁ and 12 ₂ are turned on. As a result, the flip-flops 11 ₅ and 11 ₄ stop taking in new data and hold the already stored data (data A ₅ and A ₆ ). At this time, in the changeover selection switch 14, the changeover selection terminal 14c is selected based on the control signal. As a result, the flip-flop 1 is output from the output terminal 15.
Data A stored in 1 ₃ and then shifted and extracted
₂ will be output.

Similarly, in FIG. 8, the data A ₃ next to the data A ₁₂ is input to the input terminal 10 as shown in FIG.
When the time comes, the data A is stored in the flip-flop 11 _5.
5 is stored, and the data A ₆ is stored in the flip-flop 11 _4.
However, the data A ₄ is stored in the flip-flop 11 ₃ , the data A ₇ is stored in the flip-flop 11 ₂ , and the data A ₁₂ is stored in the flip-flop 11 ₁ . Here, in order to rearrange the data as shown in FIG. 4 described above, all the enable signals of the terminals 12 _{1 to} 12 ₄ are turned off. As a result, the flip-flops 11 _{1 to} 11 ₅ stop taking in new data, and hold the already stored data. At this time, in the changeover selection switch 14, the changeover selection terminal 14e is selected based on the control signal. As a result, the data A ₃ supplied to the input terminal 10 is directly output from the output terminal 15 from the output terminal 15.

In FIG. 9, as shown in FIG. 3, at the time when the next data A ₈ after the above data A ₃ arrives at the input terminal 10, the data A ₅ is stored in the flip-flop 11 ₅ , and the flip-flop 11 ₅ is stored. data A ₆ to _4, the flip-flop 11 ₃ data A ₄ is data A ₇ to the flip-flop 11 ₂ is, to the flip-flop 11 ₁ is stored data A _12. Here, in order to rearrange the data as shown in FIG.
The enable signals of ₃ and 12 ₄ are turned off, and the enable signals of the remaining terminals 12 ₁ and 12 ₂ are turned on. As a result, the flip-flops 11 ₅ and 11 ₄ stop taking in new data and hold the already stored data (data A _5, A ₆ ). At this time, in the changeover selection switch 14, the changeover selection terminal 14c is selected. As a result, the output terminal 15 outputs the data A _{4 which} is stored in the flip-flop 11 ₃ and then shifted and taken out.

In FIG. 10, as shown in FIG. 3, at the time when the next data A ₁₁ of the data A ₈ comes to the input terminal 10, the data A ₅ is stored in the flip-flop 11 ₅ , and the flip-flop 11 ₅ is stored. Data A ₆ is stored in ₄ , data A ₇ is stored in the flip-flop 11 ₃ , data A ₁₂ is stored in the flip-flop 11 ₂ , and data A ₈ is stored in the flip-flop 11 ₁ . Here, in order to rearrange the data as shown in FIG.
All the enable signals _{1 to} 12 ₄ are turned on. As a result, the data shift is performed in each of the flip-flops 11 _{1 to} 11 ₅ . At this time, in the changeover selection switch 14, the changeover selection terminal 14a is selected. As a result, the output terminal 15 outputs the data A _{5 which} is stored in the flip-flop 11 ₅ and is then shifted and taken out.

In FIG. 11, at the time when the next data A ₁₃ following the above data A ₁₁ arrives at the input terminal 10 as shown in FIG. 3, the data A ₆ is stored in the flip-flop 11 ₅ , and the flip-flop 11 Data A ₇ is stored in _4; data A ₁₂ is stored in the flip-flop 11 _3; data A ₈ is stored in the flip-flop 11 _2; data A ₁₁ is stored in the flip-flop 11 ₁ . Here, in order to rearrange the data as shown in FIG.
All the enable signals _{1 to} 12 ₄ are turned on. As a result, the data shift is performed in each of the flip-flops 11 _{1 to} 11 ₅ . At this time, in the changeover selection switch 14, the changeover selection terminal 14a is selected. As a result, the output terminal 15 outputs the data A _{6 which} is stored in the flip-flop 11 ₅ and is then shifted and taken out.

In FIG. 12, at the time when the next data A ₉ of the above data A ₁₃ arrives at the input terminal 10 as shown in FIG. 3, the data A ₇ is stored in the flip-flop 11 ₅ , and the flip-flop 11 ₅ is stored. Data A ₁₂ is stored in _4; data A ₈ is stored in the flip-flop 11 _3; data A ₁₁ is stored in the flip-flop 11 _2; data A ₁₃ is stored in the flip-flop 11 ₁ . Here, in order to rearrange the data as shown in FIG.
All the enable signals _{1 to} 12 ₄ are turned on. As a result, the data shift is performed in each of the flip-flops 11 _{1 to} 11 ₅ . At this time, in the changeover selection switch 14, the changeover selection terminal 14a is selected. As a result, the output terminal 15 outputs the data A ₇ that is stored in the flip-flop 11 ₅ and then shifted and taken out.

[0027] In FIG. 13, the next time the data A ₁₀ came in the data A ₉ to the input terminal 10 as shown in FIG. 3, the data A ₁₂ is stored in the flip-flop 11 _5, flip-flop 11 data A ₈ to _4, the flip-flop 11 ₃ data A ₁₁ is, data A ₁₃ to the flip-flop 11 ₂ is, the flip-flop 11 ₁ is stored data A ₉ is. Here, in order to rearrange the data as shown in FIG.
The enable signal of ₄ is turned off, and the remaining terminals 12 ₁
The enable signals of ~ 12 ₃ are turned on. Accordingly, the flip-flop 11 _5, holding the data of the new data capture is stored is stopped previously (data A ₁₂₎ is made. At this time, the changeover selection switch 1
In 4, the switched selection terminal 14b is selected. As a result, the output terminal 15 outputs the data A _{8 which} is stored in the flip-flop 11 ₄ and then shifted and taken out.

[0028] In FIG. 14, the next time the data A ₁₄ has come of the data A ₁₀ to the input terminal 10 as shown in FIG. 3, data A ₁₂ to the flip-flop 11 ₅ is the flip-flop 11 ₄ Is the data A ₁₁ , the flip-flop 11 ₃ is the data A ₁₃ , the flip-flop 11 ₂ is the data A ₉ , and the flip-flop 11 ₁ is the data A _13.
10 is stored. Here, to perform the reordering of the data as shown in FIG. 4 described above, the terminals 12 _2, 12
The enable signals of ₃ and 12 ₄ are turned off, and the enable signals of the remaining terminals 12 ₁ are turned on. As a result, the flip-flops 11 ₃ , 11 ₄ , and 11 ₅ stop taking new data and hold the already stored data (data A ₁₂ , A ₁₁ , and A ₁₃ ). At this time, the switch selection switch 14 selects the switch selection terminal 14d. As a result, the output terminal 15
Will output the data A ₉ stored in the flip-flop 11 ₂ and then shifted and taken out.

In FIG. 15, as shown in FIG. 3, at the time when the next data A ₁₅ after the above data A ₁₄ arrives at the input terminal 10, the data A ₁₂ is sent to the flip-flop 11 ₅ and the data A ₁₅ is sent to the flip-flop 11 ₄ . Is the data A ₁₁ , the flip-flop 11 ₃ is the data A ₁₃ , the flip-flop 11 ₂ is the data A ₁₀ , and the flip-flop 11 ₁ is the data A _13.
14 are stored. Here, in order to rearrange the data of FIG. 4, the enable signals of the terminals 12 ₂ , 12 ₃ and 12 ₄ are turned off, and the enable signals of the remaining terminals 12 ₁ are turned on. As a result, the flip-flops 11 ₃ , 11 ₄ , and 11 ₅ stop taking new data and hold the already stored data (data A ₁₂ , A ₁₁ , and A ₁₃ ). At this time, the switch selection switch 14 selects the switch selection terminal 14d. As a result, the output terminal 15 outputs the data A _{10 which} is stored in the flip-flop 11 ₂ and is then shifted and taken out.

In FIG. 16, the first data B of the next 4 rows and 4 columns (the same as in FIG. 3 except that A of each data in FIG. 3 is replaced by B) of the above data A ₁₅ is input terminal 10. At time ₀ came, to the flip-flop 11 ₅ contains data a _12, data a ₁₁ to the flip-flop 11 ₄ is,
The data A ₁₃ is stored in the flip-flop 11 ₃ and the data A ₁₄ is stored in the flip-flop 11 _2.
Data A ₁₅ is stored in ₁ . Here, in order to rearrange the data, the enable signal of the terminal 12 ₄ is turned off, and the enable signals of the remaining terminals 12 _{1 to} 12 ₃ are turned on. Accordingly, the flip-flop 11 _5, holding the data of the new data capture is stored is stopped previously (data A ₁₂₎ is made. At this time, in the changeover selection switch 14, the changeover selection terminal 14b is selected. As a result, the output terminal 15 outputs the data A ₁₁ that is stored in the flip-flop 11 ₄ and then shifted and taken out.

[0031] In FIG. 17, above the next data B _{time 1} came data B ₀ to the input terminal 10, the flip-flop 11 ₅ contains data A _12, data A ₁₃ to the flip-flop 11 ₄ is , The data A ₁₄ is stored in the flip-flop 11 ₃ and the data A ₁₄ is stored in the flip-flop 11 _2.
15 and the data B ₀ is stored in the flip-flop 11 ₁ . Here, to rearrange the above data,
All the enable signals of the terminals 12 _{1 to} 12 ₄ are turned on. As a result, each of the flip-flops 11 _{1 to} 11
_{In 5} , data shift is performed. At this time, in the changeover selection switch 14, the changeover selection terminal 14a is selected.
Is selected. As a result, the output terminal 15 outputs the data A ₁₂ that is stored in the flip-flop 11 ₅ and then shifted and taken out.

[0032] In FIG. 18, the data B ₁ of the next data B ₅ came time to the input terminal 10, the flip-flop 11 ₅ contains data A _13, data A ₁₄ to the flip-flop 11 ₄ is , The data A ₁₅ is stored in the flip-flop 11 ₃ and the data B is stored in the flip-flop 11 _2.
0 , the data B ₁ is stored in the flip-flop 11 ₁ . Here, to rearrange the above data,
All the enable signals of the terminals 12 _{1 to} 12 ₄ are turned on, whereby each of the flip-flops 11 _{1 to} 11 _{5 is} turned on.
Then, data shift is performed. Further, at this time, the switch selection switch 14 selects the switch selection terminal 14a. As a result, the output terminal 15 outputs the data A ₁₃ that is stored in the flip-flop 11 ₅ and then shifted and taken out.

In FIG. 19, at the time when the next data B ₆ after the above data B ₅ arrives at the input terminal 10, the data A ₁₄ is stored in the flip-flop 11 ₅ and the data A ₁₄ is stored in the flip-flop 11 _4.
Stores the data A ₁₅ , the flip-flop 11 ₃ stores the data B ₀ , the flip-flop 11 ₂ stores the data B ₁ , and the flip-flop 11 ₁ stores the data B ₅ . Here, in order to rearrange the data, all the enable signals of the terminals 12 _{1 to} 12 ₄ are turned on,
As a result, the data shift is performed in each of the flip-flops 11 _{1 to} 11 ₅ . Further, at this time, the switch selection switch 14 selects the switch selection terminal 14a. Thus, from the output terminal 15, data A ₁₄ taken out is shifted after being stored in the flip-flop 11 ₅ is output.

In FIG. 20, at the time when the next data B ₂ after the above data B ₆ arrives at the input terminal 10, the flip-flop 11 ₅ receives the data A ₁₅ and the flip-flop 11 ₄ returns.
Stores data B ₀ , flip-flop 11 ₃ stores data B ₁ , flip-flop 11 ₂ stores data B ₅ , and flip-flop 11 ₁ stores data B ₆ . Here, in order to rearrange the data, all the enable signals of the terminals 12 _{1 to} 12 ₄ are turned on,
As a result, the data shift is performed in each of the flip-flops 11 _{1 to} 11 ₅ . Further, at this time, the switch selection switch 14 selects the switch selection terminal 14a. As a result, the output terminal 15 outputs the data A ₁₅ that is stored in the flip-flop 11 ₅ and then shifted and taken out.

By performing the above-described processing, the data supplied in the order of FIG. 3 can be output in the order of FIG. After that, by repeating such processing, the data rearrangement processing can be performed on the input data sequence that is sequentially supplied.

As described above, in the specific example circuit of the first embodiment of the present invention, each of the constituent elements is only the flip-flop and the changeover selection switch. The circuit scale is smaller than that of the configuration used, and high-speed operation is possible. Therefore,
For example, in image data processing of 8 rows and 8 columns, for example, D
High-speed processing can be performed for processing that requires conversion from rows to columns such as CT, which is extremely effective.

Next, FIG. 21 shows the configuration of the second embodiment of the data string rearrangement circuit of the present invention. The data string rearrangement circuit of FIG. 21 rearranges the order of each data of the input data string supplied to the input terminal 40 and outputs the output terminal 45.
It is a data string rearrangement circuit for outputting from. In addition, in the second embodiment, the configuration of FIG. 22 shows the configuration in each shift register (r) of FIG. For this reason,
In the configuration of FIG. 22, the terminal 30 is supplied with the input data via the input terminal 40 of FIG. 21 or the output from the shift register of the previous stage, and the output from the terminal 35 of FIG. 22 is the shift of the latter stage of FIG. It is sent to a register or a changeover selection switch.

That is, in FIG. 21 and FIG. 22, the data string rearrangement circuit of the second embodiment is supplied with each data of the input data string as shown in FIG. As shown in FIG. 21, a flip-flop (FF) that shifts the stored data according to an enable signal supplied from the terminal 42 as shown in FIG. 21 and a plurality of switched selection terminals 44S ₀ , 44S ₁ ,
, 44S _q by selecting one of the selected terminals to be switched, the plurality of switched terminals 44S _{0 to} 44S.
And a changeover selection switch 44 for selectively outputting only one signal from the plurality of input signals supplied to S _q ,
A plurality of the above-mentioned flip-flops (for example, flip-flops 31 ₁ , 31 ₂ , ..., 31 _p as shown in FIG. 22) are provided, and a plurality of shift registers which are first rearranging means in which the respective flip-flops are connected in cascade are further provided. (For example, the shift registers 41 ₁ , 41 ₂ , ..., 41 in FIG.
_q ) are provided to connect the shift registers 41 _{1 to} 41 _q in cascade, and the changeover selection switch 44 selectively outputs the output from the connection point of the cascaded shift registers 41 _{1 to} 41 _q as the plurality of input signals. The input data string is rearranged by outputting to. The changeover selection switch 44 is controlled by a changeover control signal from a control circuit (not shown) via the terminal 43. In addition, each shift register 4
The enable signals supplied to the terminals 42 ₁ , 42 ₂ , ..., 42 _q of 1 _{1 to} 41 _q are also supplied from the control circuit.

It should be noted that in the second embodiment, as shown in FIG.
As shown in FIG. 3, the configuration shown in FIG. 22 is used as a second rearrangement means (R), and a plurality of the configurations shown in FIG. 22 (second rearrangement means 51, 51 ₂ , ..., 51 _r ) are provided. It is also possible to make a cascade connection. In this case, the data output from the output terminal 45 in FIG. 21 is sent to the second rearrangement unit or the output terminal 55 in the latter stage of the configuration in FIG.
As a result, it is possible to carry out the data sequence rearrangement process with the configuration of FIG. 21 several times in succession to perform the desired rearrangement.

Now, referring to FIGS. 24 to 55, the second
A specific example of the data string rearrangement process in the embodiment will be described.

FIG. 24 shows a concrete example of the data string rearrangement circuit of the second embodiment shown in FIGS. 21 and 22. The data string rearrangement circuit of FIG.
00 is a data string rearrangement circuit that rearranges the order of the respective data of the input data string supplied to 00 and outputs it from the output terminal 125, as in the specific example of the first embodiment described above.
For example, the image data rearrangement processing such as the zigzag scanning used when compressing the image data is performed.
The configuration of FIG. 24 is obtained by cascade-connecting two circuits of the second embodiment, and the configuration of the input stage of FIG. 24 is one shift register in FIG. In this example, the number of flip-flops is two, and the configuration of the output stage is an example in which a shift register including three flip-flops and a shift register including two flip-flops are provided. .

That is, in the specific circuit of FIG. 24, the enable signal is supplied to the terminals 102, 112 and 122, and the shift register 101 including the flip-flops 101 ₁ and 101 ₂ and the flip-flop 111.
Shift register 111 including ₁ , 111 ₂ , and 111 _3.
And a shift register 121 including flip-flops 121 ₁ and 121 ₂ are connected in cascade.

Here, the changeover selection switch 104 having the changeover selection terminals 104a and 104b is provided between the shift registers 101 and 111, and the output of the flip-flop 101 ₂ is output to the changeover selection terminal 104a. And the input of the flip-flop 101 ₁ (input to the input terminal 100) is supplied to the switched selection terminal 104b. Further, the flip-flops 101 ₁ and 101 ₂ of the shift register 101 is the enable signal from terminal 102 is supplied to the change-over selector switch 104 switching control signal through the terminal 103 are supplied.

Further, in the subsequent stage of the shift register 121, 3
Input 1-output selector selection switch 124 is provided, this is to be switched and selected terminal 124a of the change-over selector switch 124 the output of flip-flop 121 ₂ of the shift register 121 are supplied, the switching selection switch to be switched and selected terminal 124c The output of 104 is supplied, and the switched selection terminal 124b is connected to the connection point between the shift registers 111 and 121. In addition, an enable signal via the terminal 112 is applied to each flip-flop of the shift register 111.
An enable signal is supplied to each flip-flop 21 through a terminal 122, and a changeover control signal is supplied to a changeover selection switch 124 through a terminal 123. These enable signals and switching control signals are also supplied from a control circuit (not shown) as in the above.

In FIG. 24, a plurality of pieces of data, that is, each piece of data of an input data row composed of each piece of data of 4 rows and 4 columns as shown in FIG. A ₀ , A ₁ , A ₅ , A
₆ , A ₂ , A ₄ , A ₇ , A ₁₂ , A ₃ , A ₈ , A ₁₁ ,
It is assumed that A ₁₃ , A ₉ , A ₁₀ , A ₁₄ , and A ₁₅ are serially input in this order). The configuration of FIG. 24 corresponds to that of FIG.
And 22 shows an example in which two configurations of 22 are connected in series,
In the configuration of the input stage, the order of each data of the above input data string is A
₀ , A ₁ , A ₅ , A ₆ , A ₂ , A ₄ , A ₇ , A ₁₂ ,
_{A 3, A 13, A 8} , A 11, A 14, A 15, A 9, A 10 rearranged in order of further order of data rearranged by the arrangement of the input stage in the construction of output stage A _0, A ₁ ,
A ₂ , A ₃ , A ₄ , A ₅ , A ₆ , A ₇ , A ₈ , A ₉ , A
₁₀ , A ₁₁ , A ₁₂ , A ₁₃ , A ₁₄ , A ₁₅ shown in FIG.
The data is rearranged in the order of data obtained by zigzag scanning. The rearranged data is output from the output terminal 125. Also in the configuration of FIG. 24, the switching control signal and the enable signal are signals corresponding to the zigzag scanning of FIG.

25 to 40 show the same structure as the input stage structure (shift register 101, changeover selection switch 104, etc.) of FIG. 24. First, in FIG. 25, the data A ₀ , A ₁ , A ₅ , A ₆ , A ₂ , A ₄ , A ₇ , A ₁₂ , from the first row of FIG.
_{A 3, A 8, A 11} , A 13, A 9, A 10, A 14, coming is serially inputted in the order of A _15. At this time, the enable signal supplied to the terminal 102 is ON (for example, high level).
It is said that As a result, each flip-flop 101 ₁ ,
At 101 ₂ , the supplied data are sequentially shifted. Therefore, when the next data A ₅ of the data A ₁ came to an input terminal 100 (time), the flip-flop 101 ₂ is stored data A _0, data A ₁ is stored in the flip-flop 101 ₁ Will be. Further, in this case, the changeover selection switch 104 selects the terminal 1a to be changed over by the changeover control signal via the terminal 103 (not shown).
From 05, the data A _{0 that} is stored in the flip-flop 101 ₂ and then shifted and taken out is output.

Next, referring to FIG. 26, as shown in FIG. 3, the data A ₅ next to the data A ₅ is input to the input terminal 100.
The time (time) _{of 6} has come, the data A ₁ to the flip-flop 101 ₂ is, so that the stored data A ₅ are the flip-flop 101 _1. The enable signal at this time is also turned on. Further, in this case, by selecting the switched selection terminal 104a of the selection switch 104, the terminal 105 outputs the data A ₁ stored in the flip-flop 101 ₂ and then shifted and taken out. become.

Further, in FIG. 27, at the time when the next data A ₂ after the above data A ₆ arrives at the input terminal 100 as shown in FIG. 3, the flip-flop 101 ₂ receives the data A ₅
However, the data A ₆ is stored in the flip-flop 101 ₁ . The enable signal at this time is also turned on. Further, the changeover selection switch 104 selects the changeover selection terminal 104a, and the terminal 105 outputs the data A _{5 which} is stored in the flip-flop 101 ₂ and then shifted and taken out.

Similarly, the input terminal 1 in FIG.
Data A ₄ is supplied to 00 and data A ₆ is output from the terminal 105, data A ₇ is supplied to the input terminal 100 in FIG. 29, data A ₂ is output from the terminal 105, and in FIG. Data A _{12 on} input terminal 100
Is supplied and data A ₄ is output from the terminal 105,
In FIG. 31, the data A ₃ is supplied to the input terminal 100 and the data A ₇ is output from the terminal 105. In FIG. 32, the data A ₄ is supplied to the input terminal 100 and the data A ₁₂ is output from the terminal 105. In FIG. 33, the data A ₁₁ is supplied to the input terminal 100 and the data A ₃ is output from the terminal 105.

Further, in FIG. 34, at the time when the next data A ₁₃ of the above data A ₁₁ arrives at the input terminal 100, the data A ₈ is stored in the flip-flop 101 ₂ and the data A ₁₁ is stored in the flip-flop 101 _1. It is stored. At this time, the enable signal to the terminal 102 is turned off. As a result, the flip-flops 101 ₁ and 101
_{In 2} , the acquisition of new data is stopped and the already stored data is held (data A ₈ and A ₁₁ ). Further, at this time, as the changeover selection switch 104, the changeover selection terminal 104b is selected. As a result, the terminal 105
Therefore, the data A ₁₃ supplied to the input terminal 100 is directly output.

In FIG. 35 and FIG. 36, the enable signals are both turned on, and the switch selection terminal 104a of the switch selection switch 104 is selected. As a result, in FIG. 35, the data A ₉ is supplied to the input terminal 100 and the terminal 10 receives the data A _9.
5, data A ₈ is output, in FIG. 36, data A ₁₀ is supplied to the input terminal 100 and data A ₁₁ is output from the terminal 105.

In FIGS. 37 and 38, the enable signals are both turned off, and the switch selection terminal 104b of the switch selection switch 104 is selected. As a result, in FIG. 37, the data A ₁₄ is supplied to the input terminal 100 and
5, the data A ₁₄ is output as it is, and the data A ₁₅ is supplied to the input terminal 100 in FIG.
Data A ₁₅ is output from 5 as it is.

In FIGS. 39 and 40, the enable signals are both turned on, and the switch selection terminal 104a of the switch selection switch 104 is selected. Input terminal 1 of FIG. 39
00 is supplied with the first data B ₀ of the next 4 rows and 4 columns of the data ₁₅ (similar to FIG. 3 and replacing each data A in the drawing of FIG. 3 with B). As a result, in FIG. 39, the data B ₀ is supplied to the input terminal 100 and the data A ₉ is output from the terminal 105, and in FIG.
0 is supplied with the next data B ₁ of the data B ₀ and the terminal 10
Data A ₁₅ is output from 5.

As described above, according to the input stage configuration of FIG. 24, the order (A ₀ , A ₁ , A ₅ , A ₆ , A ₂ , A ₂ ,
A ₄ , A ₇ , A ₁₂ , A ₃ , A ₈ , A ₁₁ , A ₁₃ , A ₉ , A
_The data supplied in the order of ₁₀ , A ₁₄ , A ₁₅ )
₀ , A ₁ , A ₅ , A ₆ , A ₂ , A ₄ , A ₇ , A ₁₂ ,
Processing for rearranging A ₃ , A ₁₃ , A ₈ , A ₁₁ , A ₁₄ , A ₁₅ , A ₉ , and A ₁₀ is performed.

41 to 56 show the same configuration as the output stage configuration (shift registers 111, 121, changeover selection switch 124, etc.) shown in FIG. First, in FIG. 41, the terminal 105 is the same as the terminal 105 in FIGS. 25 to 40. The terminal 105 is connected to the terminal shown in FIG.
Data rearranged by the input stage configuration of A ₀ ,
A ₁ , A ₅ , A ₆ , A ₂ , A ₄ , A ₇ , A ₁₂ , A ₃ , A
Serial inputs are made in the order of ₁₃ , A ₈ , A ₁₁ , A ₁₄ , A ₁₅ , A ₉ , and A ₁₀ . At this time, the terminals 112 and 122
The enable signal supplied to is turned on. As a result, each of the flip-flops 111 ₁ , 111 ₂ , 111 ₃
And 121 ₁ and 121 ₂ , the supplied data are sequentially shifted. Therefore, the next data A ₄ came time of the data A ₂ to the terminal 105, the flip-flop 121 ₂ is stored data A _0, data A ₁ to the flip-flop 121 _1, flip-flop 1
11 ₃ stores the data A ₅ , the flip-flop 111 ₂ stores the data A ₆ , and the flip-flop 111 ₁ stores the data A ₂ . Further, in this case, the changeover selection switch 124 is operated by the changeover control signal via the terminal 123 (not shown).
When a is selected, the data A _{0 that} is stored in the flip-flop 121 ₂ and then shifted and taken out is output from the terminal 125.

Next, in FIG. 42, at the time when the next data A ₇ after the above data A ₄ arrives at the terminal 105, the data A ₁ is stored in the flip-flop 121 ₂ , and the data A ₅ is stored in the flip-flop 121 _1. , Flip-flop 111 ₃
The data A ₆ is stored in the flip-flop 111 ₂ , the data A ₂ is stored in the flip-flop 111 ₂ , and the data A ₄ is stored in the flip-flop 111 ₁ . At this time, the enable signal is ON, and the selection switch 104 is the selected terminal 10 to be switched.
By selecting 4a, the data A _{1 that} is stored in the flip-flop 121 ₂ and then shifted and taken out is output from the terminal 125.

Further, in FIG. 43, when the data A ₁₂ arrives at the terminal 105, the data A ₅ is stored in the flip-flop 121 ₂ and the data A ₁₂ is stored in the flip-flop 121 _1.
6 , the data A ₂ is stored in the flip-flop 111 ₃ , the data A ₄ is stored in the flip-flop 111 ₂ , and the data A ₇ is stored in the flip-flop 111 ₁ . At this time, the enable signal to the terminal 122 is set to O.
FF, and the enable signal to the terminal 112 is turned on. As a result, the flip-flops 121 ₁ and 121
_{At 2} , the acquisition of new data is stopped and the already stored data is retained (data A ₅ and A ₆ ), and the flip-flops 111 ₁ , 111 ₂ , 111 ₃ perform data shift. At this time, as the changeover selection switch 124, the changeover selected terminal 124b is selected. As a result, the data A ₂ stored in the flip-flop 111 ₃ and then shifted and taken out is output from the terminal 125.

In FIG. 44, data A ₃ is input to the terminal 105.
When the time comes, the data A ₅ is stored in the flip-flop 121 ₂ and the data A ₆ is stored in the flip-flop 121 ₁ .
The flip-flop 111 ₃ stores data A ₄ , the flip-flop 111 ₂ stores data A ₇ , and the flip-flop 111 ₁ stores data A ₁₂ . At this time, the enable signals to the terminals 112 and 122 are turned off. As a result, the fetching of new data is stopped in each flip-flop, and the already stored data is retained (data A ₅ , A ₆ , A ₄ , A ₇ , A ₁₂ ). At this time, the selection terminal 124c is selected as the selection switch 124. As a result, the data A ₃ supplied to the terminal 105 is directly output from the terminal 125.

In FIG. 45, data A ₁₃ is input to the terminal 105.
When the time comes, the data A ₅ is stored in the flip-flop 121 ₂ and the data A ₆ is stored in the flip-flop 121 ₁ .
The flip-flop 111 ₃ stores data A ₄ , the flip-flop 111 ₂ stores data A ₇ , and the flip-flop 111 ₁ stores data A ₁₂ . At this time, the enable signal to the terminal 122 is turned off and the terminal 1
The enable signal to 12 is turned on. As a result, the fetching of new data is stopped in the flip-flops 121 ₁ and 121 ₂ , and the data already stored (data A ₅ and A ₆ ) is held, and the flip-flops 111 ₁ , 111 ₂ , and 111 ₃ are held. Data shift is performed. Further, as the changeover selection switch 124, the changeover selection terminal 124b is selected. As a result, the data A ₄ stored in the flip-flop 111 ₃ and then shifted and taken out is output from the terminal 125.

In FIG. 46, FIG. 47, and FIG. 48, the enable signals are both turned on, and the changeover selection switch 124 is turned on.
The switched selection terminal 124a is selected. Accordingly, in FIG. 46, the data A ₈ is supplied to the terminal 105, the data shift is performed in each flip-flop, and the data A ₈ from the flip-flop 121 ₂ is output from the output terminal.
₅ is output, likewise, data is output A ₆ from the terminal 125 the data A ₁₁ to the terminal 105 is supplied in FIG. 47, from the terminal 125 the data A ₁₄ to the terminal 105 is supplied in FIG. 48 Data A ₇ is output.

Similarly, in FIG. 49, the enable signal to the terminal 122 is turned off and the enable signal to the terminal 112 is turned on, and the switch selection terminal 124b is selected. In FIGS. 50 and 51, each enable signal is selected. Are turned off and the selected terminal to be switched 124c is selected, and the enable signal to the terminal 122 is turned off in FIG.
The enable signal to the terminal 112 is turned on, and the switched selection terminal 124b is selected.
In FIG. 55 and FIG. 56, each enable signal is turned on and the switched selection terminal 124a is selected. As a result, in FIG. 49, the data A ₁₅ is supplied to the terminal 105 and the data A ₈ is output from the terminal 125, and in FIG. 50, the data A ₉ is supplied to the terminal 105 and the data A ₉ is directly output from the terminal 125. 51, the data A ₁₀ is supplied to the terminal 105 and the data A ₁₀ is directly output from the terminal 125. In FIG. 52, the data A ₁₅ is output to the terminal 105.
The data B ₀ of the next 4 rows and 4 columns is supplied and the data A ₁₁ is output from the terminal 125. In FIG. 53, the data B ₁ is supplied to the terminal 105 and the data A ₁₂ is output from the terminal 125. 54, the data B ₅ is supplied to the terminal 105 and the data A ₁₃ is output from the terminal 125. In FIG. 55, the data B ₆ is supplied to the terminal 105 and the data A ₁₄ is output from the terminal 125 in FIG. Then, the data B ₂ is supplied to the terminal 105 and the data A ₁₅ is output from the terminal 125.

As described above, according to the input stage configuration of FIG. 24, A ₀ , A ₁ , A ₅ , A ₆ , A ₂ , A ₄ , A ₇ , A
₁₂ , A ₃ , A ₁₃ , A ₈ , A ₁₁ , A ₁₄ , A ₁₅ , A ₉ , A ₁₀
The data supplied in the order of A ₀ , A ₁ , A ₂ , A ₃ , A
₄ , A ₅ , A ₆ , A ₇ , A ₈ , A ₉ , A ₁₀ , A ₁₁ ,
The data items A ₁₂ , A ₁₃ , A ₁₄ , and A ₁₅ are rearranged in the order of the data obtained by the zigzag scanning of FIG.

Also in the configuration of FIG. 24, high-speed operation and miniaturization of the circuit scale can be realized as in the concrete circuit of the first embodiment described above.

Further, according to the specific example circuit configuration of the second embodiment of FIG. 24, the changeover selection switches 104 and 1 are provided.
Since 24 is for 2-input 1-output and 3-input 1-output, it is faster than 5-input 1-output such as the changeover selection switch 14 of the concrete example circuit of the first embodiment shown in FIG. It is possible to operate with.

As another specific example of the above-described second embodiment of the present invention, a configuration as shown in FIG. 57 can be cited. Another specific example circuit is a circuit that performs processing similar to the specific example circuit of FIG. 24 described above, and shows, for example, a case where input data has a 3-bit word length, and parallel / serial in the input stage. After conversion, this data is rearranged as bit serial data.

That is, in the configuration of FIG. 57,
Parallel / serial conversion circuit 200, serial / parallel conversion circuit 201, and three flip-flops 131
_A shift register 131 composed of ₁ , 131 ₂ , 131 _3.
And a shift register 141 composed of flip-flops 141 _{1 to} 141 ₃ , and flip-flops 151 ₁ to 15
Shift register 151 composed of 1 ₃ and shift register 161 composed of flip-flops 161 _{1 to} 161 _3.
When a shift register 171 composed of flip-flops 171 _{1 to 171 3,} the flip-flop 181 _1-18
A shift register 181 composed of 1 _3, and a shift register 191 composed of flip-flops 191 _{1 to 191 3,} it is connected in cascade. Further, between the shift registers 141 and 151, there is a switched selection terminal 134.
A changeover selection switch 134 having a and 134b is provided, the output of the flip-flop 141 ₂ is supplied to the changeover selected terminal 134a, and the input of the flip-flop 131 ₁ is supplied to the changeover selected terminal 134b. It has become so. Further, the shift register 13
A first flip-flop 131 ₁ to 131 _3, the enable signal from the terminal 132 is supplied to the flip-flop 141 _{1 to 141 3} of the shift register 141, switching control signals to switching selection switch 134 via the terminal 133 It is being supplied.

Further, in the subsequent stage of the shift register 191, there are 3
Is provided changeover selection switch 194 of the input 1 output, this is to be switched and selected terminal 194a of switching the selection switch 194 is supplied the output of the flip-flop 191 ₃ of the shift register 191, the switching selection switch to be switched and selected terminal 194c The output of 134 is supplied, and the switched selection terminal 194b is connected to the connection point between the shift registers 171 and 181. Further, the enable signal via the terminal 152 is supplied to each flip-flop of the shift registers 151, 161, 171.
The flip-flops of the shift registers 181 and 191 are supplied with an enable signal via a terminal 182, and the changeover selection switch 194 is supplied with a changeover control signal via a terminal 193. These enable signals and switching control signals are also supplied from a control circuit (not shown) as in the above.

In the circuit of FIG. 57, the input terminal 13
Each of the data of the 3-bit word length is supplied to 0 ₁ , 130 ₂ , 130 ₃ . For example, the input terminal 130
_The most significant bit (MSB) is supplied to ₁ , and the least significant bit (LSB) is supplied to the input terminal 130 ₃ . This input data is supplied to the subsequent stage configuration as serial data by the parallel / serial conversion circuit 200.

The shift register 131 corresponds to the flip-flop 101 ₁ shown in FIG. 24, the shift register 141 is the flip-flop 101 _2, and the changeover selection switch 134 is the changeover selection switch 104.
And the shift register 151 is the flip-flop 11
1 ₁ , the shift register 161 is the flip-flop 111 ₂ , the shift register 171 is the flip-flop 111 ₃ , the shift register 181 is the flip-flop 121 ₁ , the shift register 191 is the flip-flop 121 ₂ , and switching selection is performed. The switch 194 corresponds to the changeover selection switch 124. Also, the terminal 132 corresponds to the terminal 102, the terminal 133 is the terminal 103, the terminal 152 is the terminal 112, and the terminal 18.
2 corresponds to the terminal 122, and the terminal 193 corresponds to the terminal 123. Since the operation of each unit in FIG. 57 is the same as that in FIG. 24 described above, the description thereof will be omitted. However, in the configuration of FIG. 57, unlike the circuit of FIG. 24, processing is performed in units of 3 bits. The data in which the data strings have been rearranged is again converted into 3-bit word length data by passing through the serial / parallel conversion circuit 201, and output from the output terminals 191 _{1 to} 191 ₃ .

Also in the configuration of FIG. 57, the same processing as that of FIG. 24 described above can be performed. In the case of processing data having a 3-bit word length in this manner, instead of the configuration shown in FIG. 57, three configurations shown in FIG. 24 are arranged in parallel and each digit of the 3-bits shown in FIG. The above configurations may be assigned one by one and processed. However, by using FIG. 57, it is possible to shorten the wiring length connecting the respective constituent elements. Further, the number of changeover selection switches can be reduced to 1/3 as compared with the case where three configurations in FIG. 24 are arranged in parallel. It should be noted that, in the future, as the technology advances, it can be expected that other arithmetic circuits can also operate at high speed. When this high speed operation becomes possible, the parallel / serial conversion circuit 200 and the serial / serial conversion circuit 200 of FIG. Parallel conversion circuit 201
Are unnecessary, and the configuration can be further simplified.

As described above, according to the data string rearrangement circuit of the embodiment of the present invention, the RAM is not used and only the flip-flops and the changeover selection switches are used. Therefore, high speed operation is possible. There is. Further, when a RAM is used as in the conventional example, this RAM cannot operate at a high speed enough to handle data in bit serial. Therefore, when exchanging data with the outside, the serial / parallel conversion circuit and the parallel / serial conversion are reversed. A circuit is required, and the configuration becomes large.

[0072]

As described above, in the data string rearranging circuit of the present invention, a plurality of first rearranging means including a memory means or a plurality of memory means are provided, and each memory means or the first rearranging means is cascaded. Since the connecting means and the selecting means selectively switch the output from the connection points of the plurality of storage means or the first rearranging means connected in cascade to output only one, the circuit scale is small, and It is possible to perform rearrangement processing of data strings at high speed.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a first embodiment of a data string rearrangement circuit of an embodiment of the present invention.

FIG. 2 is a block circuit diagram of a specific example circuit of the first embodiment.

FIG. 3 is a diagram showing an input order of image data.

FIG. 4 is a diagram showing image data on which a data string rearrangement process is performed.

FIG. 5 shows data A ₀ in the specific example circuit of the first embodiment.
FIG. 7 is a diagram for explaining the operation when outputting the.

FIG. 6 shows data A ₁ in the specific circuit of the first embodiment.
FIG. 7 is a diagram for explaining the operation when outputting the.

FIG. 7 shows data A ₂ in the specific circuit of the first embodiment.
FIG. 7 is a diagram for explaining the operation when outputting the.

FIG. 8 shows data A ₃ in the specific circuit of the first embodiment.
FIG. 7 is a diagram for explaining the operation when outputting the.

FIG. 9 shows data A ₄ in the specific example circuit of the first embodiment.
FIG. 7 is a diagram for explaining the operation when outputting the.

FIG. 10 shows data A in the specific example circuit of the first embodiment.
FIG. 6 is a diagram for explaining the operation when outputting ₅ .

FIG. 11 shows the data A in the specific example circuit of the first embodiment.
FIG. 6 is a diagram for explaining the operation when outputting ₆ .

FIG. 12 shows the data A in the specific example circuit of the first embodiment.
FIG. 8 is a diagram for explaining the operation when outputting ₇ .

FIG. 13 shows the data A in the specific example circuit of the first embodiment.
FIG. ₈ is a diagram for explaining the operation when outputting ₈ .

FIG. 14 shows the data A in the specific example circuit of the first embodiment.
FIG. ₉ is a diagram for explaining an operation when ₉ is output.

FIG. 15 shows the data A in the specific example circuit of the first embodiment.
FIG. 6 is a diagram for explaining an operation when outputting ₁₀ .

FIG. 16 shows data A in the specific example circuit of the first embodiment.
FIG. ₁₁ is a diagram for explaining an operation when outputting ₁₁ .

FIG. 17 shows the data A in the specific example circuit of the first embodiment.
FIG. 6 is a diagram for explaining the operation when outputting ₁₂ ;

FIG. 18 shows the data A in the specific example circuit of the first embodiment.
FIG. 7 is a diagram for explaining the operation when outputting ₁₃ ;

FIG. 19 shows the data A in the specific example circuit of the first embodiment.
FIG. 10 is a diagram for explaining the operation when outputting ₁₄ ;

FIG. 20 shows the data A in the specific example circuit of the first embodiment.
FIG. 6 is a diagram for explaining the operation when outputting ₁₅ .

FIG. 21 is a block circuit diagram showing a data string rearrangement circuit according to a second embodiment of the present invention.

FIG. 22 is a block circuit diagram showing the configuration in the shift register of the second embodiment circuit.

FIG. 23 is a block circuit diagram showing a configuration in which the circuits of the second embodiment are further connected in cascade.

FIG. 24 is a block circuit diagram showing a specific example circuit of the second embodiment.

FIG. 25 is a diagram for explaining an operation when outputting data A ₀ in the input stage configuration of the specific example circuit of the second example.

FIG. 26 is a diagram for explaining an operation when outputting data A ₁ in the input stage configuration of the specific example circuit of the second example.

FIG. 27 is a diagram for explaining the operation when outputting data A ₅ in the input stage configuration of the specific example circuit of the second example.

FIG. 28 is a diagram for explaining the operation when outputting data A ₆ in the input stage configuration of the specific example circuit of the second example.

FIG. 29 is a diagram for explaining an operation when outputting data A ₂ in the input stage configuration of the specific example circuit of the second example.

FIG. 30 is a diagram for explaining an operation when outputting data A ₄ in the input stage configuration of the specific example circuit of the second example.

FIG. 31 is a diagram for explaining an operation when outputting data A ₇ in the input stage configuration of the specific example circuit of the second example.

FIG. 32 is a diagram for explaining an operation when outputting data A ₁₂ in the input stage configuration of the specific example circuit of the second example.

FIG. 33 is a diagram for explaining the operation when outputting data A ₃ in the input stage configuration of the specific example circuit of the second example.

FIG. 34 is a diagram for explaining an operation when outputting data A ₁₃ in the input stage configuration of the specific example circuit of the second example.

FIG. 35 is a diagram for explaining an operation when outputting data A ₈ in the input stage configuration of the specific example circuit of the second example.

FIG. 36 is a diagram for explaining the operation when outputting data A ₁₁ in the input stage configuration of the specific example circuit of the second example;

FIG. 36 is a diagram for explaining an operation when outputting data A ₁₄ in the input stage configuration of the specific example circuit of the second example.

FIG. 38 is a diagram for explaining an operation when outputting data A ₁₅ in the input stage configuration of the specific example circuit of the second example;

FIG. 39 is a diagram for explaining an operation when outputting data A ₉ in the input stage configuration of the specific example circuit of the second example;

FIG. 40 is a diagram for explaining an operation when outputting data A ₁₀ in the input stage configuration of the specific example circuit of the second example.

FIG. 41 is a diagram for explaining the operation when outputting data A _{0 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 42 is a diagram for explaining an operation when outputting data A _{1 in} the configuration of the output stage of the specific example circuit of the second example;

FIG. 43 is a diagram for explaining an operation when outputting data A _{2 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 44 is a diagram for explaining the operation when outputting data A _{3 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 45 is a diagram for explaining the operation when outputting data A _{4 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 46 is a diagram for explaining an operation when outputting data A _{5 in} the configuration of the output stage of the specific example circuit of the second example;

FIG. 47 is a diagram for explaining an operation when outputting data A _{6 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 48 is a diagram for explaining the operation when outputting the data A _{7 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 49 is a diagram for explaining an operation when outputting data A _{8 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 50 is a diagram for explaining an operation when outputting data A _{9 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 51 is a diagram for explaining the operation when outputting data A _{10 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 52 is a diagram for explaining an operation when outputting data A _{11 in} the configuration of the output stage of the specific example circuit of the second example;

FIG. 53 is a diagram for explaining the operation when outputting the data A _{12 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 54 is a diagram for explaining the operation when outputting the data A _{13 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 55 is a diagram for explaining the operation when outputting data A _{14 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 56 is a diagram for explaining an operation when outputting data A _{15 in} the configuration of the output stage of the specific example circuit of the second example;

FIG. 56 is a block circuit diagram showing the configuration of another specific example circuit of the second embodiment.

FIG. 57 is a block circuit diagram showing a configuration of a conventional data string rearrangement circuit.

[Explanation of symbols]

21 _{1 to} 21 _m ... Flip-flops 24, 44 ... Changeover selection switches 41 _{1 to} 41 _q ... Shift register

[Procedure amendment]

[Submission date] November 5, 1991

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[Correction content]

As a circuit for rearranging the input data sequence used when performing such two-dimensional DCT processing, for example, a circuit having a configuration as shown in FIG. 58 is usually used. In the configuration of FIG. 58, the input terminal 1 is supplied with a serial input data string composed of a group of data to be rearranged. This input data string is sequentially written to either one of the RAMs 3 and 4 having the same number of words as the number of data of a group of the input data string via the changeover switch 2. The data written in the RAMs 3 and 4 is read according to the read address data RA. At this time, the read address data RA is the address data such that each data of the input data string is read in a desired order. Controlled by. In this way, by controlling the read address data RA when the data is read from the RAM, the rearrangement of the data string is realized. That is, R
When writing data to the AM, for example, write address data WA is used so that data is sequentially written from address 0 of the RAM, and when reading data, for example, the address at the time of writing is used. Are read from different read addresses and the data is read in a desired read order to rearrange the data strings. The data string read from one of the RAMs 3 and 4 is output as an output data string from the output terminal 6 via the changeover switch 5.

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Also in the configuration of FIG. 57, the same processing as that of FIG. 24 described above can be performed. In the case of processing data having a 3-bit word length in this manner, instead of the configuration shown in FIG. 57, three configurations shown in FIG. 24 are arranged in parallel and each digit of the 3-bits shown in FIG. The above configurations may be assigned one by one and processed. However, in FIG.
By using, it is possible to shorten the wiring length that connects each component. Further, the number of changeover selection switches can be reduced to 1/3 as compared with the case where three configurations in FIG. 24 are arranged in parallel. In the future, when technology advances, it can be expected that other arithmetic circuits will also be able to operate at high speed. If this high-speed operation becomes possible, other arithmetic circuits will also become bit-serial arithmetic circuits. The parallel / serial conversion circuit 200 and the serial / parallel conversion circuit 201 of 57 are unnecessary, and the configuration can be further simplified.

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[Submission date] June 4, 1993

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[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a first embodiment of a data string rearrangement circuit of an embodiment of the present invention.

FIG. 2 is a block circuit diagram of a specific example circuit of the first embodiment.

FIG. 3 is a diagram showing an input order of image data.

FIG. 4 is a diagram showing image data on which a data string rearrangement process is performed.

FIG. 5 shows data A ₀ in the specific example circuit of the first embodiment.
FIG. 7 is a diagram for explaining the operation when outputting the.

FIG. 6 shows data A ₁ in the specific example circuit of the first embodiment.
FIG. 7 is a diagram for explaining the operation when outputting the.

FIG. 7 shows data A ₂ in the specific example circuit of the first embodiment.
FIG. 7 is a diagram for explaining the operation when outputting the.

FIG. 8 shows data A ₃ in the specific example circuit of the first embodiment.
FIG. 7 is a diagram for explaining the operation when outputting the.

FIG. 9 shows the data A ₄ in the specific example circuit of the first embodiment.
FIG. 7 is a diagram for explaining the operation when outputting the.

FIG. 10 shows data A in the specific example circuit of the first embodiment.
₅ is a diagram for explaining an operation when outputting ₅ ; FIG.

FIG. 11 shows the data A in the specific example circuit of the first embodiment.
₆ is a diagram for explaining the operation when outputting ₆ ; FIG.

FIG. 12 shows the data A in the specific example circuit of the first embodiment.
FIG. ₇ is a diagram for explaining an operation when ₇ is output.

FIG. 13 shows the data A in the specific example circuit of the first embodiment.
FIG. ₈ is a diagram for explaining the operation when outputting ₈ ;

FIG. 14 shows the data A in the specific example circuit of the first embodiment.
₉ is a diagram for explaining an operation when ₉ is output. FIG.

FIG. 15 shows the data A in the specific example circuit of the first embodiment.
FIG. ₁₀ is a diagram for explaining an operation when outputting ₁₀ .

FIG. 16 shows data A in the specific example circuit of the first embodiment.
It is a figure for demonstrating the operation | movement at the time of outputting ₁₁ .

FIG. 17 shows the data A in the specific example circuit of the first embodiment.
FIG. 10 is a diagram for explaining the operation when outputting ₁₂ ;

FIG. 18 shows the data A in the specific example circuit of the first embodiment.
₁₃ is a diagram for explaining an operation when outputting ₁₃ ; FIG.

FIG. 19 shows the data A in the specific example circuit of the first embodiment.
It is a figure for demonstrating the operation | movement at the time of outputting ₁₄ .

FIG. 20 shows the data A in the specific example circuit of the first embodiment.
It is a figure for demonstrating the operation | movement at the time of outputting ₁₅ .

FIG. 21 is a block circuit diagram showing a data string rearrangement circuit according to a second embodiment of the present invention.

FIG. 22 is a block circuit diagram showing the configuration in the shift register of the second embodiment circuit.

FIG. 23 is a block circuit diagram showing a configuration in which the circuits of the second embodiment are further connected in cascade.

FIG. 24 is a block circuit diagram showing a specific example circuit of the second embodiment.

FIG. 25 is a diagram for explaining the operation when outputting data A ₀ in the input stage configuration of the specific example circuit of the second example.

FIG. 26 is a diagram for explaining an operation when outputting data A ₁ in the input stage configuration of the specific example circuit of the second example.

FIG. 27 is a diagram for explaining an operation when outputting data A ₅ in the input stage configuration of the specific example circuit of the second example.

FIG. 28 is a diagram for explaining an operation when outputting data A ₆ in the input stage configuration of the specific example circuit of the second example.

FIG. 29 is a diagram for explaining the operation when outputting data A ₂ in the input stage configuration of the specific example circuit of the second example.

FIG. 30 is a diagram for explaining an operation when outputting data A ₄ in the input stage configuration of the specific example circuit of the second example.

FIG. 31 is a diagram for explaining an operation when outputting data A ₇ in the input stage configuration of the specific example circuit of the second example.

FIG. 32 is a diagram for explaining an operation when outputting data A ₁₂ in the input stage configuration of the specific example circuit of the second example.

FIG. 33 is a diagram for explaining an operation when outputting data A ₃ in the input stage configuration of the specific example circuit of the second example.

FIG. 34 is a diagram for explaining an operation when outputting data A ₁₃ in the input stage configuration of the specific example circuit of the second example;

FIG. 35 is a diagram for explaining an operation when outputting data A ₈ in the input stage configuration of the specific example circuit of the second example.

FIG. 36 is a diagram for explaining an operation when outputting data A ₁₁ in the input stage configuration of the specific example circuit of the second example;

FIG. 37 is a diagram for explaining an operation when outputting data A ₁₄ in the input stage configuration of the specific example circuit of the second example.

FIG. 38 is a diagram for explaining an operation when outputting data A ₁₅ in the input stage configuration of the specific example circuit of the second example;

FIG. 39 is a diagram for explaining an operation when outputting data A ₉ in the input stage configuration of the specific example circuit of the second example;

FIG. 40 is a diagram for explaining an operation when outputting data A ₁₀ in the input stage configuration of the specific example circuit of the second example.

FIG. 41 is a diagram for explaining an operation when outputting data A _{0 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 42 is a diagram for explaining the operation when outputting the data A _{1 in} the configuration of the output stage of the specific example circuit of the second example;

FIG. 43 is a diagram for explaining an operation when outputting data A _{2 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 44 is a diagram for explaining an operation when outputting data A _{3 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 45 is a diagram for explaining an operation when outputting data A _{4 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 46 is a diagram for explaining the operation when outputting data A _{5 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 47 is a diagram for explaining the operation when outputting data A _{6 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 48 is a diagram for explaining the operation when outputting data A _{7 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 49 is a diagram for explaining the operation when outputting the data A _{8 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 50 is a diagram for explaining the operation when outputting data A _{9 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 51 is a diagram for explaining the operation when outputting data A _{10 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 52 is a diagram for explaining an operation when outputting data A _{11 in} the configuration of the output stage of the specific example circuit of the second example;

FIG. 53 is a diagram for explaining the operation when outputting data A _{12 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 54 is a diagram for explaining the operation when outputting the data A _{13 in} the configuration of the output stage of the specific example circuit of the second example;

FIG. 55 is a diagram for explaining an operation when outputting data A _{14 in} the configuration of the output stage of the specific example circuit of the second example.

FIG. 56 is a diagram for explaining the operation when outputting the data A _{15 in} the configuration of the output stage of the specific example circuit of the second example;

FIG. 57 is a block circuit diagram showing the configuration of another specific example circuit of the second embodiment.

FIG. 58 is a block circuit diagram showing a configuration of a conventional data string rearrangement circuit.

[Explanation of Codes] 21 _{l to} 21 _m ··· Flip-flops 24, 44 ··· Selection switch 41 _{l to} 41 _q ··· Shift register

Claims (2)

[Claims] 1. A data string rearrangement circuit for rearranging the order of each data of an input data string consisting of a plurality of data and outputting the data, wherein each data of the input data string is supplied and held, and in response to a predetermined signal Storage means for shifting the stored data and a selection means for supplying a plurality of input signals and selectively outputting only one signal from the plurality of input signals. A plurality of storage means are provided and each storage means is connected in cascade, and the selection means selectively outputs the output from the connection point of the plurality of storage means connected in cascade as the plurality of input signals to output the input data string. A data string rearrangement circuit for rearranging the order of each data. 2. A data string rearrangement circuit for rearranging the order of each data of an input data string composed of a plurality of data and outputting the data, wherein each data of the input data string is supplied and held, and in response to a predetermined signal Storage means for shifting the stored data and a selection means for supplying a plurality of input signals and selectively outputting only one signal from the plurality of input signals. A plurality of first rearranging means, each of which is provided with a plurality of storage means connected in cascade, are further provided to connect each first rearranging means in cascade, and the selecting means is connected from the connection point of the first rearranging means connected in cascade. A data string rearrangement circuit for rearranging the order of each data of the input data string by selectively outputting the output of the above as the plurality of input signals. .