JPH06138853A - Matrix type liquid crystal display device and its driving method - Google Patents

Abstract

PURPOSE:To obtain an excellent contrast by the driving method for fast-response STN liquid crystal. CONSTITUTION:The matrix type liquid crystal display device which makes a display by applying row electrodes with a voltage based upon an orthogonal function system consisting of plural functions having mutual orthogonality and also applying each column electrode with a voltage based upon a function of the sum of products of display information and function with orthogonality is provided with a row function generating means 3 which selectively generates one of plural orthogonal function systems, a selection control means 43 which switches the orthogonal function system selected by the row function generating means, and a row electrode driving means 8 which applies the row electrodes with the voltage based upon the orthogonal function system generated from the row function generating means. Thus, a novel liquid crystal driving system which prevents deterioration in display quality due to a drop in column electrode driving voltage even when display contents are constant like a still picture is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving method and a display device thereof, and more particularly to an STN (Super) having a high speed response.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method and a display device for displaying a high contrast of a twisted nematic liquid crystal.

[0002]

2. Description of the Related Art As a conventional method for driving a liquid crystal display device having a matrix structure, time division driving by a voltage averaging method is known. This is to display one screen by driving the column electrodes according to the display information while scanning the row electrodes of the liquid crystal one by one and scanning all the row electrodes. In such a time-division driving method, it is pointed out that the display contrast is lowered when a high-speed STN liquid crystal is used.

Therefore, a method for solving this is SID92 Digest as an active addressing method.
"Active Addressing Method
for High-Contrast Video-
Rate STN Display ", pp228-2
31 is proposed. In this method, each row electrode is given a voltage according to a function having orthogonality, and each column electrode is given a voltage according to a product-sum function of all display information of the column and a function on the scanning side for display. Is the way to do it. Below, FIG.
This will be described in detail with reference to FIG.

FIG. 2 is a diagram showing the structure of a matrix type liquid crystal display unit having N rows and M columns, and display dots are formed at the intersections of the row electrodes and the column electrodes. A voltage represented by a function of f (1), f (2), ..., F (N) is applied to the N row electrodes, and g is applied to the M column electrodes.
A voltage represented by a function of (1), g (2), ..., G (M) is applied. U (i, j) represents the voltage applied to the dot at the intersection of the i-th row and the j-th column, which is f (i) and g
This is the voltage difference from (j).

FIG. 3 shows an example of an orthogonal function called a Walsh function, showing an example of division = 8. Now, as a function of the row electrodes of the liquid crystal display part of FIG.
Consider a case where T Walsh functions are used and N (T ≧ N) of T Walsh functions are selected and applied to f (i). Effective voltage value Urm of dot U (i, j) at this time
s (i, j) is as follows.

[0006]

[Equation 2]

[0007]

[Equation 3]

Here, it is assumed that f (i) and g (j) are given by the following equations (1) and (2).

[0009]

[Equation 4]

Here, I (i, j) represents dot display information at the intersection of the i-th row and the j-th column, and is assumed to have a value of -1 when the display is on and +1 when the display is off. Also, w (i, t)
Is a Walsh function and takes a value of 1 or -1, and F is a constant represented by the equation (3).

[0011]

[Equation 5]

From the above, the effective voltage value of the dot U (i, j) is given by the following equation:

[0013]

[Equation 6]

When the display is on, the value is given by the expression (5), and when the display is turned off, the value is given by the expression (6). That is, even if the function of the voltage applied to the row electrodes is the Walsh function shown in FIG.
The effective value of the voltage applied to (i, j) is represented by equations (5) and (6) depending on whether the dot is on or off.

In this case, when g (j) in the equation (2) is transformed into the form shown in the following equation,

[0016]

[Equation 7]

Here, D is I of j = 1, i = 1 to N.
It is the number of coincidences between the values of (i, j) and w (i, j). In addition,
As described above, I (i, j) is ± 1, w (i, j) is ± 1.
Takes a value of 1). At this time, the value of D is represented by the normal distribution shown by the following equation.

[0018]

[Equation 8]

From the equation (8), since D follows a normal distribution centered on N / 2, the value of the equation (7) also follows a normal distribution. The possible value of D is 0 (no match) to N (all match). Therefore, equation (7)
Therefore, the peak value of g (j) is

[0020]

[Equation 9]

[0021] Further, g (j) can take a value of N + 1 level. Here, considering this liquid crystal display device as a display device of a personal computer, at least N = 240 lines are required. Therefore, as the column voltage g (j), 241 levels are generated, and the peak voltage is expressed by the equation (9).
Therefore, a liquid crystal driver that generates about 22.65 V (provided that the liquid crystal non-selection voltage is 1 V) is required. Since it is difficult to realize such a liquid crystal driver, the liquid crystal driver has 64 levels (at this time, the peak voltage of 5.
95 volt) is also acceptable. However, in this case 1
There is a probability of overflow once every 15 frames, that is, a voltage exceeding 64 levels may be required. However, in the actual display, the occurrence of overflow is extremely rare, and it is said that there is no problem even in the above-mentioned conventional technique.

[0022]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As mentioned above, N = 2
For a personal computer display of 40, when a liquid crystal driver of 64 levels and about 5.95 volts is used, an overflow occurs at a probability of once in 115 frames. The overflow occurs with the probability of following the normal distribution according to this theory when the display contents change every moment like a moving image display.

However, when used for a display of an information processing apparatus such as a personal computer or a workstation, the displayed contents are often still images rather than moving images. Therefore, when an overflow occurs once in a still image, it will occur every frame, and since D loses the property of following the normal distribution, the effective value of the applied voltage of the corresponding column electrode decreases, and the display quality is reduced. Is considered to decrease.

Further, in the above conventional technique, the Walsh function shown in FIG. 3 is applied to the row electrodes.
Each of the Walsh functions (1) to Φ (8) has a different frequency component of the waveform, in other words, the number of times the waveform changes. Since the row electrodes and the liquid crystal driver have impedance, distortion actually occurs when the waveform changes.
This distortion of the waveform lowers the effective value of the liquid crystal applied voltage and is considered to cause display unevenness.

Further, in the above-mentioned prior art, it is shown in the above literature that the liquid crystal applied voltage waveform changes in a complicated manner.
The fast response STN liquid crystal follows this liquid crystal applied voltage waveform. That is, it is considered that a "frame response" occurs. The liquid crystal applied voltage waveform is determined by the nature of the Walsh function given as a row function and the display pattern, and it is considered that the frame response depends on these. It is considered that the change in the state of the frame response affects the brightness characteristic and the contrast characteristic of the liquid crystal and deteriorates the display quality.

The object of the present invention is also applicable to the case of displaying a still image on a personal computer or the like, and provides a new liquid crystal driving method and device which does not lower the contrast even for a STN liquid crystal of high speed response. Especially.

Furthermore, another object of the present invention is to provide a new liquid crystal drive system in which display unevenness caused by waveform distortion of a liquid crystal applied voltage is reduced.

Furthermore, it is another object of the present invention to provide a new liquid crystal driving method and device in which a frame response is stably generated and display quality is not deteriorated due to the frame response.

[0029]

In order to achieve the above object, a matrix type liquid crystal display device according to the present invention provides a row electrode with a voltage according to an orthogonal function system composed of a plurality of functions having orthogonality to each other. In the matrix type liquid crystal display device that performs display by applying a voltage according to the product sum function of the display information of the column and the function having the orthogonality to the column electrode, one of a plurality of orthogonal function systems is used. Row function generating means for selectively generating an orthogonal function system, and selection control means for switching the orthogonal function system selected by the row function generating means,
A row electrode driving means for applying a voltage according to the orthogonal function system generated by the row function generating means to the row electrode.

[0030]

In the present invention, the above-mentioned conventional problems are solved by preparing a plurality of orthogonal function systems and switching them at a predetermined timing.

In the first configuration of the present invention, when the output of the overflow detecting means indicates that an overflow is detected, the function generating means is caused to generate a function of a type different from the currently selected row function. Give instructions.

As described above, the number of matches D is I (i,
j) and w (i, t) are the same number. Therefore, when a still image is handled, the display content is constant, that is, I (i,
Since j) is constant, it is considered that D is following a normal distribution as in the above-described conventional technique by changing w (i, t) when an overflow occurs. This can be applied to still image display.

Further, in another configuration of the present invention, the orthogonal function system is switched for each frame regardless of the presence / absence of overflow to make this a row function. With this configuration, the same effect can be obtained.

In still another configuration, by applying voltage waveforms according to different kinds of orthogonal function systems to each row electrode divided into n, display unevenness caused by waveform distortion can be reduced.

[0035]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention. Reference numeral 1 is display data, which is a signal including various clocks and pixel data. Reference numeral 2 is a column signal generating means, 3 is a row function generating means, 4 is row function data, 5 is column data, and 6 is an overflow signal. The column signal generating means 2 generates the column data 5 by operating the display data 1 and the row function data 4 output from the row function generating means 3, and outputs the overflow signal 6 to the row function generating means 3.
Output to. The column signal generating means 2 and the row function generating means 3
The detailed operation of will be described later. Reference numeral 106 is a reference clock generating means, 107 is a reference clock, and 113 is a divided clock. The divided clock 113 is used by the row function generating means 3
It is the clock that is the standard for the operation of the. 7 is a column electrode driving means, 8 is a row electrode driving means, 9 is a liquid crystal panel, 10, 1
Reference numerals 1 and 12 are column electrodes, and 13 and 14 and 15 are row electrodes.
The column electrode driving means 7 fetches the column data 5 for one row and then outputs the data for one row all at once to the liquid crystal panel 9 via the column electrodes 10, 11, 12.

The liquid crystal panel has 240 lines (N = 240).
It is assumed that the column electrode driving means 7 can generate 64 levels of voltage. Data acquisition for one line is performed in one division time. The row electrode driving means 8 fetches the function values of the row for one division time from the row function data 4, and then simultaneously applies the voltages according to the function values to the row electrodes 13, 14, and 15.
To the liquid crystal panel 9 via the. The row function data 4 is also fetched within one divided time, and is synchronized with the fetch and output operations of the column electrode driving means 7.

FIG. 4 is a diagram showing the details of the column signal generating means 2. 16 is a writing means, 17 is a frame memory,
Reference numeral 18 is a reading means, and 22 is data for one column. The writing unit 16 inputs the display data 1 and sequentially writes the display data 1 in the frame memory 17. Further, the reading means 18 performs an operation of reading the display data for one column from the frame memory 17 in synchronization with the reference clock 107 and outputting it as the data 22 for one column. Reference numeral 19 is a calculation means, 20 is an overflow detection means, 21 is a voltage conversion means, 23 is the number of coincidences, and 32 is original column data. The calculation means 19 calculates the data 22 for one column and the row function data 4,
The number of matches 23 is output. Overflow detection means 20
If the value of the number of matches 23 is between the upper limit value and the lower limit value set in advance, the number of matches 23 is output as it is as the original column data 32, and the overflow signal 6 is set to logical 0. The upper limit value and the lower limit value are output as original column data, and the overflow signal 6 is set to logic 1. The voltage converting means 21 converts the original column data 32 into column data 5 for outputting to the column electrode driving means 7. Incidentally, the calculating means 19 and the overflow detecting means 20
Details of will be described later.

FIG. 5 is a diagram showing a state of display data stored in the frame memory 17. The dots U are arranged in a matrix of N rows and M columns, and the dots of i row and j column are U
It is indicated by (i, j).

FIG. 6 is a diagram showing details of the calculating means 19. 24 is an EX-OR circuit, 25 is a decoding means, and the EX-OR circuit 24 performs an exclusive OR operation on the data 22 for one column and the row function data 4. The decoding means 25 counts the number of logic 0s as a result of the exclusive OR operation, and outputs the number as the coincidence number 23.

FIG. 7 is a diagram showing details of the overflow detecting means 20. 26 is an upper limit overflow detecting means, 27 is an upper limit overflow signal, 28 is a lower limit overflow detecting means, 29 is a lower limit overflow signal, 3
Reference numeral 0 is a clipping means, and 31 is an OR circuit. The upper limit overflow detection means 26 detects the upper limit overflow signal 27 when the number of matches 23 exceeds a predetermined upper limit value.
Is set to logic 1, and when it is not exceeded, it is set to logic 0. The lower limit overflow detection means 28 detects the lower limit overflow signal 29 when the number of matches 23 falls below a predetermined lower limit value.
Is set to logic 1, and when it is exceeded, it is set to logic 0. The clipping means 30 outputs the upper limit value as the original column data 32 when the upper limit overflow signal 27 is output, and outputs the lower limit value as the original column data 32 when the lower limit overflow signal 29 is output, In other cases, the matching number 23 is output as it is as the original column data 32. The OR circuit 31 takes the logical sum of the upper limit overflow signal 27 and the lower limit overflow signal 29, and sets the overflow signal 6 to logic 1 when either one is logic 1.

FIG. 8 is a diagram showing details of the row function generating means 3. 33, 35, 37, 39 are orthogonal function generating means,
34, 36, 38, 40 are orthogonal function data output by the respective orthogonal function generating means, and the respective orthogonal function generating means 333, 35, 37, 39 are synchronized with the divided clock 113, and the orthogonal function data 34, 36. , 38, 40 are generated. In the illustrated example, four kinds of orthogonal functions are generated. 41 is a selector, 42 is selector control means, and 43 is a select signal. The selector 41 selects one of the orthogonal function data 34, 36, 38, 40 and outputs it as the row function data 4. The selector control means 42 generates the select signal 43 in the next frame according to the overflow signal 6 and determines the selecting operation of the selector 41. The orthogonal function generating means does not have to be limited to four types, and the types may be increased or decreased as necessary.

The operation of one embodiment of the above-mentioned configuration will be described below.

FIG. 40 is a diagram showing a breakdown of the display data 1 and its timing. The display data 1 is composed of a frame clock 108, a row clock 109, row data 110, a pixel clock 111, and pixel data 112. In this embodiment, there are N row clocks 109 per frame.
Occurs and M pixel clocks 11 per line clock
1 occurs.

FIG. 41 shows a timing chart for explaining the operation of the column signal generating means 2 of FIG.

The column signal generating means 2 sequentially transfers the display data 1 sent thereto to the frame memory 17, as shown in FIG. 5, U (1,1), U (1,2), U (1,3). , ……, U
(1, M), U (2,1), U (2,2), ..., U
(2, M), ..., U (N, 1), U (N, 2), ...
, U (N, M), and the writing means 16 writes. That is, the display data 1 is composed of the respective signals shown in FIG. 40, and M pieces of pixel data 112 are serially transmitted in a so-called dot-sequential manner in synchronization with the pixel clock 111. Then, the data is written in the frame memory 17. The row clock 109 is the pixel data 1
Each time 12 Ms are sent, one is sent, and a group of M pixel data 112 is defined as row data 110. The frame clock 108 is sent every time N pieces of row data 110 are sent. In this way, the sent pixel data 112 is sequentially written in the frame memory 17.

Next, the reading means 18 collectively reads the display data written in the frame memory 17 for one column in synchronization with the reference clock 107. I.e. j
For the column, U (1, j), U (2, j), ...,
N pieces of display data of U (N, j) are read out at the same time and set as one row of data 22. For each clock of the reference clock 107, N pieces of display data are read at a time in the row direction of the frame memory 17, and this is read in the column direction by M in one division time.
Repeat (M clocks) times. This one-line data 22 is
It is input to the calculation means 19. Note that one division time is a cycle in which the row function data 4 changes. Therefore, in the row function data 4, one column of data 22 is used as the reference clock 10
It does not change while reading M pieces at 7. The row function data 4 changes when M pieces are read. The timing at which the row function data 4 changes is every one clock of the divided clock 113, and the period of the divided clock 113 is the reference clock 107.
It is M times the period.

The data 22 for one column read in synchronization with the reference clock 107 and the row function data 4 generated in synchronization with the divided clock 113 are operated by the operation means 19 and the coincidence number 23 is output. It The configuration of the calculation means 19 is as shown in FIG.

On the other hand, the row function data 4 is generated by the row function generating means 3 shown in FIG. In this embodiment, the row function generating means 3 includes four types of orthogonal function generating means 3 which are different from each other.
3, 35, 37, 39 are provided. The selector 41 selects one of the orthogonal function data 34, 36, 38, 40 output from the four types of orthogonal function generators 33, 35, 37, 39, and the calculated data is used as the row function data 4. To enter. Each orthogonal function generating means 33, 35, 3
7, 39 are N orthogonal functions h corresponding to the number of rows N.
(1), h (2), ..., H (N) are generated.

For the sake of explanation, examples of orthogonal function data 34, 36, 38, 40 different from each other when N = 5 are shown in FIGS. 9, 10, 11 and 12, respectively. Figure 9
Is the orthogonal function data 3 output from the orthogonal function generating means 33.
It is 5 pieces of orthogonal function data of 4. Similarly, FIG. 10 shows the orthogonal function data 36, FIG. 11 shows the orthogonal function data 38, and FIG. 12 shows the orthogonal function data 40. Each orthogonal function data 3
4, 36, 38, and 40 are all division numbers 8 shown in FIG.
5 are arbitrarily extracted from the Walsh functions of the above to obtain orthogonal functions h (1), h (2), ..., H (5). As described above, the mutually different orthogonal functions are different orthogonal functions even if N pieces are arbitrarily taken out from the same functional system such as a Walsh function and are arranged, if they are taken out or arranged differently. Called a function. Also, the function may be arbitrarily extracted from the N functions and the sign thereof may be inverted. Further, the basic orthogonal function system is not limited to the Walsh function, and any function system satisfying orthogonality may be used. Since the Walsh function has two values of +1 and -1,
1 is defined as a logical 0 and −1 is defined as a logical 1, which will be described below.

The selector 41, which selects one of the four different orthogonal functions, operates according to an instruction from the selector control means 43. When the logic 1 of the overflow signal 6 is input, the selector control means 42 is currently in the selector 4
The selector control signal 43 is output so that the orthogonal function different from the orthogonal function data selected in 1 is selected in the next frame. Specifically, the selector control means 42 includes a counter that counts the logic 1 of the overflow signal 6, counts up each time the logic 1 of the overflow signal 6 is input, and sequentially outputs the orthogonal function data 34, 36, 38. Four
Try to switch 0. Further, without being limited to this, a random number may be generated and each orthogonal function data may be switched according to the random number value each time the logic 1 of the overflow signal 6 is input. The details of the generation of the overflow signal 6 and the effect of switching the orthogonal function data will be described later.

The row function data 4 thus generated,
The operation of the calculating means 19 which inputs the data 22 for one column and calculates the number of coincidences 23 will be described. Computing means 19
Is calculated according to equation (7). Here, the data 22 for one column of the j-th column is set to U (1, j), U (2, j),
.., U (N, j), and the row function data 4 is represented by h (1,
t), h (2, t), ..., H (N, t), and by converting the symbol of the equation (7), it can be expressed as the following equation (10).

[0053]

[Equation 10]

The calculation of D in the equation (10) is performed by counting the number of coincident logics between U (i, j) and h (i, t), and expressing this as the coincidence number D. Details of the operation of the calculating means 19 for actually obtaining the value of D will be described with reference to FIG. The one-column data 22 and the row function data 4 are input to the EX-OR circuit 24, respectively. The EX-OR circuit 24 performs an exclusive OR operation between U (i, j) and h (i, t). In the exclusive OR operation, the result becomes logical 0 when the input logics match, and the result becomes logical 1 when the input logics do not match. Therefore, the next decoding means 25 counts the number of logical 0s indicating that the logics match from the output of the EX-OR circuit 24, and outputs the number as the matching number 23. Here, the possible range of the number of coincidences 23 is between 0 and 240 because N = 240.

Next, this coincidence number 23 is input to the overflow detecting means 20 of FIG. Details of the operation of the overflow detection means 20 will be described with reference to FIG. Number of matches 2
3, the range of possible values is 0 to 240. However, since the column electrode driving means 7 can generate only a voltage of a limited level, it is checked whether or not the value of the number of coincidences 23 is equal to or more than the lower limit value and equal to or less than the upper limit value. The output of the overflow signal 6 is set to logic 1, and otherwise it is set to logic 0. The range from the lower limit value to the upper limit value is a range centering on N / 2 = 120. Since the output level of the column electrode driving means 7 is 64 levels in this embodiment, the lower limit value is 89 and the upper limit value is 152.
As described below. The upper limit overflow detection means 26 is
It is checked whether or not the value of the number of coincidences 23 exceeds the upper limit value of 152, and when it exceeds, the upper limit overflow signal 27 is set to logic 1.
Otherwise, logical 0 is set. Further, the lower limit overflow detection means 28 checks whether or not the value of the number of coincidences 23 is lower than the lower limit value 89, and when it is lower than the lower limit overflow signal 29, sets the lower limit overflow signal 29 to logic 1 and otherwise sets it to logic 0. The clipping means 30 matches the upper limit overflow signal 27, the lower limit overflow signal 29, and the number of matches 2
3 and the upper limit overflow signal 27 and the lower limit overflow signal 29 are both logic 0, the number of matches 23
Is directly output as the original column data 32. Further, when the upper limit overflow signal 27 is logic 1, the value of the original column data 32 is set to the upper limit value 152. Further, when the lower limit overflow signal 29 is logic 1, the value of the original column data 32 is set to the lower limit value 89. In this way, the value of the original column data 32 is 6 between the lower limit value 89 and the upper limit value 152.
There are 4 levels. On the other hand, a logical sum operation of the upper limit overflow signal 27 and the lower limit overflow signal 29 is performed, and this is used as the overflow signal 6. Therefore, the overflow signal 6 becomes a logic 1 when the value of the number of coincidences 23 exceeds the range of 64 levels between the lower limit value 89 and the upper limit value 152, and becomes a logic 0 when it does not exceed the range. For example, when the value of the number of coincidences 23 is 50, the value of the original column data 32 is below the lower limit value of 89, and therefore the overflow signal 6 becomes logical 1.

Next, the original column data 32 is converted into the voltage conversion means 21.
In FIG. 4, it is converted into column data 5. Voltage conversion means 2
1 is converted into g (j) by setting the original column data 32 as D according to the equation (10) to obtain column data 5. And
The column electrode driving means 7 shown in FIG. 1 fetches the column data 5 for one row (for example, column data for M columns in the section of t = 1),
After that, the data for one row is simultaneously sent to the column electrodes 10, 11, 12
To the liquid crystal panel 9 via the.

The row function generating means 3 shown in FIG. 8 is a system in which four kinds of orthogonal functions are provided in advance and one of them is selected, but other methods are also conceivable. This is shown in FIG. In FIG. 13, five Walsh functions with eight divisions are arbitrarily selected and these are output as row function data. In FIG. 13, 44 is an orthogonal function generating means, 4
5 is orthogonal function data, 46 is a switch matrix control means, 47 is a switch matrix control signal, and 48 is a switch matrix. The row function generating means 3 shown in FIG. 13 uses the switch matrix 48 to perform an operation of selecting and rearranging any 5 pieces from one type of orthogonal function data 45. The switch matrix control means 46 controls the ON / OFF of each switch. The switch matrix control means 46 controls the overflow signal 6
Switch matrix control signal 4 every time
7 is switched to output different row function data 4 one after another. The signal pattern of the switch matrix control signal 47 may be stored in the ROM in advance and used sequentially, or may be generated by a random number. Figure 1
The row function generating means 3 of 3 need only have one orthogonal function generating means 44.

As described above, in the column signal generating means 2, the value of the number of matches 23 is 89 or more as the lower limit and 152 or less as the upper limit (N
When the value exceeds the range of (64 levels centering on / 2 = 120), the overflow signal 6 is output, whereby row function data 4 different from the row function data 4 currently output by the row function generating means 3 is output. Therefore, even if the display content is constant like a still image, and even if an overflow occurs, a different row function is used next, so that the distribution of the number of coincidences D follows the normal distribution, and the column voltage drops. It is possible to avoid the deterioration of the display quality due to. The upper limit value and the lower limit value are not limited to this, but the column electrode driving means 7 may be used.
It may be set according to the number of levels that can occur.

Next, another embodiment of the present invention will be described with reference to FIGS.
Will be explained. The same parts as those in the first embodiment are designated by the same reference numerals. In FIG. 14, 49
Is a column signal generating means, 50 is a frame signal, and 51 is a row function generating means. The detailed configuration of the column signal generating means 49 is shown in FIG.

In FIG. 15, numeral 53 is a clipping means. When the value of the number of coincidences 23 exceeds a predetermined upper limit value, the clipping means 53 outputs the upper limit value as the original column data 32, and When the value falls below a predetermined lower limit value, this lower limit value is set to the original row data 3
2 is output, and within the predetermined range, the coincidence number 23 is output as it is as the original column data 32. In this embodiment, unlike the previous embodiments, the overflow signal 6 is not generated.

On the other hand, the detailed construction of the row function generating means 51 is shown in FIG. In FIG. 16, 50 is a frame signal,
Reference numeral 52 is a counter, and the frame signal 50 is a signal synchronized with the display data 1 sent from a personal computer or a workstation (not shown), and is generated every time the transfer of the display data 1 for one screen is started. It is a pulse signal. The counter 52 counts each time the frame signal 50 is input and switches the selector 41. Thereby, the orthogonal function data is sequentially switched for each frame. The row function generating means 51 of FIG. 16 is not limited to the configuration, and a switch matrix as shown in FIG. 13 may be used.

The operation of the second embodiment as described above does not detect the overflow as shown in the first embodiment, but switches the orthogonal function data for each frame regardless of the occurrence of the overflow. It was done like this. That is, the row function generating means 51 uses the frame signal 5
Each time 0 is input, a different type of orthogonal function is generated. Therefore, even if the display contents are constant like a still image and an overflow occurs, a different line function is used for the next frame, and the line functions are switched one after another regardless of the occurrence of overflow. According to the normal distribution of the number of coincidences, it is possible to avoid the deterioration of the display quality due to the decrease of the column voltage.

Further, by switching the orthogonal function, it is possible to reduce the influence of the decrease in the effective value due to the distortion of the liquid crystal applied voltage waveform. That is, when the orthogonal function shown in FIG. 9 is applied to the liquid crystal, waveform distortion actually occurs, and the waveform becomes as shown in FIG. Waveform distortion is caused when the value of the function is +1 to -1.
Occurs when changing to or from -1 to +1 but the number of changes greatly differs depending on the function. In the example of FIG. 19, Φ (1) is twice and Φ (6) is 8 per 8 divided times.
Each time there is a change, distortion occurs each time. Since the waveform distortion causes a decrease in the effective value, the effective value of the liquid crystal applied voltage decreases according to the number of times the distortion occurs. Since the display contrast decreases as the effective value decreases, the waveform as shown in FIG. 19 causes stripe-shaped uneven brightness in the horizontal direction. Therefore, as shown in the first and second embodiments, the number of occurrences of waveform distortion can be dispersed by switching the orthogonal functions one after another, which has the effect of reducing uneven brightness.

Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 17 shows a case where a Walsh function that is sequentially different for every 2 s-th power (e.g., 8) in units of m rows (m <N) is used as the voltage function applied to the N row electrodes over n times. 1 frame period T
The voltage function given to each row electrode in (T = 2 s-th power xn) is shown. FIG. 18 is an example of each Walsh function. The liquid crystal display section has N rows and M columns.
In this case, the voltage function applied to the row electrode and the voltage function applied to the column electrode are expressed by equations (11) and (16), respectively.

[0065]

[Equation 11]

Here, Fp is a constant shown by the equation (15), and Sik is a function shown in FIGS. Effective voltage value Urms of dot U (i, j) at this time
The calculation of (i, j) is as follows.

[0067]

[Equation 12]

[0068]

[Equation 13]

Therefore, the effective voltage value Urms (i, j)
Becomes equation (23). Furthermore, when the display is on, I (i,
j) becomes -1, and I (i, j) is +1 when the display is off.
Therefore, at that time, the effective voltage value is calculated by the equation (24).
(25)

From the above, it can be seen that even when the voltage function applied to the row electrode is as shown in FIG. 17, the effective voltage values of display on and display off are not different from those of the formulas (5) and (6) shown in the conventional example. . Hereinafter, such a driving method will be described as a partial orthogonal function driving method.

The specific configuration and operation of the partial orthogonal function drive system of the third embodiment as described above will be described. The parts having the same configurations as those in the first and second embodiments are designated by the same reference numerals, and detailed description thereof will be omitted. The device configuration is basically the same as that of FIG. 1, and different points will be described below. As described above, FIG. 5 shows the display data stored in the frame memory 17.

FIG. 21 is a diagram showing details of the column signal generating means 2. In FIG. 21, 54 is the frame memory 1
Partial reading means for reading m row data 57, which is m rows of one column data from 7, and 55 is a partial reading means 54.
M row data 58 and orthogonal function data 59 read from
Is a calculating means, and 56 is a voltage converting means.

FIG. 22 is a diagram showing details of the calculation means 55. In FIG. 22, 61 is an EX-OR circuit, and 62 is a decoding means. The EX-OR circuit 61 performs an exclusive OR operation on the m-row data 58 and the orthogonal function data 59, respectively. The decoding means 25 counts the number of logical 0s as a result of the exclusive OR operation and counts the number as the matching number 6
Output as 0.

FIG. 23 is a diagram showing details of the row function generating means 3. In FIG. 23, 63 is a 3-bit counter, 6
6 is a clock. The clock 66 is a clock having a frequency of 2 to the power of 2 of the m-row data 58 read from the frame memory 17. The 3-bit counter 63 counts the clock 66 and sets the value as the count value 67. 64
Is an address conversion table, and 65 is a Walsh function ROM
Is. The address conversion table 64 has a count value 67.
Read address 68 of Walsh function ROM 65 from
Is a table to be converted into. Walsh function ROM64
Stores a Walsh function in advance, and outputs the content of the address given by the read address 68 as m-row function data 59. These functions will be described later.

The operation of the third embodiment having the above configuration will be described below. The column signal generating means 2 writes the sent display data 1 by the writing means 16 into the frame memory 17
Sequentially, as shown in FIG. 5, U (1,1), U (1,
2), U (1,3), ... U (1, M), U (2,
1), U (2,2), ..., U (2, M), U (3
1), U (3, 2), ..., U (N, 1), U (N,
2), ..., U (N, M), and write. That is, since the display data 1 is serially transmitted in a so-called dot sequence, the display data 1 is sequentially written in the frame memory 17. Next, the partial reading means 54 collectively reads the display data written in the frame memory 17 for m lines,
The line data 58 is output. Here, it will be described below that the row function generating means 3 generates a row function according to the partial Walsh function shown in FIGS.

The row function generating means 3 follows each time tk
Φ (1), Φ (2), Φ (3), Φ shown in FIG.
The m-row function data 59 of (4), Φ (5), and Φ (6) are generated. That is, with respect to the first m rows, the Walsh function of FIG. 18 is generated in the time interval of the power of 2 and the value 0 is generated at other times. For the next m rows, the Walsh function of FIG. 18 is generated only in the next 2 s-th time, and the value 0 is generated at other times. Similarly, 2 s-th power Walsh functions are sequentially generated in units of m rows, and this is performed for all N rows. The m-row data 58 and the m-row function data 59 are input to the computing means 55. Computing means 55
As shown in FIG. 22, each bit of the m-row data 58 and the m-row function data 59 is operated by the EX-OR circuit, and the decoding means 62 counts the number of logic 0 as a result. The counted value is output to the voltage conversion means 56 as the coincidence number 60. The voltage converting means 56 converts the number of coincidences 60 into g (j) as D according to the equation (19) to obtain column data 5. Then, the column electrode driving means 7 shown in FIG. 1 fetches the column data 5 for one row and then outputs the data for one row all at once to the liquid crystal panel 9 via the column electrodes 10, 11, 12. On the other hand, the row function data 4 according to the partial Walsh function shown in FIG. 18 which is output from the row function generating means 8 is taken in by the row electrode driving means 8, and then the row electrodes 13 and 1 are simultaneously sent.
It is output to the liquid crystal panel 9 via 4 and 15.

In the third embodiment as described above, FIG.
If the Walsh function shown in FIG. 8 is given m times for every n rows within one frame period, the number of times the function value changes in each row is significantly different. In the example of FIG. 18, Φ (1) is 2
Φ (2) is 3 times and Φ (6) is 7 times. The voltage applied to the liquid crystal follows this, but in reality the waveform is distorted due to the impedance of the circuit and the like, as shown in FIG. Since the waveform distortion occurs when the function value changes, in the Walsh function of FIG. 18, Φ (1) and Φ (6)
Therefore, the amount of distortion varies greatly. Since the waveform distortion lowers the effective value of the liquid crystal applied voltage, the display brightness eventually becomes uneven. Therefore, in this embodiment, the display unevenness is eliminated by substantially averaging the waveform distortion of each partial Walsh function given m rows by n times. An example will be described below.

FIG. 20 shows an example in which distortion is approximately averaged based on the Walsh function shown in FIG. 18, and time 1 and time 4 of the Walsh function of FIG. 18 are exchanged. Further, each partial Walsh function given n times in FIG. 17, that is, Walsh1, Walsh2, ..., Wal
Between sh n, the method of exchange with each other is changed, or a random number is generated and exchanged by a method in accordance with this. Further, it may be changed for each frame.

Here, the method of generating the row function of FIG. 20 will be described with reference to FIG.
This will be described with reference to FIGS. In the row function generating means 3 shown in FIG. 23, as described above, the Walsh function RO
A value according to the Walsh function is stored in advance in M65, and an example thereof is shown in FIG. The line function data 59
The value "1" of the Walsh function is -1 and the value "0" of the row function data 59 is +1 of the Walsh function. The Walsh function ROM 65 outputs the row function data 59 represented by Φ (1) to Φ (6) according to the read address 68 provided. The address conversion table 64 is shown in FIG.
21 is a table for converting the Walsh function shown in FIG. 8 into a function in which the waveform distortion as shown in FIG. 20 is approximately averaged.

FIG. 25 shows an example of the contents of the address conversion table 64 for generating the function of FIG. Figure 25
[Fig. 6] is a correspondence diagram for converting a count value 67 into a read address 68. According to this, the Walsh function ROM 65 is calculated from the count value 67 of the 3-bit counter 63.
The read address 68 of is output. In this way,
The function of 0 can be generated by the address conversion table 64 shown in FIG. Also, for each partial Walsh,
Further, the waveform distortion can be approximately averaged by changing the contents of the address conversion table 64 for each frame or changing the value of the table by using a random number.

As described above, according to the present embodiment, the waveform distortion that causes a decrease in the effective value can be approximately averaged in each row, so that there is an effect of reducing uneven brightness.

Next, a fourth embodiment of the present invention will be described with reference to FIGS.
This will be described using 9. The partial orthogonal function drive method shown in the third embodiment is a case where the display device of N rows is driven by an orthogonal function that is continuous for 2 s-th power time in units of m rows as a voltage function. An example is a method in which the s-th power of 2 is further divided into d pieces and the different m-row units are sequentially driven within the s-th power of 2, as shown in FIG. 26 as a row function. That is, in terms of one m-row unit, this is a method in which the drive is dispersed d times within one frame period T. In this case, it is obvious that driving can be performed with the same voltage effective value as in the partial orthogonal function driving method of the third embodiment by calculating the corresponding m rows at each dispersed time and calculating the applied voltage to the column electrodes. Is. Such a method of driving d orthogonal functions dispersed in one frame will be referred to as a partial dispersion orthogonal function driving method.

A method of giving a row function in the fourth embodiment will be described with reference to FIGS. As a condition of the row function, it is assumed that the 2 s-th power = 8 section time is dispersed into d = 4 in units of m = 6 rows for driving. In addition,
The values of m, s, and d are not limited to these.

FIG. 27 shows six basic Walsh functions. Based on this, time 1 and 2, time 3 and 4,
FIG. 28 shows a row function which is divided into four pieces of time 5 and 6 and time 7 and 8 and which are dispersed in one frame. This is an example of the row function of the partial dispersion orthogonal function drive system. Further, since the row function is given to all N rows, the same row function is given in order for every m rows. At this time, assuming that the display is filled with white, the voltage waveform applied to each pixel of the liquid crystal was simulated, and the waveform shown in FIG. 29 was obtained. 4 in 1 frame
There is a large peak voltage, but this occurs during the selection period that gives the basic Walsh function. The fast response liquid crystal is excited periodically according to the peak voltage.
If one frame is divided into four sections and focused, there is a large difference in the non-selection period other than the selection period. Regarding the voltage applied to the liquid crystal, a voltage pulse exceeding the threshold voltage Vth of the liquid crystal continues in the section A, a DC voltage equal to or lower than Vth in the section B, and 0 V in the sections C and D.
The threshold voltage Vth of the liquid crystal is a voltage at which excitation of the liquid crystal starts. Therefore, in the section A, the voltage sufficiently exceeding Vth is continuous, so in the fast response liquid crystal, in addition to being excited in the periodic selection period, it is also excited in the section A, and the periodicity is observed. I will be taken out. As a result, the brightness and contrast characteristics are affected, resulting in display unevenness. It is not preferable in terms of display quality to give the basic Walsh function of FIG. 27 as it is to each row. Therefore, a plurality of kinds of orthogonal functions derived from the basic Walsh function are switched every time m rows are driven. Hereinafter, such an orthogonal function is called a quasi-Walsh function.

As an example of the quasi-Walsh function, a random number of m = 6 bits as shown in FIG. 30 is generated, and the value of the basic Walsh function of FIG. 27 is sign-inverted according to the random number value. At this time, the actual row function is as shown in FIG. As a result of simulating the voltage waveform applied to each pixel of the liquid crystal when a random number is generated in this way every time m rows are driven and a row function is given by this, the waveform shown in FIG. 32 is obtained. Compared to the waveform of FIG. 29, the generation of the high peak voltage during the selection period is similar, but the waveform during the non-selection period is completely different. Although the sections A, B, C, and D have different characteristics in FIG. 29, the waveform of FIG. 32 has a voltage variation on average in each section. In addition, the voltage exceeding the liquid crystal threshold voltage Vth is not concentrated in a specific section and is scattered on average in almost one frame. From this, the frame response of the high-speed response liquid crystal is controlled only by the peak voltage in the selection period, and the influence in the non-selection period is almost eliminated.

Specific configurations of the partial dispersion orthogonal function system of the fourth embodiment as described above are shown in FIGS. 1, 5, 21, and 22.
This will be described with reference to FIGS. Since the same parts as those in the previous embodiment are designated by the same reference numerals, detailed description thereof will be omitted.

FIG. 35 is a column signal generating means 2 having the row function generating means 3 of FIG. 1 and the partial reading means 54 of FIG.
It is a figure which shows the detail of. In FIG. 35, 69 is a latch means, and 70 is a frame memory read address generation means. Frame memory read address generation means 70
Outputs the frame memory read address 79 to the frame memory 17 and reads the m-row data 57 accordingly. Then, the m-row data 57 is stored in the latch means 69.
Are latched by and output to the calculating means 55 as m-row data 58. Reference numeral 71 is a reference clock generating means for generating a clock 80 which serves as a reference for the operation timing of each part. 72 is an M-adic counter, 73 is an s-th power / d-adic counter, 74 is an n-adic counter, and 75 is an ad-adic counter.
The M-adic counter 72 outputs the count value of the clock 80 as the M-adic count value 81 to the frame memory read address generation means 70, and when the M clocks 80 are counted, the M-adic carry 87 is raised to the power of 2s / d. Output to the advance counter 73. The 2 s-th power / d-adic counter 73 is M
The count value of the base carry 87 is 2 to the power of s / the base count value of 8
In addition to being output as 2, the s-th power / d-adic carry 88 of 2 when the s-th power / d is counted is output to the n-adic counter 74. The n-ary counter 74 outputs the count value of the 2 s-th power / d-ary carry 88 as the n-ary count value 83, and also outputs the n-ary carry 89 to the d-ary counter 75. The d-adic counter 75 outputs the count value of the n-adic carry 89 as a d-adic count value 84. 76 is a Walsh ROM read address generation means, 77 is a Walsh ROM, and 78 is a latch means. The Walsh ROM read address generation means 76 generates a Walsh ROM read address 85 based on the 2 s-th / d-adic count value 82, the n-adic count value 83 and the d-adic count value 84, and in accordance with this. , Walsh function value 86 is read from Walsh ROM 77. The read Walsh function value 86 is latched by the latch means 78 and output to the computing means 55 as m-row function data 59.

FIG. 38 is a diagram for explaining the details of the column electrode driving means 7 in FIG. In FIG. 38, 90 is a drive voltage of a predetermined level, 102 is a decoder, and 104 is an X drive means. The decoder 102 converts the matching number 60 into the input data 103 of the X driving means 104.

FIG. 39 is a diagram for explaining the details of the row electrode driving means 8 of FIG. In FIG. 39, 91 is an m-ary counter, 93 is an n-ary counter, 95 is a comparator, 10
1 is a drive voltage of a predetermined level. m-adic counter 91
Is a carry 92 when m clocks 80 are counted.
Is output to the n-ary counter 93. Also, the n-ary counter 9
3 outputs the count value of the carry 92 as the block number 94 to the comparator 95. Comparator 95
Compares the block number 94 with the n-ary count value 83, and if the two values are equal, the logic 1 is given, and if they are different, the logic 0 is given.
Is output as a comparison value 96. Reference numeral 97 is a PS (parallel / serial) conversion means, 99 is a decoder, and 105 is a Y drive means. When the comparison value 96 is logic 1, the PS conversion means 97 performs parallel-serial conversion of the m-row function data 59 in synchronization with the clock 80, and outputs it as serial data 98 to the decoder 99. The decoder 99 uses the comparison value 9
6 and the serial data 98 are converted into the input data 100 of the Y driving means 105.

The operation of the fourth embodiment having the above configuration will be described below. The column signal generating means 2 shown in FIG.
It is configured as 1. In FIG. 21, the display data 1 sent is sequentially written to the frame memory 17 by the writing means 16 as shown in U (1,1), as shown in FIG.
U (1,2), U (1,3), ..., U (1, M), U
(2,1), U (2,2), ..., U (2, M), ...
…, U (N, 1), U (N, 2),…, U (N, M)
And write. That is, since the display data 1 is serially sent in the so-called dot order, the display data 1 is sequentially written in the frame memory 17. On the other hand, the partial read means 54 is configured as shown in FIG. 35, and uses the frame memory read address generation means 70 to output the frame memory read address 79 to the frame memory 17 and read the m-row data 57 accordingly. The read m-row data 57 is latched by the latch means 69 and output to the arithmetic means 55 as m-row data 58.
The frame memory read address 79 is generated with an M-adic count value 81 and an n-adic count value 83, and with the M-adic count value 81, column data for m rows of the frame memory is read. Also, every time the n-ary counter value 83 is counted up, the column data for the next m rows is read out.
The frame memory read address 79 is generated.

As described above, the M-adic counter 72 counts the clock 80 generated by the reference clock generating means 71 and outputs it as the M-adic count value 81 to the frame memory read address generating means 70, and at the same time, the clock 80. When M is counted, M-ary carry 87
To the s-th power / d-adic counter 73. The 2's-th power / d-adic counter 73 counts the M-th power carry 87 and outputs it as the 2's-th power / d count value 82 to the Walsh ROM read address generation means 76, and at the same time, outputs the M-ary carry 87 to the 2's power. When the s-th power / d number is counted, the 2 s-th power / d-adic carry 88 is output to the next n-adic counter 74. The n-adic counter 74 counts the 2 s-th power / d-adic carry 88, outputs it as the n-adic count value 83 to the Walsh ROM read address generation means 76 and the frame memory read address generation means 70, and at the same time outputs the 2 s power. When n / d-adic carry 88 is counted, the n-adic carry 89 is output to the next d-adic counter 75. d-adic counter 75
Counts the n-ary carry 89 and sets it as the d-ary count value 84 to the Walsh ROM read address generating means 76.
Output to. The Walsh ROM read address generation means 76 uses the Walsh ROM based on the 2's power / d-adic count value 82, the n-adic count value 83, and the d-adic count value 84.
The read address 85 is generated.

Details of the Walsh ROM read address generating means 76 are shown in FIG. FIG. 36 shows the Walsh ROM read address 8 from the s-th power / d-adic count value 82, the n-adic count value 83, and the d-adic count value 84.
It is an example of a table to be converted to 5. Here, as a condition, N = 24 rows, m = 6, M = 10 columns, 2 s power = 8.
(S = 3), n = 4, and d = 4. This table, that is, the Walsh ROM read address generation means 76.
Accordingly, Walsh ROM read address 85 is generated. For example, the s-th power of 2 / d-adic count value 82 is “0”, the n-adic count 83 is “2”, and the d-adic count value is 8
When 4 is "1", the Walsh ROM read address 85 is uniquely determined to be "18". The Walsh ROM read address 85 thus generated is input to the Walsh ROM 77.

The details of the Walsh ROM 77 are shown in FIG.
Shown in. FIG. 37 is an example of a table for converting the Walsh ROM read address 85 into the Walsh function value 86. The Walsh ROM 77 generates the Walsh function value 86 according to this table. For example, when the Walsh ROM read address 85 is “18”, the Walsh function value 86 is Φ (1) = 1, Φ (2) = 0, Φ
(3) = 0, Φ (4) = 1, Φ (5) = 1, Φ (6) =
It is uniquely determined as 0. The Walsh function value 86 thus generated is latched by the latch means 78 and is output to the computing means 55 as orthogonal function data 59. Next, the calculation means 55 performs a calculation process on the m-row data 58 and the orthogonal function data 59, and outputs the calculation result as the coincidence number 60. The details of the calculation means 55 are as shown in FIG. The coincidence number 60 is input to the decoder 102, and the X driving means 104
Input data 103 of Input data 103
Are stored in the X driving means in accordance with the clock 80, and the column electrodes 10, 11 and 12 are simultaneously stored by the M-ary carry 87.
A voltage is applied to the liquid crystal panel 9 via the.

Next, the operation of the row electrode driving means 8 will be described with reference to FIG. In FIG. 39, an m-ary counter 91
Is a carry 92 when m clocks 80 are counted.
Is output to the next n-ary counter 93. n-ary counter 93
Takes the count value of the carry 92 as a block number 94 and uses this as one input of the comparator 95. Further, the n-ary count value 83 is used as the other input of the comparator 95. The comparator 95 compares the block number 94 and the value of the n-ary count value 83, and when both are equal, sets the logic 1 to the comparison value 9
6 is output, and if they are not equal, a logical 0 is output as a comparison value 96. When the comparison value 96 is logic 1, the PS conversion means 97 performs parallel-serial conversion of the m-row function data 59 in synchronization with the clock 80 and outputs it as serial data 98 to the decoder 99. The decoder 99 uses the comparison value 96
And the serial data 98 is converted into the input data 100 of the Y driving means 105. Clock 80 for input data 100
Accordingly, N pieces are stored in the Y driving means 105, and a voltage is applied to the liquid crystal panel 9 via the row electrodes 13, 14, 15 all at once by the M-ary carry 87.

In the table shown in FIG. 37, that is, in the Walsh ROM 77, when the Walsh ROM read address 85 is 0 to 7, the orthogonal function data 59 is shown in FIG.
When the Walsh ROM read address 85 is 8 to 15, the orthogonal function data 59 is the quasi-Walsh function shown in FIG.
When the read address 85 is 16 to 23, the orthogonal function data 59 is further Φ from the quasi-Walsh function shown in FIG.
(1) to Φ (6) are replaced with Φ (6) to Φ (1), and the Walsh ROM read address 85 is 24
In the case of .about.31, the orthogonal function data 59 is obtained by further exchanging the time 6 and the time 7 from the quasi Walsh function shown in FIG. This is an example of the Walsh ROM 77, and is not limited to this. Inversion of any value of Φ (1) to Φ (6), replacement of Φ (1) to Φ (6), and arbitrary replacement. You can freely combine the times selected in. As a result, the voltage applied to the liquid crystal is appropriately dispersed, and the high voltage is not concentrated in a specific period. Furthermore, the quasi-Walsh function may be switched for each frame as in the first and second embodiments.

As described above, according to this embodiment, the voltage waveform applied to each pixel of the liquid crystal by the scan of the Walsh function is a waveform in which the voltage is dispersed evenly in the non-selection period, and only the peak voltage in the selection period is obtained. Since the frame response of the high-speed response liquid crystal is controlled, stable luminance characteristics and contrast characteristics can be obtained.

[0097]

As described above, according to the present invention, a new liquid crystal drive which can be applied to the display of a still image on a personal computer or the like and which does not deteriorate the display quality even for STN liquid crystal having a high speed response. The method can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a liquid crystal display device of the present invention.

FIG. 2 is an explanatory diagram of a liquid crystal display unit having a matrix structure of N rows and M columns.

FIG. 3 is an orthogonal function called a Walsh function,
Explanatory drawing showing an example of division = 8

FIG. 4 is a block diagram showing details of the column signal generating means 2.

FIG. 5 is an explanatory diagram showing display data stored in a frame memory 17.

FIG. 6 is a circuit block diagram showing details of a calculation means 19.

FIG. 7 is a circuit block diagram showing details of overflow detection means 20.

FIG. 8 is a block diagram showing details of the row function generating means 3.

FIG. 9 is an explanatory diagram showing orthogonal function data 34.

FIG. 10 is an explanatory diagram showing orthogonal function data 36.

FIG. 11 is an explanatory diagram showing orthogonal function data 38.

FIG. 12 is an explanatory diagram showing orthogonal function data 40.

FIG. 13 is a block diagram of another configuration example of the row function generating means 3 for generating different row function data using a switch matrix.

FIG. 14 is a block diagram of a second embodiment of the liquid crystal display device of the present invention.

FIG. 15 is a block diagram showing details of column signal generating means 49.

FIG. 16 is a block diagram showing details of the row function generating means 51.

FIG. 17 is a function of voltage applied to N row electrodes,
Explanatory drawing which shows the voltage function of 1 frame period T in the case where a Walsh function of 2 s-th power is given sequentially in order of m rows by n times.

FIG. 18 is an explanatory diagram of an example of each Walsh function.

FIG. 19 is an explanatory diagram showing waveform distortion.

FIG. 20 is an explanatory diagram in which distortion is approximately averaged.

FIG. 21 is a block diagram showing details of the column signal generating means 2.

FIG. 22 is a circuit block diagram showing details of the calculating means 55.

FIG. 23 is a block diagram showing details of the row function generating means 3.

FIG. 24 is an explanatory diagram showing an example of the Walsh ROM 65.

FIG. 25 is an explanatory diagram showing an example of an address conversion table 64.

FIG. 26 is an explanatory diagram showing a method of distributing 2 s-th power times to d pieces and d pieces to be driven in one frame T.

FIG. 27 is an explanatory diagram of six basic Walsh functions.

FIG. 28 is an explanatory diagram of a row function in which the basic Walsh function is divided into four and dispersed in one frame.

FIG. 29 is an explanatory diagram in which a voltage waveform applied to liquid crystal is simulated.

FIG. 30 is a waveform chart of an example of the quasi-Walsh function.

FIG. 31 is an explanatory diagram showing a row function using a quasi-Walsh function.

FIG. 32 is a waveform diagram simulating a voltage waveform applied to the liquid crystal.

FIG. 33 is an explanatory diagram showing another example of the quasi-Walsh function.

FIG. 34 is an explanatory diagram showing a row function using another example of the quasi-Walsh function.

FIG. 35 is a block diagram showing details of the column signal generating means 2, the row function generating means 3, and the partial reading means 54.

FIG. 36 is a Walsh ROM based on the 2 s-th power / d-adic count value 82, the n-adic count value 83, and the d-adic count value 84.
Explanatory diagram showing an example of a table for converting to a read address 85

FIG. 37 is an explanatory diagram illustrating details of the Walsh ROM 77.

FIG. 38 is a block diagram illustrating details of column electrode driving means 7.

FIG. 39 is a block diagram illustrating details of the row electrode driving means 8.

FIG. 40 is a timing chart for explaining the image data 1.

41 is a timing chart for explaining the operation of the embodiment of FIG.

[Explanation of symbols]

1 ... Display data, 2 ... Column signal generating means, 3 ... Row function generating means, 4 ... Row function data, 5 ... Column data, 6 ... Overflow signal, 7 ... Column electrode driving means, 8 ... Row electrode driving means, 9 ... liquid crystal panel, 10 ... column electrode, 11 ... column electrode, 1
2 ... Column electrode, 13 ... Row electrode, 14 ... Row electrode, 15 ... Row electrode, 16 ... Writing means, 17 ... Frame memory, 18
... Read-out means, 19 ... Arithmetic means, 20 ... Overflow detection means, 21 ... Voltage conversion means, 22 ... One column data, 23 ... Matching number, 24 ... EX-OR circuit, 25 ... Decoding means, 26 ... Upper limit overflow detection Means, 27 ...
Upper limit overflow detection signal, 28 ... Lower limit overflow detection means, 29 ... Lower limit overflow signal, 30 ... Clipping means, 31 ... OR circuit, 32 ... Original column data,
33 ... Orthogonal function generating means, 34 ... Orthogonal function data, 35
... orthogonal function generating means, 36 ... orthogonal function data, 37 ... orthogonal function generating means, 38 ... orthogonal function data, 39 ... orthogonal function generating means, 40 ... orthogonal function data, 41 ... selector,
42 ... Select control means 43 ... Select signal 44 ...
Orthogonal function generating means, 45 ... Orthogonal function data, 46 ... Switch matrix control means, 47 ... Switch matrix control signal, 48 ... Switch matrix, 49 ... Column signal generating means, 50 ... Frame signal, 51 ... Row function generating means, 52 ... counter, 53 ... clipping means, 54 ...
Partial reading means, 55 ... Arithmetic means, 56 ... Voltage conversion means, 61 ... EX-OR circuit, 62 ... Code means, 63
... 3-bit counter, 64 ... Address conversion means, 65 ...
Walsh function ROM, 69 ... Latch means, 70 ... Frame memory read address generation means, 71 ... Reference clock generation means, 72 ... M-ary counter, 73 ... 2s power /
d-adic counter, 74 ... n-adic counter, 75 ... d-adic counter, 76 ... Walsh ROM read address generating means, 77 ... Walsh ROM, 78 ... latch means, 91
... m-ary counter, 93 ... n-ary counter, 95 ... comparator, 97 ... parallel-serial conversion means, 99 ... decoder, 102 ... decoder, 104 ... X driving means, 105 ...
Y drive means.

Front Page Continuation (72) Inventor ▲ Shin ▼ Hiroyuki Nono 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Ltd. Hitachi, Ltd. Microelectronics Device Development Laboratory

Claims (12)

[Claims] 1. A voltage according to an orthogonal function system composed of a plurality of functions having orthogonality to each other is applied to a row electrode, and each column electrode has a sum of products of display information of the column and the function having the orthogonality. In a matrix-type liquid crystal display device that performs display by applying a voltage according to the function of, a row function generating means for selectively generating one orthogonal function system of a plurality of orthogonal function systems, and a row function generating means of the row function generating means. A matrix type comprising: selection control means for switching the orthogonal function system to be selected; and row electrode driving means for applying a voltage according to the orthogonal function system generated by the row function generating means to the row electrode. Liquid crystal display device. 2. The row function generating means comprises a plurality of orthogonal function system generating means for generating a plurality of orthogonal function systems, and a selecting means for selecting one of the plurality of orthogonal function system generating means. The matrix type liquid crystal display device according to claim 1, wherein 3. The row function generating means is different from the orthogonal function system generating means for generating one orthogonal function system and the plurality of different function data output methods of the orthogonal function system generating means. The matrix type liquid crystal display device according to claim 1, wherein the matrix type liquid crystal display device comprises a switch matrix for generating an orthogonal function system. 4. The voltage obtained according to the product sum function of the display information of the column and the function having the orthogonality is the maximum liquid crystal applied voltage level used by the column electrode driving means for driving the column electrode. Overflow detection means for generating an overflow signal when exceeding, and the selection control means according to the overflow signal,
4. The matrix type liquid crystal display device according to claim 1, wherein the selected orthogonal function system is switched. 5. The matrix type liquid crystal display device according to claim 1, wherein the selection control means switches the selection of the orthogonal function system by the selection means at a predetermined constant period. 6. The matrix type liquid crystal display device according to claim 5, wherein selection of the orthogonal function system is switched according to a frame synchronization signal. 7. The orthogonal function system is defined as w (i, t) (where:
i = 1 to N, N = number of rows, t = time), the display data given to the column electrode driving means is as follows. 2. The matrix type liquid crystal display device according to claim 1, further comprising data conversion means for converting the input display data so as to obtain the voltage indicated by. 8. A matrix type liquid crystal display device according to claim 7, wherein at least the column signal generating means is a one-chip display controller. 9. The selection control means controls when the output of the data conversion means exceeds a predetermined range to select a different one from the orthogonal function system currently selected. The matrix type liquid crystal display device according to claim 7. 10. A voltage difference between voltage waveforms applied to the row electrode and the column electrode, which are formed by N row electrodes and M column electrodes, and the dots at the intersections of the row electrodes and the column electrodes are applied to the row electrodes and the column electrodes. In a driving method of a matrix type liquid crystal display device that displays on and off with an effective value of, there are a plurality of orthogonal function systems having values of +1 and -1, and one of them is selected. Then, a voltage waveform according to the above is applied to the row electrodes, and a method for driving a matrix type liquid crystal display device. 11. A row electrode of N rows and a column electrode of M columns, and a dot at an intersection of the row electrode and the column electrode is defined by voltage waveforms applied to the row electrode and the column electrode. In a driving method of a matrix type display device for turning on / off a display based on an effective value of a voltage difference, n s (n is a positive integer) each having 2 s-th power (s is a positive integer) section is one cycle. Orthogonal function systems with different integers are prepared, N row electrodes are divided into m rows (m <N) each by n, and one frame period T is divided by (2 s power) × n. In the (i = 1 to n) -th 2 s-th section, a voltage corresponding to a value of +1 or −1 is applied to the i-th row electrode of the m-th row according to the i-th orthogonal function system, and A method for driving a matrix type display device, characterized in that a voltage corresponding to a value of 0 is applied to the row electrodes of. 12. The 2s-th section is further divided into d sections (d is a positive integer) to obtain the i-th orthogonal function system to be applied to the i-th row electrode of the m-th row. Followed voltage,
7. The method of driving a matrix type display device according to claim 6, wherein the application is performed in a distributed manner for d periods over one frame.