JPH06138189A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06138189A
JPH06138189A JP4292837A JP29283792A JPH06138189A JP H06138189 A JPH06138189 A JP H06138189A JP 4292837 A JP4292837 A JP 4292837A JP 29283792 A JP29283792 A JP 29283792A JP H06138189 A JPH06138189 A JP H06138189A
Authority
JP
Japan
Prior art keywords
internal circuit
teg
circuit
input
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4292837A
Other languages
Japanese (ja)
Other versions
JP3156397B2 (en
Inventor
Moyuru Fujii
もゆる 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29283792A priority Critical patent/JP3156397B2/en
Publication of JPH06138189A publication Critical patent/JPH06138189A/en
Application granted granted Critical
Publication of JP3156397B2 publication Critical patent/JP3156397B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To reduce the number of terminals of a semiconductor device by using the same terminal for an internal circuit and a TEG part. CONSTITUTION:A connection selection circuit 6 including Field Effect Transistors Q1-Q8 and an inverter A and a selection signal input terminal 7 for inputting a control signal are provided for an internal circuit 1 and a TEG part 2, a terminal 4 for input for inputting a signal for operation of the internal circuit and a terminal 5 for output for taking out the operation result are commonly used as a signal input terminal for measuring the TEG part 2 and a terminal for output for taking out measurement result, and then the connection of the internal circuit and the TEG part to the terminals 4 and 5 for input and output is selected depending on whether the selection signal is either H or L level. It is not necessary to use separate terminal for each of the internal circuit and the TEG part as compared with before, thus eliminating the terminals for one input and output for the internal circuit and the TEG part and hence reducing the total number of terminals.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置、特に装置本
来の機能を果たすための内部回路とは別に、電気特性測
定のためだけに設けられているTEG(test el
ementgroup)部を有する半導体装置に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and in particular to a TEG (test cell) provided only for measuring electrical characteristics, apart from an internal circuit for performing the original function of the device.
The present invention relates to a semiconductor device having an element group).

【0002】[0002]

【従来の技術】上述のTEG部を有する従来の半導体装
置は、図3の平面図に示すように、論理演算を行う演算
回路や情報の記憶を行う記憶装置などが設けられている
内部回路1と、外部からの信号を内部回路に入力するた
めの入力端子14、14と、出力端子15、15と、半
導体装置を構成するトランジスタなどの素子の電気特性
を測定するために特に設けられているTEG部2と、T
EG部2への測定用信号入力端子16、16と、出力用
端子17、17とが半導体基板上に形成されて成るもの
である。そして、この半導体装置の内部回路1を動作さ
せるためには、適当な信号発生装置を用いて入力端子1
4から動作用の信号を入力し、内部回路における演算結
果や記憶情報を出力端子15から取り出していた。ま
た、TEG部2の電気特性測定を行う場合は、入力端子
16に測定用信号を入力し、TEG部における素子の測
定結果を出力端子17から取り出していた。
2. Description of the Related Art As shown in the plan view of FIG. 3, a conventional semiconductor device having the above-mentioned TEG portion has an internal circuit 1 provided with an arithmetic circuit for performing a logical operation and a memory device for storing information. And input terminals 14 and 14 for inputting a signal from the outside to the internal circuit, output terminals 15 and 15, and especially provided for measuring electrical characteristics of elements such as transistors included in a semiconductor device. TEG part 2 and T
The measurement signal input terminals 16 and 16 to the EG part 2 and the output terminals 17 and 17 are formed on a semiconductor substrate. In order to operate the internal circuit 1 of this semiconductor device, an appropriate signal generator is used to input the input terminal 1
A signal for operation is input from No. 4, and the calculation result and stored information in the internal circuit are taken out from the output terminal 15. Further, when measuring the electrical characteristics of the TEG portion 2, a measurement signal was input to the input terminal 16 and the measurement result of the element in the TEG portion was taken out from the output terminal 17.

【0003】[0003]

【発明が解決しようとする課題】上記の内部回路の動作
およびTEG部における電気特性測定においては、それ
ぞれ異なる入力用端子および出力用端子を用いていた。
そのため、装置の総端子数が増大し、基板面積が大きく
なってしまうという問題があった。
In the operation of the internal circuit and the measurement of the electrical characteristics in the TEG section, different input terminals and output terminals are used.
Therefore, there is a problem that the total number of terminals of the device is increased and the substrate area is increased.

【0004】[0004]

【課題を解決するための手段】上記課題に対して本発明
では、1枚の半導体基板上に形成されている、内部回路
とTEG部に対して共通に入力端子と出力端子を設け、
また、この端子の内部回路とTEG部に対する接続の接
続選択回路を設け、内部回路動作の場合には内部回路
に、TEG部の測定の場合にはTEG部にのみ前記入力
端子及び出力端子を接続するようにしている。
In order to solve the above problems, according to the present invention, an input terminal and an output terminal are provided commonly to an internal circuit and a TEG portion formed on one semiconductor substrate,
Further, a connection selection circuit for connecting the internal circuit of this terminal to the TEG portion is provided, and the input terminal and the output terminal are connected only to the internal circuit when operating the internal circuit and only to the TEG portion when measuring the TEG portion. I am trying to do it.

【0005】[0005]

【実施例】つぎに図面を参照して本発明を説明する。図
1は本発明の一実施例の平面図である。図において、1
はこの半導体装置本来の機能を果たすための演算回路や
情報記憶装置などを含む内部回路であり、2はこの半導
体装置を構成するトランジスタなどの素子の電気特性を
測定するために特に設けてあるTEG部である。また、
内部回路1と、装置基板の周辺に設けてある入力用端子
4、4および出力用端子5、5との間に、ドレイン、ソ
ースが接続された電界効果トランジスタQ1〜Q4と、
同じく入力用端子4、4および出力用端子5、5と、T
EG部2との間にドレイン、ソースが接続された電界効
果トランジスタQ5〜Q8と、トランジスタQ1〜Q4
の共通ゲートが入力側でトランジスタQ5〜Q8の共通
ゲートを出力側に接続されたインバータAとにより、内
部回路1とTEG部2を入力用および出力用の端子群に
選択接続するための接続選択回路6が構成されている。
そして、接続選択回路6のトランジスタQ1、Q4の共
通ゲートからは接続選択回路を制御するための選択信号
入力端子7が引き出されている。
The present invention will be described below with reference to the drawings. FIG. 1 is a plan view of an embodiment of the present invention. In the figure, 1
Is an internal circuit including an arithmetic circuit and an information storage device for performing the original function of this semiconductor device, and 2 is a TEG provided especially for measuring the electrical characteristics of elements such as transistors constituting this semiconductor device. It is a department. Also,
Field-effect transistors Q1 to Q4 having drains and sources connected between the internal circuit 1 and the input terminals 4 and 4 and the output terminals 5 and 5 provided on the periphery of the device substrate,
Similarly, input terminals 4 and 4 and output terminals 5 and 5, and T
Field effect transistors Q5 to Q8 whose drains and sources are connected to the EG section 2 and transistors Q1 to Q4
Connection selection for selectively connecting the internal circuit 1 and the TEG unit 2 to the input and output terminal groups by the inverter A in which the common gate of the transistors Q5 to Q8 is connected to the output side. The circuit 6 is configured.
A selection signal input terminal 7 for controlling the connection selection circuit is drawn from the common gate of the transistors Q1 and Q4 of the connection selection circuit 6.

【0006】つぎに本例の動作について説明する。まず
内部回路1が動作の場合は、選択信号入力端子7はHレ
ベルの信号が入力されていて、トランジスタQ1〜Q4
はオン、インバータAにより共通ゲートがLレベルとな
っているトランジスタQ5〜Q8はオフとなって、内部
回路1が選択される。適当な信号源に接続された入力用
端子4、4への入力に対応じた、内部回路の演算回路の
演算結果は出力用端子5、5に接続されているディスプ
レイ装置などに表示される。
Next, the operation of this example will be described. First, when the internal circuit 1 is in operation, an H level signal is input to the selection signal input terminal 7, and the transistors Q1 to Q4
Is turned on, and the transistors Q5 to Q8 whose common gate is at the L level by the inverter A are turned off and the internal circuit 1 is selected. The calculation result of the calculation circuit of the internal circuit corresponding to the input to the input terminals 4 and 4 connected to an appropriate signal source is displayed on the display device or the like connected to the output terminals 5 and 5.

【0007】選択信号入力端子7がLレベルのときはT
EG部2が選択されて、入力用端子4に入力された測定
用信号によりTEG部素子の電気特性測定が行われる。
When the selection signal input terminal 7 is at L level, T
The EG section 2 is selected, and the electrical characteristics of the TEG section element are measured by the measurement signal input to the input terminal 4.

【0008】図2は本発明の実施例2の平面図である。
図において、本例を図1の実施例1と比べると、本例で
は図1に対しTEG部が2、3の2群になったことと、
それに対応して接続選択用の電界効果トランジスタQ9
〜Q12が新しく増えたこと、また、選択対象が内部回
路および二つのTEG部の三つになり、その中の一つを
選択するために、2個のNORゲートG1、G2とイン
バータA1とからなる選択信号回路8が設けられ、さら
に、選択信号回路8へ制御用信号を入力するための選択
信号入力端子9が増えたことである。
FIG. 2 is a plan view of the second embodiment of the present invention.
In the figure, comparing this example with the example 1 of FIG. 1, in this example, there are two groups of TEG parts 2 and 3 with respect to FIG.
Correspondingly, the field effect transistor Q9 for connection selection
~ Q12 is newly added, and the selection target is three of the internal circuit and the two TEG units, and in order to select one of them, two NOR gates G1 and G2 and the inverter A1 are selected. The selection signal circuit 8 is provided, and the selection signal input terminal 9 for inputting the control signal to the selection signal circuit 8 is increased.

【0009】この実施例では選択信号入力端子7と9が
共にHレベルのときは内部回路1が選択され、選択信号
入力端子7と9が共にLレベルのときはTEG部2が選
択され、選択信号入力端子7がLレベル、選択信号入力
端子9がHレベルならばTEG部3が選択される。
In this embodiment, when the selection signal input terminals 7 and 9 are both at the H level, the internal circuit 1 is selected, and when the selection signal input terminals 7 and 9 are both at the L level, the TEG section 2 is selected and selected. When the signal input terminal 7 is at L level and the selection signal input terminal 9 is at H level, the TEG unit 3 is selected.

【0010】[0010]

【発明の効果】以上説明したように本発明では、内部回
路とTEG部に対して接続選択回路を用いて何れか一方
を選択して入力用および出力用端子に接続していること
により、内部回路とTEG部に対して同一端子を使用す
るので、従来別々の端子を設けていたときに比べ端子数
を減らすことができ、当然基板面積も縮小でき、装置小
形化が図られるという効果が得られる。
As described above, according to the present invention, the internal circuit and the TEG section are connected to the input and output terminals by selecting either one by using the connection selection circuit. Since the same terminal is used for the circuit and the TEG section, the number of terminals can be reduced as compared with the case where separate terminals are conventionally provided, and naturally the board area can be reduced and the device can be downsized. To be

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例1の平面図である。FIG. 1 is a plan view of a first embodiment of the present invention.

【図2】本発明の実施例2の平面図である。FIG. 2 is a plan view of a second embodiment of the present invention.

【図3】従来の半導体装置の平面図である。FIG. 3 is a plan view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 内部回路 2,3 TEG部 4 入力用端子 5 出力用端子 6 接続選択回路 7,9 選択信号入力端子 8 選択信号回路 1 Internal circuit 2,3 TEG section 4 Input terminal 5 Output terminal 6 Connection selection circuit 7,9 Selection signal input terminal 8 Selection signal circuit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 装置本来の機能を果たすための演算回路
や情報記憶装置などを含む内部回路と、電気特性測定専
用の素子群からなる1群または複数群のTEG部と、前
記内部回路やTEG部に対する入力用および出力用端子
と、これら入力用および出力用端子を前記内部回路およ
びTEG部に共用するために前記の入力用端子および出
力用端子を前記内部回路およびTEG部のそれぞれ対し
て独立に接続する接続選択回路と、この接続選択回路に
対する制御信号を入力するための選択信号入力端子とを
有することを特徴とする半導体装置。
1. An internal circuit including an arithmetic circuit and an information storage device for performing the original function of the apparatus, a group of TEGs of one or a plurality of groups consisting of an element group dedicated to electrical characteristic measurement, the internal circuit and the TEG. Input and output terminals to the internal circuit and the TEG section, and the input and output terminals for the internal circuit and the TEG section are independent of each other in order to share the input and output terminals with the internal circuit and the TEG section. A semiconductor device comprising: a connection selection circuit connected to the connection selection circuit; and a selection signal input terminal for inputting a control signal to the connection selection circuit.
【請求項2】 上記接続選択回路は、前記入力用および
出力用端子と、内部回路およびTEG部のそれぞれとの
間に設けられた電界効果トランジスタと、上記選択信号
入力端子に入力された選択信号により前記トランジスタ
のゲートに前記内部回路および1群または複数群のTE
G部それぞれ毎のトランジスタだけをオンにする選択用
信号を加えるための選択信号回路とから形成されている
ことを特徴とする請求項1の半導体装置。
2. The connection selection circuit includes a field effect transistor provided between the input and output terminals, an internal circuit and a TEG section, and a selection signal input to the selection signal input terminal. To the gate of the transistor by the internal circuit and one or more TE groups.
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed of a selection signal circuit for applying a selection signal for turning on only the transistor of each G section.
JP29283792A 1992-10-30 1992-10-30 Semiconductor device Expired - Fee Related JP3156397B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29283792A JP3156397B2 (en) 1992-10-30 1992-10-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29283792A JP3156397B2 (en) 1992-10-30 1992-10-30 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH06138189A true JPH06138189A (en) 1994-05-20
JP3156397B2 JP3156397B2 (en) 2001-04-16

Family

ID=17787005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29283792A Expired - Fee Related JP3156397B2 (en) 1992-10-30 1992-10-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3156397B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6489799B1 (en) 1999-04-30 2002-12-03 Nec Corporation Integrated circuit device having process parameter measuring circuit
JP2007147617A (en) * 2005-11-28 2007-06-14 Samsung Electronics Co Ltd Film type semiconductor package provided with test pad having shared output channel, test method for film type semiconductor package, test device and semiconductor device provided with pattern shared with test channel, and testing method in semiconductor device
US7751998B2 (en) 2006-09-20 2010-07-06 Elpida Memory, Inc. Semiconductor device, method for measuring characteristics of element to be measured, and characteristic management system of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6489799B1 (en) 1999-04-30 2002-12-03 Nec Corporation Integrated circuit device having process parameter measuring circuit
JP2007147617A (en) * 2005-11-28 2007-06-14 Samsung Electronics Co Ltd Film type semiconductor package provided with test pad having shared output channel, test method for film type semiconductor package, test device and semiconductor device provided with pattern shared with test channel, and testing method in semiconductor device
US7751998B2 (en) 2006-09-20 2010-07-06 Elpida Memory, Inc. Semiconductor device, method for measuring characteristics of element to be measured, and characteristic management system of semiconductor device

Also Published As

Publication number Publication date
JP3156397B2 (en) 2001-04-16

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