JPH06135057A - Printing apparatus - Google Patents

Abstract

PURPOSE:To prevent the degration of images at the reduced time by providing means for changing the printing density in the transferring direction of papers and a detecting means for detecting whether the data of the same line is printed a plurality of number of times or once in accordance with the reduction rate. CONSTITUTION:A central processing unit CPU1 controls the whole of the printing apparatus, and a ROM2 stores various kinds of control programs and data to be executed by the CPU1. A RAM3 is a working area to temporarily preserve the data for the CPU1 to perform various kinds of treatments. An operating part 4 is provided with keys and a display to allow a user to make various settings, particularly setting of the magnification for a reducing process. A video signal generating part 5 having an image memory, a P/S converter and the like generates video signals to be printed at a printing part 6. The video signal generating part 5 reduces images in accordance with the reduction rate set at the operating part 4 and generates video signals of the reduced images. The printing part 6 carries out printing to a recording medium by the video signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printing apparatus for printing an image according to image information from a host computer or the like.

[0002]

2. Description of the Related Art Conventionally, in a printer that develops character information sent from a host computer or the like as a bit image in an internal memory, and then reads and outputs the bit image, if there is reduced printing, it is stored in the memory. The reduced bit image is expanded and output again.

[0003]

However, in the above-mentioned conventional example, there is a disadvantage in that the original bit image and the memory for storing the reduced bit image are required in the memory, resulting in high cost. In addition, since processing such as simple thinning is performed at the time of reduction, there is a drawback that image deterioration occurs.

[0004]

According to the present invention, by increasing the print density in the paper conveying direction, the same line is normally printed twice at the time of reduction, but depending on the reduction ratio,
By printing the same line only once, reduction is performed and image deterioration due to conventional thinning is prevented.

[0005]

1 is a block diagram showing a schematic configuration of a printing apparatus according to this embodiment. In the figure, reference numeral 1 denotes a central processing unit (CPU), which controls the entire printing apparatus. A ROM 2 stores various control programs executed by the CPU 1 and data. Reference numeral 3 denotes a RAM, which is a work area for the CPU 1 to temporarily store data in order to execute various processes. An operation unit 4 includes keys and a display for the user to make various settings. In particular, the magnification setting for reduction processing is also performed by the operation unit 4
Using. A video signal generation unit 5 includes an image memory, a P / S converter, and the like, and generates a video signal for executing printing in the printing unit 6. A printing unit 6 executes printing on a recording medium such as recording paper. Reference numeral 7 denotes a system bus, which includes an address bus and a data bus, connects the above-described components, and exchanges data with each other.

In the above structure, the video generation unit 5 reduces the image according to the reduction ratio set by the operation unit 4, and generates the video signal of the reduced image. The printing unit 6 prints on the recording medium by the video signal.

Next, the sub-scanning direction reduction unit in the video signal generation unit 5 will be described with reference to FIG. Reference numeral 101 is a reduction ratio register for setting the reduction ratio by the data bus 103 of the CPU, and its output 105 is an input to the adder 102. The addition result 104 of the adder 102 is latched in the register 103 by the latch clock 111. The output 106 of the register 103 becomes the input of the adder 102, and the output 106 is the clear signal 1 according to the instruction of the CPU.
It is cleared to the value “0” by 07. The adder 102 adds the value set in the reduction register 101 and the value latched in the register 103, and the carry signal 116 is at level "H" when there is a carry and at level "L" when there is no carry. To Reference numeral 109 denotes a main scanning synchronization signal, which serves as a latch clock of the register B119, an input of the AND circuit 118, and an input of the NAND circuit 112. The flip-flop 114 divides the clock of the input signal 113 by ½ and is cleared when the carry signal 116 is at level “L”, and the output 128 is at level “L”. Reference numeral 110 denotes a scan end signal generated when video conversion of parallel data for one line into serial data is completed, and is an input clock of the flip-flop 115 and the inverter circuit 12.
7 and NAND circuit 117. The flip-flop 115 divides the input clock 110 by half,
It is cleared when the output 130 of the flip-flop 102 is at level "L". The output 129 becomes the input of the AND circuit 118. The output 125 of the NAND circuit 117 is an address load pulse for storing the value of the input 122 in the address counter 123, and the output of the AND circuit 118 is the latch clock of the register 103. Address counter 1
The output 124 of 23 becomes the address of the image memory and is latched in the register 119 by the main scanning synchronizing signal.
Reference numeral 126 is a data transfer end signal that is generated when data is read from the image memory and the data is transferred to the video signal generation unit at the end of transfer. When the address counter 123 receives the data transfer end signal 126, it increments. Reference numeral 121 is a selector for selecting the data bus 108 and the register 119 of the CPU 1, and when the CPU 1 sets an initial address in the address counter 123 via the data bus 108, the selector 12
In 1, the data bus 108 of the CPU 1 is selected and the value of the data bus 108 is output as the output 122. In the flip-flop 132, the carry signal 116 of the adder 102 is sampled at the rising edge of the signal 131 which is inverted by the inverter of the scan end signal 110, and its output 130 is the clear input of the flip-flop 115, N
It becomes an input to the AND circuit 112.

Next, the operation will be described with reference to FIGS.

FIG. 3 is a timing chart for explaining this embodiment, FIG. 4 shows an example of setting a value in the reduction ratio register, and FIG. 5 shows each timing on the paper surface.

The CPU 1 first outputs a clear signal 107 to clear the contents of the register 103 to "0".
Next, the CPU 1 transfers the data bus 10 to the reduction ratio register 101.
Set the reduction rate through 8. The format of the data set here is fixed-point, and is shown in FIG. Here, when the reduction ratio is 0.75, FIG. 4B is set. The CPU 1 also sets the head address N of the image memory in the address counter 123. The CPU 1 sets the print density of the printing unit 6 to be double the normal print density in the paper conveyance direction.
That is, a print density that is double the normal print density is set in the sub-scanning direction. In the adder 102, the value of the register 103 and the value of the reduction rate register 101 are added, and here the value is 0.75.
It is + 0 = 0.75 (step S0). When a print start command is issued to the printing unit 6, the main scanning synchronization signal 109 is sent from the printing unit 6 (step S
1). The initial levels of the outputs 130, 129 and 128 of the flip-flops 132, 115 and 114 are “H”,
“H” and “L”. Therefore, the output 111 of the AND circuit 118 becomes the level “H”, and the value of the output 104 of the adder 102, here 0.75, is latched in the register 103. In addition, in the adder 102, the value of the reduction register 101 is 0.75 and the value of the register 103 is 0.75.
Is added to 0.75 + 0.75 = 1.5, and the carry signal 127 becomes the level "H". At this time, the value "N" of the output of the address counter 123 is latched in the register 119. At the falling edge of the main scanning synchronization signal 109, the output 128 of the flip-flop 114 is inverted and becomes the level "H" (step S2). The data transfer end signal 126 is input, and the address counter 123 is incremented. Here, it is assumed that one line is composed of m words. When the one-line transfer is completed, the scan end signal 110 is generated (step S3). At this time, since the output of the flip-flop 114 is at the level “H”, the output address counter load signal of the NAND circuit 117 becomes the level “L” and the value “N” latched in the register 119 is reloaded to the address counter 123. At this time, the output 1 of the flip-flop 115
29 is inverted and becomes the level "L". At the trailing edge of scan end signal 110, carry signal 10 of adder 102
2 is sampled but remains at level "H" here. Flip-flop 115 on the second line
Output 129 is at level "L", the AND circuit 11
The output 111 of No. 8 remains at the level “L” (step S4). Therefore, the value of the register A 103 does not change and remains “0.75”, and the output 104 of the adder 102
The value of is 0.5 as in the first line. Similarly to the case of one line, the output 128 of the flip-flop 114 is inverted at the trailing edge of the main scanning synchronization signal 109 and becomes the level "L" (step S5). The scan end signal 110 at the end of the transfer of the second line is generated, but the flip-flop 11
Since the output 128 of 4 is at level "L", the output 125 of the WAND circuit 117 remains at level "H" and is not loaded into the address counter 123. That is N + m
The address counter 123 indicates a value of +1 (step S6). At this time, the output 129 of the flip-flop 115 is inverted and becomes the level "H". At the third line, the output 129 of the flip-flop 115 is at the level “H” as in the case of the first line, so the latch clock 111 is output to the register 103 and the value 0.5 of the output of the adder 102 is latched. . Hereinafter, operations similar to those for the 1st line and the 2nd line are executed in the 3rd, 4th, 5th, and 6th lines. On the seventh line, carry signal 116 of adder 102 becomes level "L" (step S7). In the flip-flop 114, the carry signal 116 is input.
The output 128 remains at the level "L" even at the trailing edge of the main scanning synchronization signal 109 after the level "L".
At the end of the transfer of the 7th line, the output 129 of the flip-flop 115 becomes the level "L" due to the rise of the scan end signal 110 (step S9). At this time, since the output 128 of the flip-flop 114 is at the level "L", the counter load signal 125 is not output and remains at the level "L". At the falling edge of the scan end signal 110, the level “L” of the carry signal 116 of the adder 102 is sampled by the flip-flop 132, the output 130 thereof becomes the level “L”, the flip-flop 115 is cleared, and the output 129 is the level. It becomes "H" (step S10). On the eighth line, the output 129 of the flip-flop 115 is at level “H”, 0.75 is latched in the register 103 at the rising of the main scanning synchronization signal 109, and the adder 102
Carry signal 116 becomes level "H" (step S11). At the falling edge of the scan end signal 110 on the eighth line, the carry signal 116 is sampled by the flip-flop 132, and the output 130 thereof becomes the level “H”. Hereinafter, 3, 4, 5, 6, 7, and 8 lines are repeated.

Needless to say, the present invention is not limited to a printing apparatus which converts into a video signal and outputs the video signal, but can be configured in a printing apparatus which can increase the printing density in the paper carrying direction.

It is also possible that the CPU 1 executes the data transfer to the printing section and controls the sub-scanning direction while calculating the reduction ratio.

It is also possible to set the address of the image memory in the DMA circuit each time the transfer of each line is completed, while the CPU 1 calculates the reduction rate by the DMA circuit.

[0014]

As described above, by increasing the print density in the paper conveying direction, that is, the sub-scanning direction, it is possible to prevent the deterioration of the image at the time of reduction and obtain a high quality image.

[Brief description of drawings]

FIG. 1 is an overall block diagram of an embodiment of the present invention.

FIG. 2 is a detailed block diagram of an embodiment of the present invention.

FIG. 3 is a timing chart of an embodiment of the present invention.

FIG. 4 is a diagram showing an example of setting a reduction rate in the present embodiment.

FIG. 5 is a diagram showing a relationship between main scanning and sub scanning.

FIG. 6 is a diagram showing scanning lines in a normal scanning direction and a reduction case in the sub-scanning direction in the present embodiment.

[Explanation of symbols]

 1CPU 2ROM 3RAM 5 Video signal generation unit 6 Printing unit 101 Reduction ratio register 102 Adder 103,119 register 132,115,114 Flip-flop 12 Address counter

Claims (1)

[Claims] 1. A means for changing the print density with respect to the paper conveyance direction, and a means for judging whether data of the same line is printed a plurality of times or once according to the reduction ratio. And printing device.