JPH0613448A - Semiconductor device - Google Patents

Abstract

PURPOSE:To suppress power consumption by separating from a power supply a circuit for exclusive use for testing which is used when selecting a wafer, without adding an extra power terminal to a semiconductor device. CONSTITUTION:A main body circuit section 1 which performs a normal operation of a semiconductor device is directly connected to a power terminal Vcc and a circuit section for exclusive use for testing 2 which conducts a test for checking a characteristic when selecting a wafer is connected to the power terminal Vcc through a fuse element F which can be optically separable. By operating the circuit 2 when selecting a wafer and by conducting a fuse cut for a finished goods, power consumption of the semiconductor device is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a test-dedicated circuit effective for a characteristic test on a semiconductor wafer.

[0002]

2. Description of the Related Art In a semiconductor device manufacturing process, a characteristic test for individual chips, that is, a wafer test is performed before a pelletizing process. FIG. 3 is a block diagram of a conventional semiconductor device having a dedicated circuit for wafer test.
In this example, the main body circuit portion 1 and the test dedicated circuit portion 2 are connected in parallel between the power supply terminal V _CC and the ground terminal GND.

The test-dedicated circuit section 2 includes a circuit for setting the state of the main body circuit section 1, a circuit for reading the state, a ring oscillator for indirectly measuring the gate delay time of the main body circuit section, and the like. Is provided.

The test-dedicated circuit section 2 is a circuit that becomes unnecessary after the completion of the wafer test. In the semiconductor device shown in FIG. 3, however, a current flows through the test-dedicated circuit section 2 even during normal operation. In a semiconductor device such as a semiconductor device, the power consumed wastefully increases. Therefore, in order to suppress the power consumption during the normal operation, as shown in FIG. 4, there is a semiconductor device in which power is supplied to the test dedicated circuit section 2 through the test power supply terminal V _TEST only during the wafer test. .

In this circuit, during the wafer test, power is supplied to both the main body circuit section 1 and the test dedicated circuit section 2 by the probe through the power supply terminal V _CC and the test power supply terminal V _TEST to perform a predetermined test. The power supply terminal V _CC is connected to the external terminal, but the test power supply terminal is not connected to the external terminal. That is, during normal operation, only the main body circuit section 1 receives power.

[0006]

The above-mentioned first conventional example has a drawback in that the power consumption of the entire semiconductor device increases because a current always flows through the test-dedicated circuit during normal operation. In the second conventional example shown in FIG. 4, the power consumption can be suppressed, but the dedicated pad V for the wafer test is used.
There is a drawback that _TEST is required, and there is also a problem that more probes have to be used during the test.

[0007]

The semiconductor device of the present invention comprises:
The main body circuit section and the test dedicated circuit section used only during the wafer test share the same power supply terminal, and the connection between the test dedicated circuit section and the power supply terminal is cut off. The devices that can be connected are connected.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. In the semiconductor device of the present embodiment, the main body circuit section 1 and the test dedicated circuit section 2 are connected in parallel between the common power supply terminal V _CC and the ground terminal GND, and the power supply terminal V _CC is connected.
A fuse element F that can be cut by a laser beam or the like is inserted between the test-only circuit section and the circuit. Here, the test-dedicated circuit unit 2 includes a ring oscillator for measuring the delay time of the gate, a circuit for setting an internal state in the body circuit of the semiconductor device, a circuit for reading the state of the body circuit, and the like. ing.

Next, the operation of the apparatus of this embodiment will be described. When a wafer selection test is performed in the semiconductor device manufacturing process, the fuse element F is in a conductive state, and when a power supply voltage is applied to the power supply terminal V _CC by the probe, both the main body circuit section 1 and the test dedicated circuit section 2 It becomes an operating state. Here, an operation test of the main body circuit section of the semiconductor device alone and a characteristic confirmation test of the semiconductor device using the test dedicated circuit section 2 are performed. After the wafer test is completed, the fuse element F is cut by the laser beam.

FIG. 2 is a block diagram showing a second embodiment of the present invention. In this embodiment, unlike the first embodiment, the dedicated test circuit section 2 is connected to the power supply terminal V _CC via the transistor TR, and the fuse element F is connected to the base of the transistor TR. In this embodiment, when the power supply current of the main body circuit portion is large and the current capacity of the fuse element is small, it is possible to suppress an increase in the area and the number of fuse elements to be used.

[0011]

As described above, in the semiconductor device of the present invention, the test-dedicated circuit section is connected to the power supply terminal to which the main body circuit section is connected via the element capable of being disconnected. Therefore, according to the present invention, it is possible to reduce power consumption during normal use, reduce the number of terminals in the test-dedicated circuit section, and reduce the number of probes required during the test.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram of a first conventional example.

FIG. 4 is a block diagram of a second conventional example.

[Explanation of symbols]

1 Main unit circuit 2 Test-dedicated circuit F Fuse V _CC Power supply terminal GND Ground terminal V _TEST Test power supply terminal

Claims (1)

[Claims] 1. A test-dedicated circuit used in a wafer test and a regular main body circuit are connected to the same power supply terminal, and the connection between the power-supply terminal and the test-dedicated circuit is cut off. A semiconductor device in which elements capable of being connected are connected.