JPH0613321A - Forming method for silicon thin film - Google Patents

Forming method for silicon thin film

Info

Publication number
JPH0613321A
JPH0613321A JP16602392A JP16602392A JPH0613321A JP H0613321 A JPH0613321 A JP H0613321A JP 16602392 A JP16602392 A JP 16602392A JP 16602392 A JP16602392 A JP 16602392A JP H0613321 A JPH0613321 A JP H0613321A
Authority
JP
Japan
Prior art keywords
thin film
film
tantalum oxide
resist
silicon thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16602392A
Other languages
Japanese (ja)
Inventor
Tsutomu Hashizume
勉 橋爪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP16602392A priority Critical patent/JPH0613321A/en
Publication of JPH0613321A publication Critical patent/JPH0613321A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To selectively form a silicon film having a clean front surface without contamination on a substrate by forming a tantalum oxide thin film patterned in a shape necessary for the substrate, and selectively coating a region in which the oxide film is not exposed with a silicon thin film by a chemical vapor growing method. CONSTITUTION:A clean glass substrate SBS is covered with a tantalum oxide TOX by a sputtering method. Then, a resist film RSL is formed on the tantalum oxide film TOX. Thereafter, a resist is photosensed and developed so as to allow the resist of a necessary part to remain, and a partial tantalum surface is exposed. Then, the tantalum oxide of the exposed part is removed by etching. Subsequently, a surface PTX of contaminated tantalum oxide is removed by a dry etching method using CF4 gas. Then, a silicon thin film SFL is formed by low pressure chemical vapor deposition(LPCVD). Thus, the silicon thin film having no contamination of impurity of the resist can be formed on the substrate.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】シリコン基板上の集積回路やアク
ティブマトリクス型平面ディスプレイのMOS型トラン
ジスタのシリコン薄膜の形成に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to formation of a silicon thin film of a MOS transistor of an integrated circuit on a silicon substrate or an active matrix type flat display.

【0002】[0002]

【従来の技術】アクティブマトリクス型の液晶ディスプ
レイの素子である薄膜トランジスタの能動層はシリコン
薄膜が利用されている。この薄膜トランジスタのシリコ
ン薄膜にとって電気特性を低下させるナトリウムなどの
不純物は大敵である。
2. Description of the Related Art A silicon thin film is used as an active layer of a thin film transistor which is an element of an active matrix type liquid crystal display. Impurities such as sodium that deteriorate the electrical characteristics are a serious enemy for the silicon thin film of this thin film transistor.

【0003】コプラナー型の薄膜トランジスタのシリコ
ン薄膜は、図2(a)に示すように、まずパッシベーシ
ョン膜が表面に形成された清浄なガラス基板SBS上に
減圧化学気相成長法によりシリコン薄膜PSLを形成
し、次に図2(b)に示すようにレジストRSLを塗布
し、次に図2(c)に示すようにフォトリソグラフィー
法でレジストをパターニングPRSして、さらに、図2
(d)の様に露出したシリコン膜をエッチング除去し、
さらに、図2(e)に示すようにシリコン膜上に残った
レジストを除去することによりパターニングされたシリ
コン薄膜DSSを形成していた。
As shown in FIG. 2 (a), a silicon thin film of a coplanar thin film transistor is formed by first forming a silicon thin film PSL on a clean glass substrate SBS having a passivation film on its surface by a low pressure chemical vapor deposition method. Then, a resist RSL is applied as shown in FIG. 2 (b), and then the resist is patterned PRS by a photolithography method as shown in FIG. 2 (c).
The exposed silicon film is removed by etching as shown in (d),
Further, as shown in FIG. 2E, the resist remaining on the silicon film is removed to form the patterned silicon thin film DSS.

【0004】この従来の方法では、図2(b)に示すよ
うにシリコン薄膜上にレジストを塗布するときに、レジ
ストに含まれているNaなどの不純物が、シリコン膜表
面に付着したり、レジストを構成している有機物の分子
や炭素原子がシリコン表面に結合して、不純物に汚染さ
れたシリコン表面SIPを形成していた。このシリコン
膜で構成された薄膜トランジスタは、シリコン膜とゲー
ト絶縁膜の界面準位が大きく、電気的特性が劣化してい
た。
In this conventional method, when a resist is applied on a silicon thin film as shown in FIG. 2 (b), impurities such as Na contained in the resist adhere to the surface of the silicon film or the resist is resisted. The molecules and carbon atoms of the organic substance that constitute the silicon atom are bonded to the silicon surface to form a silicon surface SIP contaminated with impurities. In the thin film transistor formed of this silicon film, the interface state between the silicon film and the gate insulating film is large, and the electrical characteristics are deteriorated.

【0005】また、シリコン薄膜の汚染された表面を、
過酸化水素水とアンモニアと水の混合液で洗浄する試み
もあるが、汚染を完全に除去することは困難であった。
In addition, the contaminated surface of the silicon thin film is
There have been attempts to wash with a mixed solution of hydrogen peroxide solution, ammonia and water, but it was difficult to completely remove the contamination.

【0006】[0006]

【発明が解決しようとする課題】この発明は、「従来の
技術」で述べたような表面汚染のない、パターニングさ
れたシリコン薄膜の製造方法と、シリコン能動層とゲー
ト絶縁膜の間の界面に汚染のない薄膜トランジスタの製
造方法を提供する。
SUMMARY OF THE INVENTION The present invention provides a method for producing a patterned silicon thin film without surface contamination as described in "Prior Art" and an interface between a silicon active layer and a gate insulating film. A method for manufacturing a thin film transistor without contamination is provided.

【0007】[0007]

【課題を解決するための手段】この発明は、基板に必要
な形状にパターニングされた酸化タンタル薄膜を形成す
る工程と、化学気相成長法によりシリコン薄膜を選択的
に被着形成することを特徴とするシリコン薄膜の形成方
法を提供する。
The present invention is characterized in that a step of forming a tantalum oxide thin film patterned into a required shape on a substrate and a selective deposition of a silicon thin film by chemical vapor deposition. A method of forming a silicon thin film is provided.

【0008】また、この発明は、基板に酸化タンタル膜
を形成する工程と、この酸化タンタルをパターニングす
る工程と、化学気相成長法により酸化タンタル膜が露出
していない領域に選択的にシリコン膜を形成する工程
と、このシリコン膜上に酸化シリコン膜を被着形成する
工程と、この酸化シリコン膜上にゲート電極を形成する
工程を含むことを特徴とする薄膜トランジスタの製造方
法である。
Further, according to the present invention, a step of forming a tantalum oxide film on a substrate, a step of patterning this tantalum oxide film, and a silicon film selectively in a region where the tantalum oxide film is not exposed by a chemical vapor deposition method. And a step of forming a silicon oxide film on the silicon film, and a step of forming a gate electrode on the silicon oxide film.

【0009】[0009]

【実施例】以下、本発明の詳細を図示の実施例によって
説明する。
The details of the present invention will be described below with reference to the illustrated embodiments.

【0010】まず、図1(a)に示すように、表面を絶
縁膜PBLで覆われた清浄なガラス基板SBS上にスパ
ッタ法により酸化タンタル膜TOXを200nmの厚み
で被着形成する。次にレジスト膜RSLをこの酸化タン
タル膜TOX上に形成する。このとき、従来例と同じ理
由で、レジストを被着する工程により、酸化タンタル膜
TOX上の表面PTXがNaなどの不純物により汚染さ
れる。
First, as shown in FIG. 1A, a tantalum oxide film TOX having a thickness of 200 nm is formed by sputtering on a clean glass substrate SBS whose surface is covered with an insulating film PBL. Next, a resist film RSL is formed on this tantalum oxide film TOX. At this time, for the same reason as in the conventional example, the surface PTX on the tantalum oxide film TOX is contaminated with impurities such as Na in the step of depositing the resist.

【0011】次に、図1(b)に示すように、必要な部
分のレジストを残すように、レジストを感光し現像し、
一部の酸化タンタル表面を露出する。
Next, as shown in FIG. 1 (b), the resist is exposed to light and developed so as to leave a necessary portion of the resist,
Expose some tantalum oxide surface.

【0012】次に、図1(c)に示すように、CF4
スを用いたドライエッチング法により、露出した部分の
酸化タンタルをエッチング除去し、さらにレジスト膜P
RSを過酸化水素水を含んだ98℃の濃硫酸で溶解除去
する。このとき絶縁膜PBLが露出した表面SFSを汚
染することはない。
Next, as shown in FIG. 1C, the exposed portion of tantalum oxide is removed by etching by a dry etching method using CF 4 gas, and the resist film P is further removed.
RS is dissolved and removed with concentrated sulfuric acid containing hydrogen peroxide solution at 98 ° C. At this time, the exposed surface SFS of the insulating film PBL is not contaminated.

【0013】次に、図1(d)に示すように、レジスト
中に含まれた不純物によって汚染された酸化タンタルの
表面PTXを、CF4ガスを用いたドライエッチング法
により除去する。この工程により、基板SBS上のレジ
ストによる汚染は完全に除かれる。
Next, as shown in FIG. 1D, the surface PTX of tantalum oxide contaminated by the impurities contained in the resist is removed by the dry etching method using CF 4 gas. By this step, contamination by the resist on the substrate SBS is completely removed.

【0014】次に、図1(d)まで処理された基板上
に、図1(e)に示すように減圧化学気相成長(LPC
VD)法により、シリコン薄膜SLFを形成する。基板
温度が600℃、モノシランの流量が40sccmの条
件であると、酸化シリコン膜で形成されている絶縁膜P
BLが露出している領域には、多結晶シリコン膜が形成
されるが、酸化タンタル薄膜上には、シリコン膜が形成
されない。
Next, as shown in FIG. 1E, low pressure chemical vapor deposition (LPC) is performed on the substrate processed up to FIG. 1D.
The silicon thin film SLF is formed by the VD) method. When the substrate temperature is 600 ° C. and the flow rate of monosilane is 40 sccm, the insulating film P formed of a silicon oxide film is formed.
A polycrystalline silicon film is formed in the region where BL is exposed, but no silicon film is formed on the tantalum oxide thin film.

【0015】LPCVD法は、10%以内のばらつきで
直径200mmの基板上に20nmの厚みのシリコン薄
膜を形成することができる。
The LPCVD method can form a silicon thin film having a thickness of 20 nm on a substrate having a diameter of 200 mm with a variation of 10% or less.

【0016】つまり、本発明方法により、レジストの不
純物の汚染のない、わずか20nm程度の厚みのシリコ
ン薄膜を選択的に基板上に形成することが可能である。
That is, according to the method of the present invention, it is possible to selectively form a silicon thin film having a thickness of only about 20 nm on a substrate without contamination of resist impurities.

【0017】[0017]

【発明の効果】この発明によると、汚染がない清浄な表
面であるシリコン膜を選択的に基板上に形成できる。こ
の方法で形成されたシリコン膜を利用すると、能動層と
ゲート絶縁膜の界面準位が小さい電気的に優れた薄膜ト
ランジスタを製造することができる。
According to the present invention, a silicon film, which is a clean surface without contamination, can be selectively formed on a substrate. By using the silicon film formed by this method, an electrically excellent thin film transistor in which the interface state between the active layer and the gate insulating film is small can be manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例のシリコン薄膜の製造方法の
工程図。
FIG. 1 is a process drawing of a method for manufacturing a silicon thin film according to an embodiment of the present invention.

【図2】 従来例の図。FIG. 2 is a diagram of a conventional example.

【符号の説明】[Explanation of symbols]

SBS …基板 PBL …絶縁膜 TOX …酸化タンタル薄膜 PTX …レジストの不純物が入った酸化タンタル薄膜 RSL …レジスト膜 PRS …パターニングされたレジスト膜 SFS …露出した絶縁膜表面 SLF、PSL …シリコン薄膜 SIP …汚染されたシリコン薄膜の表面 DSS …パターニングされたシリコン薄膜 SBS ... Substrate PBL ... Insulating film TOX ... Tantalum oxide thin film PTX ... Tantalum oxide thin film containing resist impurities RSL ... Resist film PRS ... Patterned resist film SFS ... Exposed insulating film surface SLF, PSL ... Silicon thin film SIP ... Contamination Surface of patterned silicon thin film DSS ... Patterned silicon thin film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板に必要な形状にパターニングされた
酸化タンタル薄膜を形成する工程と、化学気相成長法に
よりシリコン薄膜を酸化タンタル膜が露出していない領
域に選択的に被着形成することを特徴とするシリコン薄
膜の形成方法。
1. A step of forming a tantalum oxide thin film patterned into a required shape on a substrate, and selectively depositing a silicon thin film on a region where the tantalum oxide film is not exposed by a chemical vapor deposition method. A method for forming a silicon thin film, comprising:
【請求項2】 請求項1において化学気相成長法が減圧
化学気相成長法であることを特徴とするシリコン薄膜の
形成方法。
2. The method for forming a silicon thin film according to claim 1, wherein the chemical vapor deposition method is a low pressure chemical vapor deposition method.
JP16602392A 1992-06-24 1992-06-24 Forming method for silicon thin film Pending JPH0613321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16602392A JPH0613321A (en) 1992-06-24 1992-06-24 Forming method for silicon thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16602392A JPH0613321A (en) 1992-06-24 1992-06-24 Forming method for silicon thin film

Publications (1)

Publication Number Publication Date
JPH0613321A true JPH0613321A (en) 1994-01-21

Family

ID=15823501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16602392A Pending JPH0613321A (en) 1992-06-24 1992-06-24 Forming method for silicon thin film

Country Status (1)

Country Link
JP (1) JPH0613321A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5614232A (en) * 1992-05-07 1997-03-25 Minnesota Mining And Manufacturing Method of making an interengaging fastener member

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5614232A (en) * 1992-05-07 1997-03-25 Minnesota Mining And Manufacturing Method of making an interengaging fastener member

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