JPH06131310A - Parallel processor and serial/parallel converter - Google Patents

Abstract

PURPOSE:To make the arithmetic of longitudinal image data possible when the number of data is less than the number of processor elements. CONSTITUTION:For example, a pointer generation circuit 24 in a shift register for input can store data Fm, Gm,... at the totally two parts of an m-th register 22m and an m+M/2-th register 22m+M/2 by generating an ON signal (pointer) in every M/2 cycle. Thus, the data Fm and Gm can be stored in the same memory 3m for input, and the conventionally disabled longitudinal operation is enabled as well. At such a time, the operation to data for a 2h-th horizontal term, for example, is performed by 1st-M/2-th processor elements (arithmetic circuits 51-5M/2) and the operation to data for a 2h+1-th horizontal term is performed by M/2+1-th-Mth processor elements (arithmetic circuits 5M/2+1-5M).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processor and a serial / parallel converter used for digital processing of video signals.

[0002]

2. Description of the Related Art As a device for digitally processing a video signal, for example, "SVP: SERIAL VIDEO PR
OCESSOR / Proceedings of the
eIEEE 1990 CUSTOM INTEGRA
TED CIRCUITS CONFERENCE / P.
The device shown in 17.3.1-4 "is known.

This device is specifically composed of a parallel processor as shown in FIG. 4, for example. That is, in the figure, for example, an image shift signal in which each pixel is composed of a plurality of bits is word (pixel) serially input (terminal 1) and has a capacity (M) for one horizontal period (1H). M in (serial / parallel converter) 2
It is stored in this register. The registers in the input shift register 2 are M input side memories 3 _{1 to} 3 respectively.
Connected to _M.

The M arithmetic circuits 5 _{1 to} 5 _M are supplied with data from the corresponding input side memories 3 _{1 to} 3 _M and the input side memories on both sides thereof via selectors (SEL) 4 ₁ to 4 _M. In addition, there are M output side memories 7 _{1 to} 7 _M
Data from the corresponding output memories 7 _{1 to} 7 _M and the output memories on both sides thereof are also selected by the selector (SEL) 6
It is supplied via a ₁ to 6 _M. The output results from the arithmetic circuits 5 _{1 to} 5 _M are written in the input side memories 3 _{1 to} 3 _M or the output side memories 7 _{1 to} 7 _M. Output side memory 7
_{1 to} 7 _M are output shift registers (parallel / parallel)
The serial converter 8 is connected to M registers. Then, from the output shift register 8, for example, an arithmetically processed video signal in which each pixel is composed of a plurality of bits is output in a word (pixel) serial manner (terminal 9).

Therefore, in this device, the data of each pixel of the video signal supplied to the input shift register 2 for each horizontal period is written in the input side memories 3 _{1 to} 3 _M within the subsequent horizontal blanking period. . This input side memory 3
_The data written in _{1 to} 3 _M is supplied to the arithmetic circuits 5 _{1 to} 5 _M during the next one horizontal period, and the values subjected to the arithmetic processing are written in the output side memories 7 _{1 to} 7 _M. Then, during the subsequent horizontal blanking period, the output side memories 7 _{1 to} 7 _M
Data is written in the output shift register 8 and the video signal subjected to the arithmetic processing for each horizontal period is taken out. In this way, for example, digital processing of the video signal is performed.

The address control of the input side memories 3 _{1 to} 3 _M and the output side memories 7 _{1 to} 7 _M and the arithmetic circuits 5 _{1 to} 5
Control of the operation in the _M, and the selector 4 ₁ ~4 _M, 6 ₁ ~
There is only one arithmetic control circuit 10 for controlling 6 _M , and all M input side memories 3 _{1 to} 3 _M , output side memories 7 _{1 to} 7 _M , arithmetic circuits 5 _{1 to} 5 _M , And selector 4
It is common in _{1 ~4 M, 6 1 ~6 M} . That is, FIG.
Is SIMD (Single Instruction)
The Multiple Data method is used. In video signal processing, the same arithmetic processing is often performed on all pixels, so that the SIMD method of giving the same processing instruction to all arithmetic circuits can be sufficiently applied and there is no inconvenience. The SIMD method has the advantage that only one control circuit 10 is required and the circuit scale is reduced.

Under the control of the selectors 4 ₁ to 4 _M and 6 _{1 to} 6 _M , the m-th arithmetic circuit 5 _m stores data stored in the m-th input memory 3 _m and output memory 7 _m ( 1
Not only the calculation of the m-th pixel data of the video signal for the horizontal period (1H) but also the calculation of the data (m-1th and m + 1th pixel data) on both sides thereof can be performed.

The set of the input side memory 3, the output side memory 7, the selectors 4 and 6 and the arithmetic circuit 5 are called a processor element, and FIG. 4 is called a parallel processor because there are plural processor elements.

Now, a conventional example will be described in more detail regarding the input shift register 2 portion related to the present invention.

A detailed view of the input shift register 2 is shown in FIG. In FIG. 5, unit delay elements (FF) 23 ₂ to 23 _M for supplying control signals (pointers) for controlling the switches 21 _{1 to} 21 _M in the input shift register 2 are shown.
There is a circuit (pointer transmission circuit) 23 connected in cascade. Further, there is a pointer generation circuit 24 for giving an ON signal (pointer) to the pointer transmission circuit 23.

A video signal (D1,
D2, D3 ,. ． ． , DM) are serially supplied.
Further, at the very first time of each 1H, the pointer transmission circuit 23
An ON signal is input from the pointer generation circuit 24 to. Servant
At the time when D1 is input, the first scan
Switch 21₁Is turned on and the first register (R) 2
Two₁D1 is stored in. ON signal is unit with time
Delay element 23₂~ 23 _MThrough the second and subsequent screens.
Switch 21₂~ 21_MTurn on. Therefore, the second
Subsequent register 22₂~ 22_MIs the data after D2
Sequentially stored. And the last video signal DM of 1H
Mth register 22_MImmediately when stored in
Then, in the subsequent horizontal blanking period, D1 to DM are respectively
Corresponding input side memory 3₁~ 3_MMoved to.

The next 1H video signals (E1, E2, E3, ..., EM) supplied serially are similarly stored in order from the _first register 22 ₁ .
Then, in the subsequent horizontal blanking period, they are moved to the corresponding input side memories 3 _{1 to} 3 _M.

For example, a filter calculation with two taps in the vertical direction
Is performed as follows. That is, m (m = 1 to 1
M) th input side memory 3_mAnd Dm as described above
Em is stored. These data are the m-th cell
Kuta 4_mVia the m-th arithmetic circuit 5_mAt Phil
Calculation (Rm = a × Dm + b × Em: a and b are filters
Coefficient) is calculated, and the m-th output side memory 7_mRm
Is stored. And Rm is the horizontal blanking period that follows
In the meantime, the m-th register in the output shift register 8 (Fig. 6)
Star (R) 25_mStored in the next horizontal period
Pointer transmission circuit (unit delay element 27₂~ 27_M)
Switch from the 1st to the Mth in order 26 ₁~ 26_MBut
It is turned on and serially output from R1 to RM.
To be done. In this way, a vertical 2-tap filter
The calculation is done. In addition, the pointer generation circuit in FIG.
28 has the same configuration as that in FIG.

It should be noted here that the pointer generation circuits 24 and 28 can generate the pointer only in M cycles (every M pieces of data).

In the above description, one horizontal period (1
The data for H) was just equal to the number of processor elements (M), but consider the case of lower quality image data below.

That is, the data for one horizontal period (1H) is
Consider the case of M / 2. Video signals (F1, F2, F3, ..., FM / 2) are serially supplied from the input terminal 1. At the same time when F1 is input, the pointer generation circuit 24 generates a pointer. Then, the pointer transmission circuit 23 sequentially turns on the switches 21 _{1 to} 21 _{M / 2} from the first to the M / 2th, and the data (F1, F2, 1H) for one horizontal period (1H) serially supplied.
F3 ,. ． ． , FM / 2, which is a total of M / 2), are sequentially stored from the _first register 22 ₁ .

Therefore, in the subsequent horizontal blanking period,
First to M / 2th register 22 ₁~ 22_{M / 2}In the
The data F1 to FM / 2 are stored. That
At this time, the pointer is M in the pointer transmission circuit 23.
/ Second unit delay element 23 _{M / 2}Exists in. That
1H worth of data (G1,
G2, G3 ,. ． ． , GM / 2) is (M / 2) +1
Register 22 from eye to M_{M / 2 + 1}~ 22_MThe case
Will be paid.

That is, the M / 2th unit delay element 23
_Since the pointer existing at M / 2 moves from (M / 2) + 1th to Mth sequentially, accordingly (M
/ 2) _{+ 1st} to _Mth switches 21 _{M / 2 + 1} to 2
1 _{M / 2} is turned on and each data is stored. Therefore, in the subsequent horizontal blanking period, the data F is stored in the _{first to M /} 2th registers 22 _{1 to} 22 _{M / 2.}
1 to FM / 2 are M / 2 + 1th to Mth registers 2
The data G1 to GM / 2 are stored in 2 _{M / 2 + 1 to} 22 _M. These data are transferred to the corresponding input side memories 3 _{1 to} 3 _M in this horizontal blanking period.

At this time, it is impossible to perform a filter calculation with two taps in the vertical direction. Because m (m = 1 to (M / 2))
Calculation using the second data (P1m = a × Fm + b ×
In order to perform Gm) in the mth arithmetic circuit 5 _m , the data Gm stored in the [1] m + (M / 2) th input side memory is once converted into m + (M / 2) −1. The second selector and the m + (M / 2) −1th arithmetic circuit are used to store the m + (M / 2) −1th input-side memory or the output-side memory, and [2] and m + (M / 2) -m + the data Gm stored in the first input-side memory or output-side memory
(M / 2) -2nd selector and m + (M / 2) -2
Stored in the m + (M / 2) -2nd input side memory or the output side memory via the th arithmetic circuit, [3] and m + (M / 2) -2nd input side memory or output The data Gm stored in the side memory is m +
(M / 2) -3rd selector and m + (M / 2) -3
The data is stored in the m + (M / 2) -third input side memory or the output side memory via the th arithmetic circuit, and :: [(M / 2) -1]. The data Gm stored in the output side memory is m + 1
M through the (th) selector and the (m + 1) th arithmetic circuit
The data Gm stored in the + 1st input side memory or the output side memory is stored in [M / 2], and then the data Gm stored in the m + 1th input side memory or the output side memory is passed through the mth selector. This is because the processing must be performed by supplying it to the arithmetic circuit, which increases the number of instructions and is unrealistic. That is, [1] to [(M
This is because there is an instruction for the data movement of [2) -1].

[0020]

The problem to be solved is that when the data for one horizontal period (1H) is less than the number of processor elements (M), image data in the vertical direction are stored. Since the memory locations are not nearby,
It is said that calculation of image data in the vertical direction was impossible (necessary unrealistic number of instructions).

[0021]

The first means of the present invention is to input a plurality of data serially input from an input terminal to a serial / parallel converter and to output a parallel output of the serial / parallel converter. The data is supplied to a plurality of processor elements in parallel, the data is arithmetically processed by the processor element, and the plurality of arithmetically processed data output in parallel from the processor element is input in parallel to the parallel / serial converter. In the parallel processor which outputs the output of the parallel / serial converter from the output terminal, the same data is output from different output terminals of the serial / parallel converter.

A second means according to the present invention is a serial / parallel converter for outputting data input serially from an input terminal in parallel from an output terminal, having a plurality of switches and a plurality of registers. Input data input from the input terminal is stored in the register via the switch, and the output of the register is taken out in parallel from the output terminal, and a plurality of switches are turned on at the same time. Then, the same data is stored in a plurality of the registers, and the same data is output from different output terminals, which is a serial / parallel converter.

A third means according to the present invention has a plurality of switches and a plurality of registers as the serial / parallel converter, and input data inputted from the input terminal is passed through the switch. In addition to being stored in the register, the output of the register is taken out from the output terminal in parallel, the plurality of switches are turned on at the same time, the same data is stored in the plurality of registers, and different The parallel processor according to the first means is characterized in that the serial / parallel converter that outputs the same data from the output terminal is used.

According to a fourth means of the present invention, different initial values are set in advance in the plurality of processor elements,
According to the first aspect, different arithmetic processing using the different initial values is performed by the same arithmetic instruction on the same data output from different output terminals of the serial / parallel converter. It is a parallel processor described in the means.

[0025]

According to this, even when the data for one horizontal period (1H) is less than the number of processor elements (M),
The vertical image data can be stored in the same memory, and for example, the above-described vertical image data can be calculated.

[0026]

1, a pointer generation circuit 24 in an input shift register, for example, generates an ON signal (pointer) every M / 2 cycles to generate data Fm, Gm ,. ． ． To the m-th register 22
It can be stored in a total of two locations of _m and m + M / 2 second register 22 _{m + M / 2} . As a result, the data Fm and Gm can be stored in the same input memory 3 _m, and vertical calculation, which has been impossible in the past, can be performed. At this time, for example, the operation for the data of the 2hth horizontal period is performed by the _{1st to M /} 2th processor elements (the operation circuits 5 _{1 to} 5 _{M / 2} ) and the data of the 2h + 1th horizontal period is performed. The operation is performed by the _{M / 2 + 1 to M-} th processor elements (operation circuits 5 _{M / 2 + 1 to} 5 _M ).

The operation will be described in more detail. As in the conventional case, consider the case where the data for one horizontal period (1H) is M / 2.

Video signals (F1, F2, F from input terminal 1)
3 ,. ． ． , FM / 2) are serially supplied. F1
The pointer is generated by the pointer generation circuit 24 at the same time as the input of. Then, the pointer transmission circuit 23
From the 2nd to M / 2th switch 21 _{1 to} 21 _{M / 2}
Is turned on and serially supplied for one horizontal period (1H) of data (F1, F2, F3, ..., FM).
/ 2 in total) is stored in order from the _first register 22 ₁ .

Therefore, in the subsequent horizontal blanking period,
First to M / 2th register 22 ₁~ 22_{M / 2}In the
The data F1 to FM / 2 are stored. this
Input side memory corresponding to each horizontal blanking period
Three₁~ 3_{M / 2}Data F1 to FM / 2 are moved to each 1
Be done. At this time, the pointer is the pointer transmission circuit 2
M / 2-th unit delay element (FF) 23 in 3_{M / 2}
Exists in.

Next 1H worth of data (G1, G2, G
3 ,. ． ． , GM / 2) is started to be serially supplied from the input terminal 1 (time when G1 is input), again,
The pointer generation circuit 24 generates a pointer. This causes G1 to switch the first and M / 2 + 1th switches 21
₁ , 21 _{M / 2 + 1} is turned on, so the first and M / 2
It is stored in both the _{+ 1st} registers 22 ₁ and 22 _{M / 2 + 1} . The G2 switches the second and M / 2 + 2nd switches 21 ₂ and 21 at the time when the data is input.
_{Since M / 2 + 2} is turned on, it is stored in both the second and M / 2 + 2nd registers 22 ₂ and 22 _{M / 2 + 2} . Similarly thereafter, Gm (m = 3 to M / 2) is m-th and M / 2.
It is stored in both the _{+ mth} register 22 _m and 22 _{M / 2 + m} .

In the subsequent horizontal blanking period, the first to
The data G1 to GM are stored in the Mth registers 22 _{1 to} 22 _M.
/ 2 is stored in two places each. Input side memory 3 ₁ corresponding to each of the horizontal blanking periods
Data G1~GM / 2 in each of the two address of ~3 _M is transferred.
At this time, the pointer exists in the M / 2-th unit delay element (FF) 23 _{M / 2} in the pointer transmission circuit 23.

The next 1H worth of data (H1, H2, H
3 ,. ． ． , HM / 2) is serially supplied from the input terminal 1 (time when H1 is input), again,
The pointer generation circuit 24 generates a pointer. As a result, the H1 is the first and the M / 2 + 1th switch 21.
₁ , 21 _{M / 2 + 1} is turned on, so the first and M / 2
It is stored in both the _{+ 1st} registers 22 ₁ and 22 _{M / 2 + 1} . H2 has the second and M / 2 + 2nd switches 21 ₂ and 21 _{2 at} the time when the data is input.
_{Since M / 2 + 2} is turned on, it is stored in both the second and M / 2 + 2nd registers 22 ₂ and 22 _{M / 2 + 2} . Similarly, thereafter, Hm (m = 3 to M / 2) is the m-th and M / 2.
It is stored in both the _{+ mth} register 22 _m and 22 _{M / 2 + m} .

In the subsequent horizontal blanking period, the first to
The Mth register is in a state in which the data H1 to HM / 2 are stored in two places each. In this horizontal blanking period, the data H1 to HM / 2 are moved to the respective three addresses of the corresponding input side memories 3 _{1 to} 3 _M. At this time, the pointer exists in the M / 2-th unit delay element (FF) 23 _{M / 2} in the pointer transmission circuit 23.

Therefore, at this time, the data is stored in each of the input side memories 3 _{1 to} 3 _M as shown in FIG.

At this time, a filter calculation with two taps in the vertical direction (P1m = a × Fm + b × Gm) is possible. This is because the data Fm (m = 1 to (M / 2)) is stored in the _mth input memory 3 _m , and the data Gm is also stored in the _mth input memory 3 _m. is there. That is, first, to supply the data Fm that is stored through the m-th selector 4 _m to m-th input side memory 3 _m to m-th arithmetic circuits 5 _m, then m-th selector 4 _m
By supplying the data Gm stored in the m-th input-side memory 3 _m to the m-th arithmetic circuit 5 _m via
Calculation using the second data (P1m = a × Fm + b ×
Gm) can be performed by the m-th arithmetic circuit 5 _m . The calculation result P1m is stored in the m-th output side memory 7 _m.

At the same time, the filter calculation (P2m = a × Gm + b × Hm) of the data for the next 1H is also calculated as m + M / 2.
This can be done with the 5th arithmetic circuit 5 _{M / 2 + m} . That is, first, m +
The data Gm stored in the m + M / 2nd input side memory 3 _{M / 2 + m} is passed through the _{M /} 2th selector 4 _{M / 2 + m} to the m + M / 2nd arithmetic circuit 5 _{M / 2 + m.} , Then m +
The data Hm stored in the m + M / 2th input side memory 3 _{M / 2 + m} is transferred to the m + M / 2 arithmetic circuit 5 _{M / 2 + m} via the _{M /} 2th selector 4 _{M / 2 + m.} By supplying, calculation using the m-th data (P2m = a × Gm + b × H
m) can be performed by the m + M / 2th arithmetic circuit 5 _{M / 2 + m} .

Then, P1m and P2m (m = 1 to M /
2) is the m-th and m + M / 2-th register 25 _m in the output shift register during the subsequent horizontal blanking period.
_{5M / 2 + m} , respectively, and during the next M cycles (that is, two horizontal periods), the pointer transmission circuit 27 sequentially turns on the switches 26 _{1 to} 26 _M from the _first to the _Mth , P11, P12 ,. ． ． , P1M / 2, P2
1, P22 ,. ． ． , P2M / 2 are sequentially output serially. In this way, the vertical 2-tap filter calculation is performed.

However, the pointer generation circuit 28 in the output shift register issues a pointer every M cycles, that is, every two horizontal periods. Further, the arithmetic operation on the data of the 2h-th horizontal period is performed by the processor elements _{1 to M / 2} (the arithmetic circuits 5 _{1 to} 5 _{M / 2} ) and the arithmetic operation on the data of the 2h + 1-th horizontal period is M / 2 + 1- In the Mth processor element (arithmetic circuit 5 _{M / 2 + 1 to} 5 _M ),
Since they are done simultaneously, one processor element
A 2-tap filter calculation (either P1m or P2m) may be performed during M cycles (that is, two horizontal periods).

The calculation in the calculation circuits 5 _{1 to} 5 _M at this time is performed as follows, for example. In advance, 0 is assigned to each of the 4th addresses of the _first to _{M /} 2th input side memories 3 _{1 to} 3 _{M / 2} , and the M / 2 + 1 to Mth input side memories 3
It is written one to each address 4 of the _{M / 2 + 1 ~3 M.} Then, from the control circuit 10 of FIG. 1, [{(value of address 1) ×
(Reverse value at address 4) + (Value at address 2) × (Value at address 4)} × a + {(Value at address 2) × (Reverse value at address 4)
+ (Value of address 3) × (value of address 4)} × b], an instruction for controlling the address of the memory is supplied to each of the input side memories 3 _{1 to} 3 _M , and the calculation is performed. The instruction to perform is supplied to each of the arithmetic circuits 5 _{1 to} 5 _M. By this command,
The calculation result is once stored in an appropriate address of the output side memories 7 _{1 to} 7 _M , and then output by the output shift register.

According to this instruction, in the _first to _{M /} 2th arithmetic circuits 5 _{1 to} 5 _{M / 2} , the 4th address of the input side memories 3 _{1 to} 3 _{M / 2} is 0. Therefore, [{( Value) x (reverse value of address 4) + (value of address 2) x (value of address 4)} x a +
{(Value of address 2) x (reversal of value of address 4) + (value of address 3) x (value of address 4) x b = {(value of address 1: Fm)
× 1 + (value at address 2) × 0} × a + {(value at address 2: G
m) × 1 + (value of address 3) × 0} × b = a × Fm + b ×
Gm = P1m] is calculated, and in the M _{/ 2 + 1 to M-} th arithmetic circuits 5 _{M / 2 + 1 to} 5 _M , the input side memories 3 _{M / 2 + 1 to} 3 _M are calculated.
Since the 4th address of 1 is 1, [{(value of 1st address) × (reversal of value of 4th address) + (value of 2nd address) × (value of 4th address)} ×
a + {(value at address 2) × (inversion of value at address 4) + (value at address 3) × (value at address 4)} × b = {(value at address 1) ×
0+ (value of 2nd address: Gm) × 1} × a + {(value of 2nd address) × 0 + (value of 3rd address: Hm) × 1} × b = a × Gm
+ B × Hm = P2m] is calculated.

In this way, P1m = a × Fm + b × Gm can be calculated in the first to M / 2th processor elements even with the above-mentioned common instruction (control signal), and M / 2 + 1.
˜P2m = a × Gm in the Mth processor element
+ B × Hm can be calculated.

Thus, according to the above apparatus, the data for one horizontal period (1H) is the number of processor elements (M).
Even when the number is smaller, the vertical image data can be stored in the same memory, and for example, the above-described vertical image data can be calculated.

Input side memory 3₁~ 3_MValue at address 4
Is set as an initial value in advance. When setting this initial value
Is issued by the pointer generation circuit 24, for example.
The pointer is not generated for M cycles after
Between input terminals 1 to 0 is M / 2 cycle, 1 is M / 2 cycle
Input data and input this data to the input side memory 3₁~ 3 _M
This is done by writing at address 4.

A configuration example of the switch control circuit is shown in FIG.
In FIG. 3, the rising edge of the H-SYNC signal input from the outside together with the input data is detected by the differentiating circuit, and the output of the differentiating circuit is used as the pointer. As a result, when 1H of data is M / 2, a pointer can be generated every M / 2 cycle.

[0045]

According to the present invention, one horizontal period (1H)
Even when the minute data is less than the number of processor elements (M), the vertical image data can be stored in the same memory, and for example, the vertical image data can be calculated as described above. Became.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an example of a parallel processor and a serial / parallel converter according to the present invention.

FIG. 2 is a diagram for explaining the explanation.

FIG. 3 is a configuration diagram of an example of a switch control circuit.

FIG. 4 is a configuration diagram of a conventional parallel processor and a serial / parallel converter.

FIG. 5 is a configuration diagram of a conventional serial / parallel converter.

FIG. 6 is a configuration diagram of a conventional parallel / serial converter.

[Explanation of symbols]

1 input terminal 3 _{1 to} 3 _M input side memory 4 ₁ to 4 _M , 6 _{1 to} 6 _M selector (SEL) 5 _{1 to} 5 _M arithmetic circuit 7 _{1 to} 7 _M output side memory 9 output terminal 10 arithmetic control circuit 21 ₁ .About.21 _M , 26 _{1 to} 26 _M switch 22 _{1 to} 22 _M , 25 _{1 to} 25 _M register (R) 23 ₂ to 23 _M , 27 _{2 to} 27 _M unit delay element (F.
F. ) 23, 27 pointer transmission circuit 24, 28 pointer generation circuit

Claims (4)

[Claims] 1. A plurality of data serially input from an input terminal are input to a serial / parallel converter, and parallel outputs of the serial / parallel converter are supplied in parallel to a plurality of processor elements, and these data are input. Are processed by the processor element, and the plurality of processed data output in parallel from the processor element are input in parallel to the parallel / serial converter, and the output of the parallel / serial converter is output from the output terminal. A parallel processor for outputting, wherein the same data is output from different output terminals of the serial / parallel converter. 2. A serial / parallel converter for outputting data input serially from an input terminal in parallel from an output terminal, wherein the serial / parallel converter has a plurality of switches and a plurality of registers. The input data coming in is stored in the register via the switch, and the output of the register is taken out from the output terminal in parallel. The serial / parallel converter is characterized in that the same data is stored in the register of and the same data is output from different output terminals. 3. The serial / parallel converter,
It has a plurality of switches and a plurality of registers, and the input data input from the input terminal is stored in the register via the switch and the output of the register is taken out in parallel from the output terminal. Use a serial / parallel converter that turns on multiple switches at the same time, stores the same data in multiple registers, and outputs the same data from different output terminals. The parallel processor according to claim 1, wherein: 4. Different initial values are set in advance in the plurality of processor elements, and different initial values are given to the same data output from different output terminals of the serial / parallel converter by the same operation instruction. 2. A different arithmetic process using is performed.
The described parallel processor.