JPH06131241A - Data processor - Google Patents

Abstract

PURPOSE:To decrease the frequency of access by a CPU and shorten the processing time by accessing other specific predetermined addresses at the same time when a specific address is accessed. CONSTITUTION:The data processor which is equipped with a storage space 10 where addresses (a-d) are assigned, various peripheral devices 111-11n, and an address bus 13 and a data bus 14 connecting the storage space 10, peripheral devices 111-11n, and a CPU 12, and transfers 80 address signal generated by the CPU 12 t0 the storage space 10 and peripheral devices 111-11n through the address bus 13 and makes the CPU 12 access the storage space 10 or peripheral device whose assigned address matches the transferred address signal through the data bus 14, a duplication (e.g. (d) and (c)) of the addresses assigned to the storage space 10 and peripheral devices 111-11n is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a data processing device intended to improve processing speed. Generally, a Neumann-type data processing device that sequentially executes a program has a drawback that the processing speed becomes slower as the number of program steps increases. Therefore, for example, efforts have been made to shorten the processing cycle by increasing the clock frequency, but there is a limit to this, and a new technique capable of improving the processing speed by a simple method is required.

[0002]

2. Description of the Related Art FIG. 11 is a schematic block diagram of a conventional data processing device. In this figure, 1 is CPU (cent
ral processing unit), 2 is a memory, 3 is a peripheral device that assists the CPU 1 (here, it is a product-sum calculator for convenience), 4 is a data bus, and 5 is an address bus.

A unique address is assigned to the memory 2 and the product-sum calculation unit 3, and for example, if the assignment address of the memory 2 is "X" and the assignment address of the product-sum calculation unit 3 is "Y". If the address signal transferred from the CPU 1 to the address bus 5 indicates X, the data bus 4
If the memory 2 is accessed from the CPU 1 via the CPU or the address signal indicates Y, the CP
The product-sum calculator 3 is accessed from U1.

Here, as an operation example of the data processing device including the product-sum calculation unit 3, n-th order (for example, fourth-order) FIR filter processing will be described. This FIR filter process realizes the same function as a digital filter by software, and as shown in the calculation conceptual diagram of FIG. 12, the product (x _i × x) of the sampling input x _{i of} this time and the coefficient h _0. h ₀ ), and the product (x) of the previous sampling input x ₋₁ and the coefficient h _1
−1 × h ₁ ) and the product of the sampling input x ₋₂ two times before and the coefficient h ₂ (x ₋₂ × h ₂ ) is found, and the product of the sampling input x ₋₃ three times before and the coefficient h ₃ (X ₋₃ × h ₃ ), and then the sum y _i (y _i = x _i × h ₀ ) of these calculation results
+ X ₋₁ × h ₁ + x ₋₂ × h ₂ + x ₋₃ × h ₃ ). Z ⁻¹ is a delay element having a delay time corresponding to one sampling period.

Input x_i, X_-1, X_-2, X_-3And coefficient h₀,
h₁, H₂, H₃The number of each is four here,
This number is the same as the order of the FIR filter. Memory 2
These inputs x_i, X_-1, X_-2, X_-3And coefficient
h₀, H₁, H₂, H₃Variable area for storing
Reserved, eg 4 addresses for input
X₀, X_-1, X_-2, X_-3But also 4 for coefficients
Address H₀, H₁, H₂, H₃Has been assigned
It That is, address H₀~ H₃FIR filter for
Coefficient h required for processing₀~ H₃Is stored and
Space X₀~ X_-3X out of ₀Always has the latest input x₀Is case
As it is paid, this x₀Is the sampling period (Z^-1of
Sequential X for each delay time interval)₀→ X_-1→ X_-2→ X_-3To
It is supposed to shift.

X_iAnd h₀When finding the product of
Area S surrounded by a line₀First, note from CPU1
Address 2 of Re2₀To access its contents (x₀)
It is read by the CPU 1 and then the multiplicand register of the product-sum calculator 3 is read.
Contents read into register 3b (x₀) Write. Next
At address H of memory 2₀To access its contents
(H₀) Is read into the CPU 1, and then the product-sum calculator 3
Contents read into the multiplier register 3a of₀)
Mu. Then, the CPU 1 activates the product-sum calculation unit 3,
Contents of multiplicand register 3b (x₀) And multiplier register 3a
Contents of (h₀) And the multiplication result (x₀× h₀) Get. It
In addition, x_-1× h₁, X_-2× h ₂And x_-3
× h₃Sum of these after repeating at_iSeeking this time
After completing the multiply-accumulate calculation process of
The contents of are shifted one by one to prepare for the next product-sum operation
It The shift operation is the address X₀→ X_-1→ X_-2→ X_-3of
This is done by transferring the contents in order.

[0007]

However, in such a conventional data processing apparatus, a unique address is assigned to the memory 2 and the peripheral device 3 (for example, a product-sum calculation unit), and the memory 2 is designated by the CPU 1. And the peripheral device 3 are accessed individually,
For example, in the case where the data processing in the memory 2 (for example, processing by multiply-add operation) and the data rearrangement in the memory (for example, shift operation) are both executed, the CPU 1 performs both data processing and shift operation. Access is required, and particularly for a high-order FIR filter in which the number of data processing and shift operations is large (proportional to the order), the number of accesses by the CPU 1 is significantly increased. There is a problem that the time becomes long. [Purpose] Therefore, according to the present invention, when a specific address is accessed, it is possible to simultaneously access other predetermined specific addresses, and
It is an object of the present invention to reduce the number of times of access by U, thereby shortening the processing time.

[0008]

In order to achieve the above-mentioned object, the present invention has a storage space 10 and various peripheral devices 11 to which addresses (a to d) are assigned, as shown in the principle diagram of FIG. _{1 to} 11 _n , an address bus 13 and a data bus 14 that connect the storage space 10 and various peripheral devices 11 _{1 to} 11 _n to the CPU 12, and an address signal generated by the CPU 12 is transferred to the address bus 13. Through the storage space 10 and various peripheral devices 1
1 ₁ to 11 was transferred to _n, assigned address matches a said transfer address signal storage space 10 or various peripheral devices 11
_{1 to} 11 _n are transferred to the CPU 12 via the data bus 14.
In the data processing device accessed from the above, a part of the addresses assigned to the storage space 10 and the various peripheral devices 11 _{1 to} 11 _n are overlapped (for example, D and C). The storage space 10 is a virtual space formed by the register 10a and the memory 10b.
Reference numeral 16 is an address map, the structure of which is an example.

[0009]

In the present invention, the CPU 12 to the peripheral device 11
_When a specific address (c) assigned to _n is accessed, an address common to this peripheral device 11 _n (d)
The storage space 10 to which is allocated is simultaneously accessed. Alternatively, when a specific address (d) assigned to the storage space 10 is accessed from the CPU 12, the peripheral device 11 _n to which a common address (c) is assigned to the storage space 10 is simultaneously accessed.

That is, it becomes possible to simultaneously access both the peripheral device 11 _n and the storage space 10, and, for example, the data bus 1 is connected to the peripheral device 11 _n and the storage space 10.
The data on 4 can be written at the same time. Therefore, when the peripheral device 11 _n is the product-sum calculator at the beginning, the data processing by this product-sum calculator and the rearrangement of the data in the storage space 10 can be performed simultaneously in parallel, and the access by the CPU is possible. The number of times can be reduced and the processing time can be shortened.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 10 are views showing an embodiment of a data processing device according to the present invention, and are examples of a data processing device used for controlling rotation of a joint motor of a robot or the like, for example.

First, the structure will be described. In FIG. 2, 2
Reference numeral 0 is a data processing device. The data processing device 20 is C
PU (central processing unit) 21, RAM (rando
m access memory) 22, ROM (read only memory)
23, UART (universal asynchronous receiver tr
ansmitter) 24, A / D converter 25, timer 2
6, PWM (pulse width modulation) 27, product-sum calculator (sometimes simply referred to as calculator) 28, WDT (watchdog timer) 29, I / O port 30, and various buses (data bus, address bus, control) Bus) 3
It is configured to include 1 and the like. In addition, this data processing device 2
0 may be made in one chip.

As is well known, the CPU 21 has an arithmetic logic unit (ALU), a program counter, various registers, etc. inside, and a RAM 22 and a ROM 2 according to an address indicated by the program counter.
It fetches instructions from 3, and executes them sequentially,
For example, while executing each command of the motor control program, various control values necessary for matching the joint angle and the angular velocity of the robot with a desired target value are calculated. The RAM 22 is a general-purpose memory for securing a variable area and a work area of the motor control program, and the ROM 23 is a read-only memory for storing the motor control program, an OS (operating system), a BIOS (basis input output system), and the like. And these RAM 22
The ROM 23 and the registers inside the CPU 21 form a storage space. Further, the UART 24 is a device having an asynchronous serial communication function, and includes a transmission / reception unit, a bidirectional conversion unit for serial data and parallel data, a transmission / reception data format generation unit, a data decoding unit, etc. For example, it receives the detection data from the motor rotation angle detector and transmits the drive data to the motor drive unit. The A / D converter 25 converts analog detection data into digital data, the timer 26 generates a reference clock, and the PWM 27 uses a variable pulse width signal for driving a motor based on a control value calculated by the CPU 21. Is generated, the WDT 29 judges a program abnormality (runaway) when the CPU 21 does not execute an instruction even after the stipulated time is exceeded, and the I / O port 30 is connected to various detectors and motor drive units (not shown). The signal interface between the two.

Here, the arithmetic unit 28 is a device that specially executes predetermined arithmetic processing (in this example, product-sum arithmetic processing) instead of the CPU 21, that is, a peripheral device having a function of assisting the CPU 28. As peripheral devices, in addition to the arithmetic unit 28, the UART 24, A / D
The converter 25 and the PWM 27 correspond to these peripheral devices, and their peripheral devices are assigned unique addresses in advance.

FIG. 3 is a configuration diagram of a main part including a CPU 21, a RAM 22 and a calculator 28. In this figure, 31a
Is a control bus, 31b is an n-bit wide data bus, 31c is also an n-bit wide address bus, 22a.
Is an address decoder (hereinafter referred to as R
An AM address decoder), 22b is a RAM main body, 28a is an address decoder provided in the arithmetic unit 28 (hereinafter, referred to as an arithmetic unit address decoder), 28b is an area designation register, and 28c is an arithmetic unit main body.

The RAM address decoder 22a has a specific address range (RA on the address map) in which the address signal on the address bus 31c is predetermined.
When an address included in the entire address range of M22 is displayed, a signal for permitting a read or write operation to the RAM main body 22b is output. The arithmetic unit address decoder 28a is an address on the address bus 31c. address included in; signal, specific address ranges specified (see FIG. 7 for example, the address range of the input variable region X ₀ to X _-3 of RAM22 entire address range on the address map) by the area designation register 28b Is displayed, the data on the data bus 31b is transferred to the arithmetic unit main body 28c. That is,
The content of the area designation register 28b is the address information corresponding to the first area described in the gist of the invention, and when the first address information and the address signal on the data bus 31b match, the first area information At the same time as accessing the area (input variable area of RAM 22) indicated by the address information of 1,
The arithmetic unit 28 is accessed. this is,
In other words, this corresponds to simultaneously accessing the addresses of the arithmetic units 28 assigned on the address map.

FIG. 4 is a diagram showing an example configuration of the arithmetic unit main body 28c. The arithmetic unit main body 28c receives the data on the data bus 31b in response to the multiplicand write signal from the arithmetic unit address decoder 28a and outputs the multiplicand register A.
Similarly, a multiplier register B that takes in data on the data bus 31b in response to a multiplier write signal from the arithmetic unit address decoder 28a and a product calculator 28d (B that multiplies the contents of the multiplicand register A and the multiplier register B
It is desirable to adopt the ooth algorithm and Wallace tree configuration), the addition unit 28e that adds the output of the product calculation unit 28d and the previous addition result (that is, the content of the latch 28f), and the addition result is sequentially updated. Latch 28f for holding the total sum, product calculation unit 28d and addition unit 28e
And a timing control unit 28g that generates a latch signal at each time in consideration of the total operation delay of.

FIG. 5 is a diagram showing an example of the structure of the timing controller 28g. In this example, the multiplier write signal generated by the arithmetic unit address decoder 28a is delayed by the two D-FFs 28h and 28i which are synchronized with the system clock, and the AND signal between the delayed signal and the system clock is taken to obtain the latch signal. Is output from the AND gate 28j.

FIG. 6 is a diagram showing an example of the configuration of the address decoder for arithmetic unit. In this example, the upper bits of the address signal on the address bus 31c (e.g., A ₀ 6 high order bits of the 8-bit address signal to ~A ₇ A ₂ ~A ₇₎
To one of the inputs, and the data (B _{2 to} B ₇ ) stored in the area designation register 28b to the other of the plurality of exclusive NOR gates 28k to 28.
q and the outputs of the ENOR gates 28k to 28q are all H
When the level (A ₂ ~A ₇ = when B ₀ ~B ₇₎ to configure a multi-input AND gate 28r which outputs a multiplier write signal and multiplicand write signal H level.

Next, the operation will be described. Now, the fourth-order FIR filter processing described in the conventional example, that is, the product (x _i × h ₀ ) of the current sampling input x _i and the coefficient h ₀ is obtained as shown in FIG. Input x _-1
And the coefficient h ₁ (x ₋₁ × h ₁ ) are calculated, and the product (x ₋₂ × h ₂ ) of the sampling input x ₋₂ two times before and the coefficient h ₂ is calculated,
The product of the sampling input x _-3 three times before and the coefficient h ₃ (x _-3 ×
h ₃ ), and then the total sum y _i of these calculation results
(Y _i = x _i × h ₀ + x _-1 × h ₁ + x _-2 × h ₂ + x _-3 ×
Consider the case of finding h ₃ ).

Here, as shown in FIG. 7, a variable area (hereinafter referred to as a coefficient) for storing the coefficients h ₀ to h ₃ from the address 10h (h represents a hexadecimal number) to the address 13h of the RAM 22. Variable area) and address 14h
1 to 17h are secured as variable areas (hereinafter, input variable areas) for storing the inputs x ₀ to x _-3 .

The area designation register 28b stores a value indicating the range (14h to 17h) of the input variable area. FIG. 8 is a main part flowchart of the FIR filter process. In this flowchart, four steps S
_For each _{1 to} S ₄ , the coefficients h _{3 to} h ₀ are taken out and set in the multiplicand register A, and the inputs x _{0 to} x _-3 are taken out and set in the multiplier register B, and set in the multiplier register B. In parallel with this, the shift operation (x ₀ → x _-1 , x _-1 → x _-2 , x _-2 → x _-3 ) in the input variable area is executed.

FIG. 9 is a time chart inside the arithmetic unit 28.
is there. Read / write signal on control bus 31a
(R / W) indicates the write mode (W),
When the multiplier write signal goes high, the data at that time
Data on bus 31b (coefficient h ₀~ H₃Is one of the
It is stored in the number register A. Then, the above shift operation
Address value on the address bus 31c is 1
Change to any of 4h to 17h (address of input variable area)
Then, the address signal and the area designation register 28b
And the multiplier write signal goes high.
Then, the data on the data bus 31c at that time (that is,
Input x read for shift operation₀~ X_-3Of 1
Are also set in the multiplier register B at the same time.

Therefore, according to the above configuration, the RAM
22 The shift operation of the inputs x _{0 to} x _-3 inside and the set operation of the inputs x ₀ to x _-3 to the multiplier register B can be performed simultaneously in parallel, so that the shift operation can be performed independently. The processing steps (see steps Sa to Sc in the FIR filter processing program flow of the conventional example shown in FIG. 10) can be eliminated, and the number of accesses of the CPU 21 can be reduced accordingly, and the processing speed can be improved.

In this embodiment, the product sum operation of the FIR filter processing is taken as an example, and the data storage in the multiplier register B and the data shift operation in the RAM 22 can be executed simultaneously in parallel. However, it is not limited to this. In short, when a specific address (or area) on the address map is accessed by the CPU, at least one other address (or area) can be simultaneously accessed, and these specific address and other The address may be a physical address in a storage space formed by a RAM, a ROM and a register, an address assigned to various peripheral devices, or a combination thereof.

[0026]

According to the present invention, when a specific address is accessed, it is possible to simultaneously access other predetermined specific addresses.
It is possible to reduce the number of accesses due to, and to shorten the processing time.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is an overall block diagram of an embodiment.

FIG. 3 is a configuration diagram of a main part including a RAM and an arithmetic unit according to an embodiment.

FIG. 4 is a configuration diagram of an arithmetic unit according to an embodiment.

FIG. 5 is a configuration diagram of a timing control unit according to an embodiment.

FIG. 6 is a configuration diagram of an arithmetic unit address decoder according to an embodiment.

FIG. 7 is a conceptual diagram of a variable area according to an embodiment.

FIG. 8 is a program flow of a main part of one embodiment.

FIG. 9 is an operation time chart of an example.

FIG. 10 is a program flow of a conventional example shown for comparison.

FIG. 11 is a schematic configuration diagram of a conventional example.

FIG. 12 is a conceptual diagram of calculation of a 4th-order FIR filter.

[Explanation of symbols]

10: Storage space 11 _{1 to} 11 _n : Various peripheral devices 12: CPU 13: Address bus 14: Data bus

Claims (4)

[Claims] 1. A storage space (10) to which addresses (A to D) are assigned, and various peripheral devices (11 ₁ to 1)
1 _n ), the storage space (10) and various peripheral devices (11 ₁ ~
11 _n ) and the CPU (12) are provided with an address bus (13) and a data bus (14), and an address signal generated in the CPU (12) is stored in the storage space via the address bus (13). (10) and various peripheral devices (11 _{1 to} 11 _n ), and a storage space (10) whose assigned address matches the transfer address signal or various peripheral devices (11 _{1 to} 11 _n ),
In a data processing device accessed from a CPU (12) via the data bus (14), the storage space (10) and various peripheral devices (11 ₁ ...
11 _n ) part of the addresses assigned to ( _n ) are overlapped (for example, d). 2. Holding first address information corresponding to a first area on an address map including respective addresses of the storage space and various peripheral devices, the first address information and the transfer address signal. 2. The data processing apparatus according to claim 1, wherein if the two match, the first area on the address map and the second area other than the first area are simultaneously accessed. 3. The first and second areas are represented by a single address value.
The described data processing device. 4. The data processing apparatus according to claim 2, wherein one of the first and second areas is expressed in a predetermined address range.