JPH023821A - High speed arithmetic unit - Google Patents

Abstract

PURPOSE:To execute an arithmetic processing in a small unit at high speed by permitting the function unit of an operation part which is address-designated to output its own processing data to an operation part bus and permitting a function unit which as not been address-designated to fetch data on the operation part bus. CONSTITUTION:A control part 21 including a processor (CPU) 26 and the opera tion part 22 where plural function units 28(1)-28(n) for which addresses are respectively given are mutually connected by the operation part bus 24, are provided and the part 22 is connected with the control part 21 with an interface part 23. For a first control instruction which CPU 26 has given by designating addresses to the function units 28(1)-28(n) of the operation part 22, a read instruc tion, for example, the function unit which is address-designated outputs its own processing, data to the operation part bus 24 and the function unit which is not address-designated fetches data of the operation part bus 24 for executing respective and prescribed functions. Thus, operation can be execute in the opera tion part whenever CPU 26 gives a read command, and the considerably high speed processing can be executed.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figures 15 to 17) Problems to be Solved by the Invention Means for Solving the Problems (Figures 1 to 17) Functions Embodiments (Figs. 4 and 5) Modifications (Figs. 6 to 14) Effects of the invention "Summary" Regarding a high-speed arithmetic device, the purpose is to execute arithmetic processing in small units at high speed, and a processor is used. and an arithmetic unit in which a plurality of functional units each having an address are interconnected by an arithmetic unit bus. In response to the first control command issued by specifying an address, the addressed functional unit outputs its own processing data to the processing unit bus, and the non-addressed functional units output the data on the processing unit bus. , each configured to be captured to perform a predetermined function.

[Industrial Application Field] The present invention relates to a high-speed arithmetic device that executes processing such as arithmetic operations in small units at high speed.

are combined.

[Prior Art] As an arithmetic circuit that executes an arithmetic operation, one using a microprocessor or one in which a dedicated arithmetic circuit is assembled with hardware logic are known.

Furthermore, a system using a back-end processor 32 as shown in FIG.

Furthermore, a calculation board 35.3 as shown in FIG.
A CPU board using 33.6 is also known, and this one uses a CPU board 33. A memory board 34, arithmetic boards 35, 36, etc. are connected via a bus.

Furthermore, a coprocessor 3 as shown in FIG.
8 is also known, and this one uses CPU37
, a coprocessor 38, a local memory 39, etc., are connected by an internal bus 41, and connected to an external bus 42 via an external bus interface 40. [Problems to be solved by the invention] Using a microprocessor allows for freedom with a simple circuit. Although it is possible to perform highly sophisticated calculation control, microprocessors have slow calculation speeds.

If a dedicated circuit is assembled using hardware logic, the scale will increase. Also, the degree of freedom is low.

Backend processor 32 as shown in FIG.
In a device using
, the data transfer speed slows down, and it takes time to notify the hit from the host computer 31 to the back-end processor 32. Furthermore, since the processing unit to be performed by the back-end processor 32 becomes large, it is difficult to perform detailed control. Moreover, it becomes a large-scale device.

In an apparatus using arithmetic boards 35 and 36 as shown in FIG. 16, data transfer between the arithmetic boards becomes a problem.

That is, although it depends on the method of control commands from the CPU board 33, in general, the processing is slow because the command is written in the command register of the arithmetic board, then the execution command is issued, and the completion status is waited for. The computation board also lacks expandability.

In a device using a coprocessor 38 as shown in FIG.
It is interpreted at the same time as U37, and the data transfer width is determined by the internal bus and is generally the same as the number of data bits of the CP LJ, for example, 16 bits or 32 bits.

In this device, it is practically difficult to create a special coprocessor suitable for each application. For example, if you make it using random logic, it will be too large to fit 4 boards. It is also possible to use a gate array, but there is a limit to the circuit scale. For example 3
Megabyte ROMs are currently difficult to obtain. There are also limits to extensibility. It is necessary to prepare many sockets for coprocessors on the CPLI board.

The devices described above are good for performing bulk processing, but
It is not very fast for executing detailed processing one after another. Furthermore, it lacks scalability.

Therefore, an object of the present invention is to provide a high-speed arithmetic device having a configuration suitable for executing processing in small units at high speed.

[Means to solve problems] FIG. 1 is a principle block diagram according to the present invention.

The high-speed arithmetic device according to the present invention includes, as one form, a control unit 21 including a processor (CPU) 26, and a plurality of functional units 28 (+j to 28(n) each assigned an address.
) is provided with an arithmetic unit 22 that is mutually coupled via an arithmetic unit bus 24, and the control unit 21 and the arithmetic unit 22 are connected to an interface unit 23.
is combined with

The CPU 26 then operates the functional unit 28 (1) of the calculation section 22.
) to 28(n), the addressed functional unit outputs its own processing data to the operation unit bus 24, and the addressed functional unit outputs its own processing data to the operation unit bus 24. The other functional units are configured to take in data on the arithmetic unit bus 24 in order to perform their respective predetermined functions.

In another aspect of the present invention, a plurality of addresses are assigned to one functional unit, and this functional unit is configured to perform a different function for each designated address when addressed.

In the present invention, as another form, CPtJ26
In response to a second control command (for example, a grab command) that is issued by addressing the functional units 28(1) to 28(n) of the calculation unit 22, only the addressed functional units perform a predetermined function. configured to run.

In the present invention, as still another form, CPtJ2
In response to the second control command issued by 6 by addressing the functional unit of the calculation unit 22, the interface unit 23 transfers at least part of the data from the control unit 21 as is onto the calculation unit bus 24 of the calculation unit 22. It is configured as follows.

In the present invention, as yet another embodiment, the CPU
In response to the first control command issued from the control unit 26, the interface unit 23 is configured to transfer at least part of the data on the calculation unit bus 24F of the calculation unit 22 as is to the control unit 2I.

In yet another embodiment of the present invention, the interface section includes an input/output register that serves both as input and output, and a selector that switches data input to the input/output register to either data from the control section or data from the arithmetic section. The input/output register is configured so that part of the data contents of the calculation section can be modified on this input/output register.

[Operation] The arithmetic processing in the arithmetic unit 22 is performed by the CPU 2 of the control unit 21.
This is performed using a first control signal, for example a read signal, issued by the computer 6 as a calculation command. Each functional unit 28(1) to 28(n) in the calculation unit 22 has a different address, for example, 0-FFFF memory + 0000-10OFF peripheral equipment (terminal, FD
D, IIDD,,,) 10100-101FF 256 calculation boards are allocated.

First, when the CPU 26 of the control unit 2 specifies an address for one of the functional units 28(1) to 28(n) of the calculation unit 22 and issues a read signal, this address signal and read signal are transmitted via the interface unit 23. and is transmitted to the calculation unit 22. Then, in the arithmetic unit 22, the addressed functional unit outputs data to the arithmetic unit bus 24.

At this time, other non-addressed functional units take in and latch the data on the arithmetic section bus 24, and start executing their respective functions (for example, arithmetic operations, ROM conversion, etc.). This process is completed before the next read signal is issued.

That is, for example, it is assumed that calculation boards 281 to 283 are connected as functional units to the calculation unit bus 24'' as shown in FIG. 230 is an interface board, which is a connection board with the C-PU section.

First, the CPU 26 sets data in a register of the board 230 by a normal write operation.

Next, the address of the board 230 is designated and a read signal is issued. Then, the data in register 5 is transferred to operation unit bus 24.
is output to. The other calculation boards 281 to 283 (calculation boards not specified by the address) are connected to the calculation unit bus 24.
The data is taken into the input register R. The calculation boards 281 to 283 complete their calculations until the next read signal arrives.

When the CPO 26 specifies the arithmetic board 281 with an address at the time of the next read signal, the arithmetic unit of the arithmetic board 281 has already finished its calculation, so it can immediately output data.

The calculations are repeated in the same manner, and finally the CPU 26 reads data from the input register R of the interface board 230 to obtain the calculation result. FIG. 3 shows a time chart in this case.

With the above configuration, each time the CPU 26 specifies the address of a functional unit of the calculation section 22 and issues a read command, the calculation section 22 can perform one operation, making it possible to perform extremely high-speed processing. Furthermore, simply by changing the order of the addresses output by the CPtJ26, calculations of different patterns can be performed, providing a high degree of freedom. Changing the order of addresses is extremely easy, as all you have to do is change the order of the machine words.

Embodiments] The present invention will be described in detail below with reference to the drawings. Fourth
The figure is a block diagram showing a high-speed arithmetic device as an embodiment of the present invention. In the figure, the device of this embodiment is composed of an execution control section and a data calculation section.

The execution control unit includes a CP tJ board 1 that issues various commands, a memory board 2, a ROM board 3, and an arithmetic unit interface board 4. 020 interconnecting these boards 1-4
It is configured to include a section bus 10.

The data calculation unit is in charge of communication with the data input/output interface board 9 that transfers data with the data way, the calculation board 6 that executes calculation processing, the two-dimensional ROM board 8 that mounts ROM, and the execution control unit. It is configured to include a CPU bus interface board 5, a register board 7, etc., and is connected to the aforementioned execution control section via a connection cable 12 stretched between the interface ports 4 and 5. This data calculation section is configured to be able to simultaneously calculate three sets of 16-bit data using a 48-bit data bus.

The functions of each board of the execution control section are as follows.

The CPU board l controls the entire processor! Performs 6-bit scalar operation. In order to increase the speed of calculations, the CPU is equipped with a microprocessor and a coprocessor for calculations, and generates an operation sequence to control the data calculation section.

The memory board 2 is a multi-pass board on which read/write memory with a capacity of 8 Mbytes is mounted.

It is connected to the CPU board 1 via a 32-bit wide high-speed data transfer bus, allowing high-speed data access.

A microprocessor on the CPU board 1 can access this memory board 2.

The ROM board 3 is a multi-pass board mounted with a read-on memory having a capacity of 1 Mbyte. It is connected to the CPU board l by a 32-bit wide high-speed data transfer bus.
High-speed data access is possible. This board stores a table of bigonal functions and the like, and the microprocessor on the CPU board l accesses them as necessary.

The arithmetic unit interface board 4 is a multipath board that transfers data to the arithmetic unit bus 11. It performs handshake with the CPLJ bus section and drives the connection cable 12 between the CPU bus section and the calculation section bus section. In addition, the CPU
The part bus 10 has the data width of the CPU.

The functions of each board of the data calculation section are as follows.

The CPtJ bus interface board 5 is a 3W board that performs data transfer with the execution control section. Transmits operation control commands from the execution control unit to each board of the data calculation unit.

It also receives three words of 16-bit data from the execution control section and converts it into 48-bit data for the data calculation section.

Also, the 48-bit data of the data calculation section is read out in 16-bit units and transferred to the CPtJ section 1.

FIG. 5 shows the detailed configuration of this CPU bus interface board 5. As shown in the figure, 1 from the execution control section
An output register 51 that converts 6-bit data into 48-bit data of the data calculation section, an input register 52 that converts 48-bit data from the data calculation section into 16-bit data for the execution control section, and a buffer memory 5 for address signals.
3. Buffer memory 54 for control signals, buffer gates (2), (4) to (6), (8) to (
10) etc.

The two-dimensional ROM board 8 is a 3W board equipped with a read-on memory having a capacity of 3M bytes.

Store a table for data conversion. The calculation board 6 is a 3W board that performs high-speed calculations. A high-speed arithmetic unit is provided for arithmetic operations for every 16 bits. The arithmetic unit performs arithmetic operations in units of 16 bits, and can perform processes such as addition and subtraction, bit processing, shifting, and setting constants. Since the arithmetic circuit employs Barbard architecture, one execution per cycle is possible.

The register board 7 is a 3W board that temporarily stores data. 32 is provided with a RAM having a word capacity. In addition to random access, the register can also be used like a FIFO by advancing a pointer every time one word is read or written. Therefore, by executing the same instruction sequence,
It is possible to process a large amount of data sequentially.

The data input/output interface board 9 is a 3W board that transfers data with other devices. This board is CP
In addition to transferring data one word at a time under the control of the U, it can also automatically handshake successive data strings sent over the data cable and continuously capture them into the internal buffer, or store them in the internal buffer. It has a burst transfer function that sends all data. This feature allows data to be transferred at hardware processing speeds, while also allowing the microprocessor to perform other tasks during data transmission and reception.

Note that the calculation unit bus +1 has a data width that is optimal for calculations in the data calculation unit, and in this embodiment, it has a width of 48 bits with three 16-bit data as one set. It is also assumed that different addresses are assigned to each of the boards 5 to 9 in the data performance section.

The operation of this embodiment device will be explained below. First, CPU board 1 of the execution control section is connected to board 1 of the data calculation section.
Address one and issue a read command. This read command and address signal are sent to the calculation section interface board 4.
, the connection cable 12, and the CPU bus interface board 5 to the data calculation unit.

Then, in the data calculation unit, processed 48-bit data is sent to the calculation unit bus 11 from the addressed board. At this time, other boards to which no other address has been designated take in the data on this operation unit bus 11 and execute processing according to the functions of each board.

For example, the two-dimensional ROM board 8 inputs data on the arithmetic unit bus 11 to the ROM, performs data conversion, and latches the result in a register. Therefore, in the next cycle (next read command), the conversion result of the ROM is already prepared in the register, and the conversion result can be immediately output by the read command. It is assumed that the read command cycle is determined so that the processing performed by each board is completed before the next read command is issued.

In this way, in the data calculation section, all the boards can execute unit processing at the same time in response to a read command from the execution control section. The execution control section continuously issues read commands while changing addresses, thereby making it possible to process a series of calculations at high speed. And CPU board l is C
A calculation result can be obtained by reading data from the input register 52 of the PU bus interface board 5.

The operation of the C)) U bus interface section will be briefly explained below. To send data from the execution control section to the data calculation section, the CPU board l must send the data! It sets 6 bits in three times in the output register 51, and then specifies the CPU-to-CPU bus interface board 5 with an address and issues a read command. With this read command, the contents of the output register 51 are sent to the calculation section bus 11.

On the other hand, when the CPU reads the data in the data calculation section, it addresses the calculation board targeted by the data calculation section and issues a read signal. Then, the data of that board is sent to the calculation unit bus 11 and latched into the input register 52 of the CPU bus interface board 5. The CPU reads the latched data in three parts of 16 bits each.

Various modifications are possible in carrying out the present invention, and these modifications will be described below.

The first modification is intended to solve the following problems in the above-mentioned embodiment. That is, in the embodiment described above, only one address was assigned to one calculation board. For this reason, each calculation board had to have a single function.

However, since an ALU board or the like mounted with an arithmetic processor is capable of performing various operations such as addition and subtraction, it is economical to make it possible to select a plurality of functions for each arithmetic board.

Therefore, in this modification, one or more addresses are assigned to one calculation board, and depending on the address value,
It also allows selection of functions. For example, a certain RO
For M board, address to 1004-10
Allocate within the range of 1007, and select functions such as outputting the value of the sine function when accessed at 101004, outputting the value of the cosine function when accessed at 101005, etc.

The method of controlling the arithmetic board is carried out in accordance with the procedure shown in FIG. That is, (1) Is the read signal coming? (Step Sl).

If the read signal is active, proceed to step s2; otherwise, return to step s1.

- Does the address bus value specify this calculation board (step S2)? If it's from this calculation board,
Proceed to step S3, otherwise proceed to step S4.

(2) Adds the processing specified by the address value to the data in the input register and outputs the result to the arithmetic unit bus (step S3).

(2) While the read signal is active, the process remains in step s4, and when it is no longer active, the process proceeds to step S5.

(2) Latch the value of the operation unit bus into the input register (step S5).

■Return to step St.

This will be explained in more detail by giving a specific example. Now, assume that a plurality of addresses, such as the following, are assigned to each board of the data calculation section.

0-FFFF: Memory + 0000-100FF: Peripheral equipment (terminal, FDD
, IIDD, , , )+0100-1 Old leaf: Operation board +0110-1011F: Register board +012
0-1012F: 2D ROM board 10!3O-
1013F: Data input/output interface board +0140-1014F: CPU bus interface board The operation board determines whether it is addressed or not.
You can find out by decoding the 5th bit or more from the bottom. The lower 4 bits are used as a function specification code. An example of function designation on the processing board will be explained below.

When the arithmetic board is addressed as 10100, it outputs the value of the input register as it is without performing any arithmetic operation.

When specified as +0101, the value of the input register is stored in the internal register of the arithmetic unit. The output value will be the same as the input register value.

When specified as +0102, the value of the input register and the value of the internal register of the arithmetic unit are added and the resulting value is output. The values in the internal registers of the arithmetic unit do not change.

When specified as 10103, the value of the input register and the value of the internal register of the arithmetic unit are added and the resulting value is output. The value of the internal register of the arithmetic unit becomes the added value.

When specified as +0104, the value in the internal register of the arithmetic unit is subtracted from the value in the input register, and that value is output. The values in the internal registers of the arithmetic unit do not change.

When specified as 10105, the value in the internal register of the arithmetic unit is subtracted from the value in the input register, and the value is output. The value of the internal register of the arithmetic unit becomes the value after the subtraction.

FIG. 6 is a diagram showing an example of the structure of the register board in this modification. As shown in the figure, this register board 7 has a decoder 71 for decoding read signals and address signals.
, a pointer 72, a RAM 73, a gate 74, and an input register 75. In addition, this register board 7
In this case, the relationship between the output of the decoder and the address and read signals is as follows.

Pointer CLR near address = l old and old l and READ =
L Pointer INc Near address: 101012 and READ = 1° RAMWR Near address = 101013 and REA
D=L Buffer output address=lold/oldX and READ=
L Input register latch: Address l other than old and old and R
EAD=L When the upper 16 bits of the register board are 1011, it is determined that the board has been designated.

When the register board is specified as +0110,
Clear the pointer value to O.

When specified as +0111, the value of the pointer is incremented.

When specified as +0102, the value of the pointer is stored in the RAM cell pointed to by the pointer. The output will be the same as the value in the input register.

When specified as 10103, the value of the input register is stored in the RAM cell pointed to by the pointer. The pointer is incremented after being stored. The output will be the same as the value in the input register.

When specified as +0104, the RA pointed to by the pointer
Output the contents of M.

When specified as 10105, the RA pointed to by the pointer
Output the contents of M. The pointer is incremented after being output.

By changing the addresses as described above, the content of the processing executed on each board of the data calculation section can be changed.

(Hereinafter blank) Another modification of the present invention will be described below with reference to FIG. In each of the above-mentioned embodiments, read commands are used to control all calculations, and the board that receives the read command always outputs some data, and other calculation boards latch that data. . However, some operations on the computing board do not have valid outputs. For example, in a write operation to the RAM of a register board, the output may become unstable depending on the circuit system.

For example, in the register board shown in Figure 6, the data output DO becomes high impedance when writing to the RAM 73, so
The value output to the calculation unit bus 11 becomes undefined.

If this operation is executed with a read command, the values latched into the input registers of other calculation boards will become undefined. As a result, if it is necessary to store intermediate results of a calculation in the RAM 73, with this method, the data becomes undefined and the calculation is interrupted.

Therefore, without destroying the input register values of other calculation boards,
A configuration that allows data to be loaded into RAM is required. The modification shown in FIG. 8 is intended to solve this problem. In this modification, in response to a write command from the CPU board 1, only the addressed board performs processing specific to that board. That is, the eighth
As shown in the figure, a write signal line for transmitting a write command is added to the calculation unit bus 11. Only the board specified by the address responds to the write signal line. Other boards ignore this. That is, even if a pulse is applied to the write signal line, the data is not latched into the input register.

In this way, even when data is written to the register board, by using the write signal, the values of the input registers of other calculation boards are not destroyed, and the calculation can be continued.

In the register board of FIG. 8, the decoder 71 generates the following outputs in response to address signals and write signals.

Pointer CLR: Address specification 101011 and WR
ITE=L Pointer INC near address=l old/old 2 and WRITE=L RAM WR near address=101013 and WRI
TE=L Buffer output Near address=1 old/old X AND READ=L Input register clutch: Address=1 other than old/old X and
READ-L Other calculation boards are similarly manufactured based on the following guidelines. That is, data is output when the own board is designated by the address line and the state is READ-L. The input register is latched when the address specifies a board other than the own board and is READ-L. In this case, data is latched at the rising edge of the read signal. Write commands are used to perform processing specific to the processing board without outputting data.

FIG. 1O is a diagram for explaining still another modification of the present invention, and shows a modified configuration of the CPLI bus interface 5. This modification is intended to address the following problems.

That is, some of the data output by the CPU is not data to be calculated, but is data for setting the calculation board, for example, a pointer value. It is sufficient if this data can be transferred only to a specific computing board, rather than being broadcast to all computing boards. When attempting to transfer this data using a read command, two steps are required: setting the data in the CPU interface 5, then specifying the address of the CP tJ interface 5 and issuing the read command. This is a waste of time.

Furthermore, in a system in which setting data of a certain calculation board is transferred by a read command, the setting data of a calculation board not specified by the address is also latched in the input register. In other words, even if valid data was previously secured in the input register, that data will be overwritten and deleted. Therefore, it becomes impossible to reset the calculation board during the data calculation process.

The above will be explained in more detail by giving specific examples. It is assumed that the configuration of the data calculation section is as shown in FIG. That is, it includes a CPU interface port 230 and calculation boards 284 to 286.

It is assumed that the data to be calculated in the calculation section of the configuration shown in FIG. 9 is stored in the RAM of the board 284. The processing content is to sequentially read the data stored on the auxiliary board 284, process it with the arithmetic unit of the arithmetic board 285, and store it in the IIAM of the arithmetic board 286. The processing contents of the arithmetic unit on the arithmetic board 285 are as follows:
When it is 000 or more, subtract 512 from the data. Otherwise, 512 is added to the data. ”. It is assumed that this instruction to the arithmetic unit is already stored in the ROM. In other words, the ROM address O is 10.
RO, an instruction that compares data with 00 and outputs the status
It is assumed that an instruction to subtract 512 from data and output the result is stored at address 1 of M, and an instruction to add 512 to data is stored at address IO.

First, CP tJ clears the pointers of the calculation boards 284-286.

Next, the arithmetic board 284 is addressed and a read command is issued. The data stored in the IIAM of the calculation board 284 is output to the calculation unit bus 11, and the data is latched into the input registers of the boards 285 and 286.

Next, the arithmetic board 285 is addressed and a read command is issued. If the function specified by the lower four bits of the address is arithmetic execution and pointer increment, the arithmetic unit executes the instruction at address O, and then the pointer pointing to the ROM is incremented. The instruction at address O is 1000
It was an instruction to compare the data and output the status. The arithmetic unit compares the data with 1000, and outputs the data to the arithmetic unit bus 11 as a status. The CPU can determine whether the data is larger than 1000 by checking the status of the execution result.

If it is larger than 1000, the address of the calculation board 285 is specified and a read command is issued. Assuming that the functions specified by the lower 4 bits of the address are arithmetic execution and pointer increment. The arithmetic unit executes the instruction at address l, and then increments the pointer pointing to the ROM. The instruction at address I was to subtract 512 from the data, so the arithmetic unit executed it and the output was the result.

This result is simultaneously latched into the input register of board 286, so that the contents of the input register on board 286 can be
A read command is issued by specifying the function using the four bits of the address to write to AM. This completes one cycle of instructions.

A problem here arises when the data read from the board 284 is less than 1000. In this case, the value of the pointer on the calculation board 285 is updated to 10, and ll0M becomes 5.
We need to output an instruction to add 12. To set the pointer to 10, the CPU usually
It is possible to set 10 in register 9 of J interface board 230 and send it to the bus of the data calculation section, but in this case, there is a drawback that the contents of input register 5 of board 285 are changed to 10. Even if the pointer is rewritten to 10, the important data will be lost. Therefore, there is a need for a method of changing only the pointer without changing the data.

The difference between the CPU bus interface board shown in FIG. 1O and the one shown in FIG.
6 pits can be sent directly to the arithmetic unit bus 11 via the buffer gate (3) (ie, without passing through the output register 5I). In this case, the buffer gate (2) opens when the CPU bus interface board 5 is addressed and a read command is issued. Further, the buffer gate (3) is opened when a write command is issued.

With this configuration, when the CPLI issues a write command, the data output by the CPU passes through the buffer gate (3) and is directly placed on the operation unit bus It. Since only the addressed board responds to the write command, only the addressed board receives and receives data from the CPU, and other boards do not operate.

This allows data to be directly transferred to the target arithmetic board without setting setting data on the CPU bus interface board 5, resulting in faster processing. Furthermore, it is also possible to prevent valid data held in input registers of other boards from being destroyed by this data setting operation to a specific board.

FIG. 11 is a diagram showing another modified example of the history of the present invention. 1
In each of the embodiments described in 1q, when the CP LJ reads data on the board of the data calculation section, the data on the board is read out from the CP LJ.
The data is temporarily held in the input register of the U bus interface board 5, and then the CPU bus interface 5 is addressed to read the data.

With this method, even when the CPU reads data that is not subject to calculation (for example, indicating calculation status, overflow, etc.), it must go through the input register 52 of the HCPU bus interface board 5, which slows down the processing. - On the other hand, data other than the data to be operated on does not need to be reused, so there is no need to latch it into the input register 51.

This modified example is an improvement made in view of this point, and is based on the first modification.
As shown in Figure 1, the CPU bus interface board 5 has been changed. In other words, the lower 1 of the data on the calculation unit bus 11
A new path is provided to directly lead the 6 bits to the CPU section bus 10 without going through the input register 52. and CP L.J.
issues a read command (read signal line is closed, OW
), if the address signal specifies CP LJ bus interface port 5, buffers (4) to (
6) is opened, and on the other hand, if the address signal specifies a port other than the CPU bus interface port 5, the buffer (7) is opened.

With this configuration, when the CPU issues a read command, the data on the operation unit bus 11 is not only latched into the input register 52 of the CPU bus interface board 5, but also a part of the data (for example, the lower 16 bit) is CP
It will be transferred directly to the U section. Therefore, when the CPU reads data other than the data to be operated on, there is no need to read the contents of the input register 52 again only for the data that is directly sent, and the speed is increased accordingly.

Note that the data position directly read by the CPU is determined in advance, and the circuit is designed so that the status and the like are sent to that range. By doing so, there is no need to read the input register 52 when reading data other than data to be calculated, and the CPU can directly monitor the state of the data calculation unit.

FIG. 12 shows still another modification of the present invention. In each of the embodiments described above, part of the data of the data calculation unit (for example,
6 bits), this can be done by copying the data latched in the input register 52 of the CPU bus interface board 5 to the output register 51. Data also needs to be copied from the input register 52 to the output register 51, and the execution time increases by the copying time of the portion that does not require modification.

FIG. 12 is a diagram showing the configuration of a modified CPU bus interface board that solves this problem. In this modification, the input register 52 and output register 51 in each of the above embodiments are combined into one set of input/output register 55, and data input to this input/output register 55 is input to the selector (MP
X) 56 is configured so that it can be switched from either the CPU section side or the data calculation section side, and thereby the 48-bit data of the data calculation section
This allows for partial correction of each bit.

Note that this modified example includes a data path passing through the buffer (3) and a data path passing through the buffer (7) described above, and are configured to have the functions explained in FIGS. 1O and 13, respectively. .

The functions of each element in FIG. 12 are as follows.

The selector 56 is for selecting data to be latched into the input/output register 55. At the time of write command, eight pieces (
When issuing a read command, select the B side (data of the calculation section).

Buffer (2) is a 3-state buffer, which specifies the CPU interface board 5 with an address and outputs data when a read command is issued.

The buffer (3) is a 3-state buffer, and transfers the data output by the CPU to the lower 16 bits of the arithmetic section bus 11 when a write signal is issued.

Buffers (4) to (6) are 3-state buffers,
When a read signal is issued and the address specifies the CPU interface port 5, one of them opens. The lower bits of the address specify which buffer is opened.

The buffer (7) is a 3-speed data buffer and is opened when a read command is issued and an address other than the CPU interface port 5 is specified.

Buffer (8) is a buffer for current enhancement.

The address data transferred from the CPU section is sent to the arithmetic section. Buffers (9) and (10) are also buffers for increasing current, and read signals transferred from the CPU section,
Sends a write signal to the calculation section.

The input/output register 55 of (3) is a 16-bit latch,
Latch the upper 16 bits of data on the operation unit bus.

The input/output register 55 of (3) is a 16-bit latch,
Latch the 16-bit data in the arithmetic unit bus.

The input/output register 55 of (3) is a 16-bit latch,
Latch the lower 16 bits of data on the operation unit bus.

A summary of the following functions is shown in the truth value table of the CPU interface in FIG. 13, and an explanatory diagram of each function is shown in FIG.

According to this modification of FIG. 12, when a read command is issued specifying a device other than the CP LJ section interface board 5, data is latched in the input/output register 55. The input/output register 55 is also used to send data from the CPtJ section to the data calculation section. When the data in the data calculation section is read, the data is latched into the input/output register 55, so that it is possible to rewrite only the necessary portion of the input/output register 55, eliminating the need for copying.

[Effects of the Invention] According to the present invention, a high-speed arithmetic device having a configuration suitable for executing processing at high speed in a small space is realized.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram according to the present invention, FIG. 2 is a diagram explaining the principle according to the present invention, FIG. 3 is a time chart according to the present invention, and FIG. 4 is a high-speed calculation device as an embodiment of the present invention. FIG. 5 is a block diagram showing an example of the configuration of the CPU bus interface port in FIG. 4. FIGS. 6 and 7 are diagrams explaining the present invention in detail. FIG. Figures illustrating another modification of the invention. Figures 9 and 10 are diagrams illustrating still another modification of the invention in which data can be directly set. FIG. 11 is a diagram illustrating still another modification of the present invention that allows direct reading of data, and FIGS. 12 to 14 are still other modifications of the present invention that allow quick partial correction of data. 15 to 17 are diagrams showing conventional calculation circuits. l...CPU port 2...Memory board 3, 4, 5, 6, 7, 8, 9, 10, 1 l, 51, 52, 55, 56, ROM board, arithmetic unit interface board, CPLI bus Interface board, operation board, register board, 2D ROM board, data input/output interface board, 020 section bus, operation section bus, output register, input register, input/output register, selector

Claims (1)

[Claims] 1. A control unit (21) including a processor (26), and a plurality of functional units (28 (1) each assigned an address.
) to 28(n)) are provided with a calculation unit (22) mutually coupled by a calculation unit bus (24), and the control unit (21) and the calculation unit (22) are connected to each other by an interface unit (23). In response to a first control command issued by the processor (26) by addressing a functional unit of the arithmetic unit (22), the addressed functional unit transfers its own processing data to the arithmetic unit (22). A high-speed arithmetic unit configured to output data to a bus (24) and whose non-addressed functional units take in data on the arithmetic unit bus (24) in order to perform their respective predetermined functions. 2. The high-speed arithmetic device according to claim 1, wherein a plurality of addresses are assigned to one functional unit, and the functional unit is configured to execute a different function for each designated address when addressed. 3. In response to a second control command issued by the processor (26) by addressing a functional unit of the arithmetic unit (22), only the addressed functional unit executes a predetermined function. A high-speed arithmetic device according to claim 1 or 2. 4. In response to a second control command issued by the processor (26) by addressing a functional unit of the arithmetic unit (22), the interface unit (23) processes the data from the control unit (21). Claim 3, wherein at least a part of the calculation unit (22) is placed on the calculation unit bus (24) of the calculation unit (22) as it is.
High-speed arithmetic device described. 5. In response to the first control command issued from the processor (26), the interface unit (23) transfers at least part of the data on the operation unit bus (24) of the operation unit to the control unit ( 5. The high-speed arithmetic device according to claim 1, wherein the high-speed arithmetic device is configured to transfer data to 21). 6. The interface unit (23) switches the input/output register for both input and output and the data input to the input/output register to either data from the control unit (21) or data from the calculation unit (22). 6. The high-speed arithmetic device according to claim 1, further comprising a selector so that part of the data content of the arithmetic unit can be modified on the input/output register.