JPH06130924A - Constitution for fifo synchronizing circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for adding a timing adjusting work regardless of the change of the constitution of unit coupling by providing a delay adjusting circuit which detects the delay or the lead of a data input timing to send a signal for synchronous control to the unit in a next stage. CONSTITUTION:Data outputted from the unit in the next stage are inputted based on the synchronous signal generated by this unit, and data are outputted to the unit in the preceding stage together with the synchronous signal indicating its sending timing. A FIFO part 11 which outputs data inputted from the unit in the next stage in the input order and a delay adjusting circuit 12 which detects the delay or the lead of the timing, at which data are inputted to the FIFO part 11 from the unit in the next stage, to send the signal for synchronous control to the unit in the next stage are provided. Consequently, the delay and the lead of the data input/output timing are decided to automatically adjust the timing, and it is unnecessary to perform adjustment at the time of coupling plural units.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of constructing a synchronizing circuit in an image synthesizing circuit used in a three-dimensional graphic display device.

In a three-dimensional graphic display device, a plurality of three-dimensional frame memories (hereinafter, referred to as 3D-FM) 40, as shown in FIG. 4, in order to display an image at high speed.
To 43, and the image data written in each of the 3D-FMs 40 to 43 may be combined.

The image synthesizing sections 44 to 46 store the image data written in the 3D-FMs 40 to 42 in the same unit,
The image data sent from each unit in the next stage is combined. In addition, the display unit 47 displays and outputs the combined image data.

When image data is transferred between different units, there is a difference between the data input / output timing of one unit and the data input / output timing of another unit due to a clock shift in each unit and a delay in transfer. Occurs. Therefore, it is necessary to synchronize the data input / output timing between the units.

[0005]

2. Description of the Related Art FIG. 5 shows the configuration of a conventional technique. In FIG. 5, the self-stage unit 50 inputs the image data from the next-stage unit and reads the image data to be combined from the 3D-FM. Then, the image data combined by the data processing unit 52 is output to the preceding unit.

Conventionally, as shown in FIG.
By providing the register 51 in the input section of the unit, a fixed delay is applied to the data input timing, and the self-stage unit 5
The data input / output timing deviation between 0 and the next-stage unit was absorbed.

[0007]

However, this conventional method has a problem that the data cannot be processed correctly when the deviation assumed at the time of design and the actual deviation are different. In this case, it is necessary to adjust each unit after the units are combined, and it is necessary to individually form a synchronization circuit for each unit. Also, this adjustment would have to be made each time the number of coupling stages changed.

The present invention has been made in view of the above-mentioned conventional problems, and even if the configuration of unit coupling is changed, it is not necessary to add timing adjustment work between units. It is an object of the present invention to provide a circuit configuration for transmitting and receiving a horizontal sync signal for notifying a data input / output timing and automatically detecting and adjusting a deviation of the horizontal sync signal.

[0009]

According to the invention, the above mentioned objects are achieved by means of the patent claims.

That is, according to the first aspect of the invention, as shown in the principle explanatory diagram of FIG. 1, the data output from the next-stage unit is input based on the synchronization signal created by the next-stage unit, and the data is output to the previous-stage unit. On the other hand, a self-stage unit 1 that outputs data together with a synchronization signal indicating the transmission timing thereof.
At 0, the FIFO unit 11 that outputs the data input from the next-stage unit in the order of input, and the delay or advance of the timing at which the FIFO unit 11 inputs the data from the next-stage unit are detected and And a delay adjustment circuit 12 for transmitting a signal for synchronization control by the FIFO synchronization circuit.

According to a second aspect of the present invention, the FIFO unit includes a plurality of registers for holding data, a write counter indicating a register for writing input data, and a read counter indicating a register for reading output data. In addition to the above, the delay adjustment circuit compares the value of the write counter with the value of the read counter, and if the difference is not within a certain range, the delay adjustment circuit is used for the next-stage unit. And a means for transmitting a signal for synchronous control, which is a structure of a FIFO synchronous circuit.

[0012]

In FIG. 1, a FIFO (first-in first-out memory) unit 11 outputs written data in the written order. The data output timing in the next-stage unit is
0 is determined by the horizontal sync signal sent to the next unit.

The delay adjusting circuit 12 is, for example, a FIF.
When the data is written up to the middle of the O section 11, the FI
The delay of the horizontal synchronizing signal sent to the next-stage unit is changed so that the data output from the FO unit 11 starts. The data processing unit 13 synthesizes image data.

[0014]

FIG. 2 shows the configuration of an embodiment according to the present invention. In FIG. 2, the write counter 22 starts counting up when the horizontal synchronizing signal from the next-stage unit becomes valid. Then, the count value is "(number of FFs)-
When it becomes "1", the count value is returned to "0".
Distributes the input data to the flip-flops 25 to 27 according to the count value of the write counter 22.

The read counter 23 starts counting up when the horizontal synchronizing signal of its own unit becomes valid. Then, when the count value becomes "(number of FFs) -1", the count value is returned to "0". The selector 21 selects the data of each flip-flop 25 to 27 according to the count value of the read counter 23.

The delay adjustment circuit 24 determines the delay or advance of the input data at the head of the scan line, and adjusts the delay of the horizontal synchronizing signal sent to the next stage unit by one cycle.

The delay adjustment may be performed as follows. That is, when the count value of the read counter 23 is “0”, the count value of the write counter 22 is read. If the count value of the write counter 22 is smaller than half of the maximum count value, the delay is decreased by one cycle, and if it is larger, the delay is increased by one cycle. If they are equal, no change is made.

For example, an operation example of the delay adjusting circuit 24 when the number of flip-flops is five will be described with reference to FIG. In the case of FIG. 3A, when the count value of the read counter 23 is “0”, the count value of the write counter 22 is “3”. This "3" is larger than half of "4" which is the maximum count value, that is, "2". Therefore, the delay is reduced by one cycle and the timing is delayed by one cycle.

Further, in the case of FIG. 3B, when the count value of the read counter 23 is "0", the write counter 22
Has a count value of "1", which is smaller than "2". Therefore, the delay is increased by one cycle and the timing is advanced by one cycle.

In both the case of FIG. 3A and the case of FIG. 3B, the timing is corrected in the next scan, and thereafter,
When the read counter 23 has a count value of "0", the write counter 22 has a count value of "2" and is stable.

[0021]

As described above, according to the present invention,
Since it is possible to determine the delay or advance of the data input / output timing and automatically adjust the timing, it is not necessary to make adjustments when connecting a plurality of units. Further, since the synchronization is performed independently in each unit, there is an effect that control through all units is unnecessary.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a timing chart illustrating an operation example of a delay adjustment circuit.

FIG. 4 is a schematic diagram of a three-dimensional graphic display device.

FIG. 5 is a diagram showing a conventional technique.

[Explanation of symbols]

 10, 50 unit 11 FIFO unit 12, 24 Delay adjustment circuit 13, 52 Data processing unit 20 Distributor 21 Selector 22 Write counter 23 Read counter 25-27 Flip-flop 40-43 Three-dimensional frame memory 44-46 Image composition unit 47 Display unit 51 register

Claims (2)

[Claims] 1. The data output from the next-stage unit is input based on a synchronization signal generated by the next-stage unit, and
In the self-stage unit (10) that outputs data to the preceding unit together with a synchronization signal indicating the transmission timing, a FIFO unit (11) that outputs the data input from the succeeding unit in the order of input, and this FIFO unit A delay adjusting circuit (12) for detecting a delay or advance of the timing at which the section (11) inputs data from the next-stage unit and sending a signal for synchronization control to the next-stage unit. FIFO to be
Synchronous circuit configuration. 2. The FIFO unit has a plurality of registers for holding data, a write counter showing a register for writing input data, and a read counter showing a register for reading output data, and the delay adjusting circuit. Is the value of the light counter,
2. The method according to claim 1, further comprising means for comparing the value of the read counter and means for sending a signal for synchronous control to the next-stage unit if the difference is not within a certain range. Configuration of FIFO synchronization circuit.