JPH06130414A - Manufacture of liquid crystal display device - Google Patents
Manufacture of liquid crystal display deviceInfo
- Publication number
- JPH06130414A JPH06130414A JP27610392A JP27610392A JPH06130414A JP H06130414 A JPH06130414 A JP H06130414A JP 27610392 A JP27610392 A JP 27610392A JP 27610392 A JP27610392 A JP 27610392A JP H06130414 A JPH06130414 A JP H06130414A
- Authority
- JP
- Japan
- Prior art keywords
- connection hole
- insulating film
- interlayer insulating
- drain
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は液晶表示装置に関し、特
に、その表示品質の向上技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a technique for improving its display quality.
【０００２】[0002]
【従来の技術】液晶表示装置においては、画素信号を供
給するデ−タ線および走査信号を伝達するゲ−ト線が格
子状に配置されており各画素領域が区画形成された一方
側の透明絶縁基板と共通電極が形成された他方側の透明
絶縁基板との間に液晶が封入されており、共通電極と各
画素領域の画素電極との間に印加される電位を制御し
て、画素領域毎の液晶の配向状態を変化させるようにな
っている。このため、各画素領域から構成されたマトリ
クスアレイの一般的な構造は、垂直方向のデ−タ線と、
水平方向のゲ−ト線とによって区画形成された画素領域
にデ−タ線が導通接続するソ−スおよびゲ−ト線が導通
接続するゲ−トを有するＴＦＴが構成されており、その
ドレインには、それらの表面側に形成されたシリコン酸
化膜からなる層間絶縁膜の接続孔を介して画素電極が導
通接続している。2. Description of the Related Art In a liquid crystal display device, a data line for supplying a pixel signal and a gate line for transmitting a scanning signal are arranged in a grid pattern, and each pixel region is divided and formed on one transparent side. Liquid crystal is enclosed between the insulating substrate and the transparent insulating substrate on the other side where the common electrode is formed, and the potential applied between the common electrode and the pixel electrode of each pixel region is controlled to control the pixel region. The alignment state of the liquid crystal is changed every time. Therefore, the general structure of the matrix array composed of each pixel area is such that the vertical data lines are
A TFT having a source to which a data line is electrically connected and a gate to which a gate line is electrically connected is constructed in a pixel region defined by a horizontal gate line and its drain. The pixel electrodes are electrically connected to each other through the connection holes of the interlayer insulating film made of a silicon oxide film formed on the surface side thereof.
【０００３】従来の液晶表示装置においては、デ−タ線
も画素電極と同一の層間絶縁膜上に形成されて、その接
続孔を介してソ−スに導通接続しているため、デ−タ線
と画素電極とデ−タ線とが短絡しやすい構造である。従
って、それらを絶縁分離しておくためには、画素電極の
端部とデ−タ線との間に所定の間隔を確保する必要があ
り、その間隔に相当して、画素電極の形成領域が狭くな
り、開口率が低減するという問題がある。この問題を解
決する方法として、デ−タ線と画素電極とを異なる絶縁
膜上に形成すれば良い。これは、第１層目の層間絶縁膜
の第１の接続孔を介して導通接続するデ−タ線を形成
し、第１層目の層間絶縁膜の第２の接続孔及び第２層目
の層間絶縁膜の接続孔を介して端部がデ−タ線の上方に
位置する画素電極が導通接続する構造である。従って、
デ−タ線と画素電極とは互いに別層に形成されているた
め短絡する危険性がないので、デ−タ線の上方位置にま
で画素電極の端部を配置することができるため、開口率
が増加し、表示品質が向上する。In the conventional liquid crystal display device, since the data line is also formed on the same interlayer insulating film as the pixel electrode and is electrically connected to the source through the connection hole, the data line is formed. The line, the pixel electrode, and the data line are easily short-circuited. Therefore, in order to insulate them from each other, it is necessary to secure a predetermined interval between the end portion of the pixel electrode and the data line, and the area where the pixel electrode is formed corresponds to the interval. There is a problem that it becomes narrower and the aperture ratio is reduced. As a method of solving this problem, the data line and the pixel electrode may be formed on different insulating films. This forms a data line that is electrically connected through the first connecting hole of the first-layer interlayer insulating film, and the second connecting hole and the second-layer connecting hole of the first-layer interlayer insulating film are formed. The pixel electrode whose end portion is located above the data line is conductively connected through the connection hole of the interlayer insulating film. Therefore,
Since the data line and the pixel electrode are formed in different layers from each other, there is no risk of short-circuiting. Therefore, since the end portion of the pixel electrode can be arranged above the data line, the aperture ratio can be increased. And the display quality is improved.
【０００４】[0004]
【発明が解決しようとする課題】上記構造で第１層目と
第２層目の層間絶縁膜ではエッチングレ−トが異なるた
めウェットエッチングにより接続孔を開口し、直接画素
電極がＴＦＴのドレインと導通接続する場合、各層ごと
にエッチングする必要がある。しかし第１層目の層間絶
縁膜にＴＦＴのソ−ス及びドレインと導通接続するよう
に接続孔を開口した後、デ−タ線（例えばＡｌ）をスパ
ッタ法により形成し、次に第２層目の層間絶縁膜を堆積
した後、第１の層間絶縁膜のドレイン側の接続孔を介し
てＴＦＴのドレインと導通接続するように接続孔を開口
しようとすると、デ−タ線を形成する際のスパッタダメ
−ジにより第１層目と第２層目の層間絶縁膜の密着不良
が発生し、その界面からエッチング液が染み込み第２層
目に開口された接続孔はオ−バ−エッチングされ逆テ−
パ−形状となる。その後その接続孔及び第１層目の層間
絶縁膜のドレイン側に開口された接続孔を介してＴＦＴ
のドレインに導通接続するように透明画素電極（例えば
ＩＴＯ膜）を形成すると、接続孔が逆テ−パ−形状のた
め画素電極が断線し表示欠陥の原因となる。In the above structure, since the first and second interlayer insulating films have different etching rates, the connection hole is opened by wet etching, and the pixel electrode is directly connected to the drain of the TFT. In the case of conductive connection, it is necessary to etch each layer. However, after forming a connection hole in the first interlayer insulating film so as to be conductively connected to the source and drain of the TFT, a data line (for example, Al) is formed by the sputtering method, and then the second layer is formed. After the first interlayer insulating film is deposited, it is attempted to open the connection hole so as to be conductively connected to the drain of the TFT through the connection hole on the drain side of the first interlayer insulating film. Adhesion failure between the first and second interlayer insulating films occurs due to the sputter damage, and the etching solution permeates from the interface, and the connection hole opened in the second layer is over-etched. Reverse test
It becomes a par shape. After that, the TFT is connected through the connection hole and the connection hole opened on the drain side of the first interlayer insulating film.
If a transparent pixel electrode (for example, an ITO film) is formed so as to be conductively connected to the drain of the pixel electrode, the pixel electrode is disconnected because the connection hole has a reverse taper shape, which causes a display defect.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するため
に、本発明の液晶表示装置において講じた手段は、透明
な絶縁基板の表面側に形成されたＴＦＴを有する液晶表
示装置において、前記ＴＦＴのソ−ス及びドレインと導
通接続するための接続孔を第１の層間絶縁膜に開口する
工程と、次に開口された接続孔のうちドレイン側の接続
孔をレジストで覆う工程と、次にそのレジストを２００
℃以上で乾燥する工程と、次にデ−タ線を成膜し接続孔
を介してＴＦＴのソ−スと導通接続するようにパタ−ニ
ングし、ドレイン側の接続孔を覆っていたレジストを剥
離する工程と、次に第２の層間絶縁膜を堆積し第１の層
間絶縁膜の接続孔を介してドレインと導通接続するよう
に前記第２の層間絶縁膜に接続孔を開口する工程と、次
に透明画素電極を成膜し、第１及び第２層間絶縁膜の接
続孔を介してＴＦＴのドレインに導通接続するようにパ
タ−ニングする工程と、を有することである。Means for Solving the Problems In order to solve the above problems, the means taken in the liquid crystal display device of the present invention is the liquid crystal display device having a TFT formed on the surface side of a transparent insulating substrate. Of the first interlayer insulating film, and a step of covering the drain side connection hole of the opened connection holes with a resist. 200 of that resist
A step of drying at a temperature of ℃ or more, and then patterning a data line to form a conductive connection with the source of the TFT through the connection hole, the resist covering the connection hole on the drain side is removed. And a step of depositing a second interlayer insulating film and opening a connection hole in the second interlayer insulating film so as to be conductively connected to the drain through the connection hole of the first interlayer insulating film. Next, a step of forming a transparent pixel electrode and patterning it so as to be conductively connected to the drain of the TFT through the connection hole of the first and second interlayer insulating films.
【０００６】[0006]
【作用】本発明の液晶表示装置の製造方法において、第
１層目の層間絶縁膜上にデ−タ線をスパッタ法で形成す
る際、ドレイン側の接続孔はレジストで覆われているた
めスパッタダメ−ジをうけない。よって第２層目の層間
絶縁膜との密着不良は発生しないため第２層目の層間絶
縁膜に開口された接続孔は逆テ−パ−形状にはならず画
素電極の断線も発生しないので表示品質向上が可能であ
る。In the method of manufacturing a liquid crystal display device according to the present invention, when the data line is formed on the first interlayer insulating film by the sputtering method, the drain side connection hole is covered with the resist and thus the sputtering is performed. I don't get any damage. Therefore, since the adhesion failure with the second-layer interlayer insulating film does not occur, the connection hole opened in the second-layer interlayer insulating film does not have an inverted taper shape and the disconnection of the pixel electrode does not occur. The display quality can be improved.
【０００７】[0007]
【実施例】次に本発明の一実施例について添付図面を参
照して説明する。図１は本発明の実施例の製造方法を適
用した液晶表示装置における画素領域の構造断面図を工
程ごとに示したものである。An embodiment of the present invention will now be described with reference to the accompanying drawings. FIG. 1 is a structural cross-sectional view of a pixel region in a liquid crystal display device to which a manufacturing method according to an embodiment of the present invention is applied.
【０００８】この画素領域には、デ−タ線１４が導通接
続するソ−ス２、ゲ−ト線が導通接続するゲ−ト７、お
よび画素電極１６が導通接続するドレイン３によって、
ＴＦＴ８が形成されている。このＴＦＴの断面構造は、
液晶表示装置全体を支持する絶縁透明基板１の表面側に
ＳｉＨ4ガスを600℃程度で熱分解させ、減圧下での化学
気相成長法（以下ＣＶＤ法と略す）により多結晶シリコ
ン層４を1000Å程度堆積した後所定の形状にパタ−ニン
グし、次にこの多結晶シリコン層４の表面を1000〜1200
℃で熱酸化することによりゲ−ト酸化膜６を1200Å程度
堆積する。このとき多結晶シリコン層４は熱酸化により
反応するため膜厚は500Å程度となる。この多結晶シリコ
ンには、真性の多結晶シリコン領域であるチャネル領域
５を除いて、ｎ型の不純物としてリンが導入されて（ｐ
型を形成する場合はボロン）、ソ−ス２およびドレイン
３が形成されている。ここでリンの導入は、多結晶シリ
コン層４の表面側に形成されたゲ−ト酸化膜６上のゲ−
ト７をマスクとするイオン注入を利用することにより、
ソ−ス２およびドレイン３がセルフアラインとなるよう
に行われる。ここでゲ−ト７は多結晶シリコン膜を3000
〜4000Å堆積した後、この多結晶シリコン膜中に酸素及
び窒素雰囲気中でオキシ塩化リン（ＰＯＣｌ3）を用い9
00〜1000℃でリンを熱拡散するかあるいは、同等量のリ
ンをイオン打ち込みにより注入し、所定の形状にパタ−
ニングして形成する。このＴＦＴ８の表面側には、シリ
コン酸化膜からなる第１の層間絶縁膜９がＳｉＨ4系あ
るいはＴＥＯＳ系のガスを用い、常圧ＣＶＤ法あるいは
減圧ＣＶＤ法により8000〜10000Å程度堆積されてお
り、それには第１の接続孔１１と第２の接続孔１２とが
それぞれＴＦＴ８のソ−ス及びドレインと導通接続する
ように開口されている（ａ）。次にそのうちの第２の接
続孔１２のみをレジスト１３で覆った後、窒素雰囲気中
で２００℃〜３００℃で加熱し乾燥させる（ｂ）。そし
てスパッタ法によりデ−タ線となるアルミニウムを8000
〜10000Å程度堆積し、第１の接続孔を介して、このアル
ミニウムがソ−ス２に導通接続するようにパタ−ニング
してデ−タ線１４を形成する（ｃ）。このとき、第２の
接続孔１２のみをレジストで覆う場合のフォトマスクは
第２の接続孔１２のみがレジスト覆われ、かつデ−タ線
がレジストで覆われないパタ−ンであれば良いから画素
電極を形成するフォトマスクを共用して用いれば良い。
あるいは画素電極の周囲に不透明金属膜でブラックマト
リクスを形成する構造の場合には、そのブラックマトリ
クスを形成する際のフォトマスクでレジストの極性を反
転させて用いても良い。つまりブラックマトリクスをパ
タ−ニングする際にポジレジストを用いたならばネガレ
ジスト、逆にブラックマトリクス形成時にネガレジスト
を用いたならばポジレジストを用いることによりドレイ
ン側の接続孔のみをレジストで覆うことができる。次に
その上層に第２の層間絶縁膜１０が第１の層間絶縁膜９
と同様にＳｉＨ4系あるいはＴＥＯＳ系のガスを用い、常
圧ＣＶＤ法あるいは減圧ＣＶＤ法により8000〜10000Å
程度堆積されており、接続孔１５を第１の層間絶縁膜の
第２の接続孔１２を介してドレイン３に導通接続される
ように開孔した後、画素電極１６となるＩＴＯ膜をスパ
ッタ法により1000Å〜2000Å堆積し、接続孔１５と第１
の層間絶縁膜の第２の接続孔１２を介してドレイン３に
導通接続され、画素電極の端部がデ−タ線の上方位置に
配置されるようにパタ−ニングして形成し完成する
（ｄ）。本実施例では画素電極にスパッタによるＩＴＯ
膜を用いたが、金属インジウムあるいはインジウム−ス
ズ合金をスパッタ法、蒸着法またはＣＶＤ法により堆積
した後、３００℃〜５００℃で酸素雰囲気あるいは空気
中においてドライ酸化または水蒸気を用いたウェット酸
化を行うことにより、画素電極を形成しても良い。In this pixel region, a source 2 to which a data line 14 is conductively connected, a gate 7 to which a gate line is conductively connected, and a drain 3 to which a pixel electrode 16 is conductively connected are formed.
The TFT 8 is formed. The cross-sectional structure of this TFT is
SiH 4 gas is thermally decomposed at about 600 ° C. on the surface side of the insulating transparent substrate 1 supporting the entire liquid crystal display device, and the polycrystalline silicon layer 4 is formed by chemical vapor deposition (hereinafter abbreviated as CVD method) under reduced pressure. After depositing about 1000Å, it is patterned into a predetermined shape, and then the surface of this polycrystalline silicon layer 4 is 1000-1200.
The gate oxide film 6 is deposited at about 1200 Å by thermal oxidation at ℃. At this time, since the polycrystalline silicon layer 4 reacts by thermal oxidation, the film thickness becomes about 500Å. Except for the channel region 5 which is an intrinsic polycrystalline silicon region, phosphorus is introduced into this polycrystalline silicon as an n-type impurity (p
In the case of forming a mold, boron), a source 2 and a drain 3 are formed. Here, the introduction of phosphorus means that the gate is formed on the gate oxide film 6 formed on the surface side of the polycrystalline silicon layer 4.
By using ion implantation with mask 7 as a mask,
The source 2 and the drain 3 are self-aligned. Here, the gate 7 is a polycrystalline silicon film 3000
~ 4000 Å After depositing, use phosphorus oxychloride (POCl 3 ) in this polycrystalline silicon film in an atmosphere of oxygen and nitrogen.
Phosphorus is thermally diffused at 100 to 1000 ° C, or an equal amount of phosphorus is ion-implanted and patterned into a predetermined shape.
To form. A first interlayer insulating film 9 made of a silicon oxide film is deposited on the surface side of the TFT 8 using SiH 4 system gas or TEOS system gas by atmospheric pressure CVD method or low pressure CVD method to about 8000 to 10000Å. The first connection hole 11 and the second connection hole 12 are opened in it so as to be conductively connected to the source and the drain of the TFT 8, respectively (a). Next, after covering only the second connection hole 12 among them with the resist 13, it is heated at 200 ° C. to 300 ° C. in a nitrogen atmosphere and dried (b). Then, the aluminum to be the data line is sputtered by 8000
About 10000 Å is deposited, and the aluminum is conductively connected to the source 2 through the first connection hole to form a data line 14 (c). At this time, the photomask for covering only the second connection holes 12 with a resist may be a pattern in which only the second connection holes 12 are covered with the resist and the data lines are not covered with the resist. The photomask for forming the pixel electrode may be shared and used.
Alternatively, in the case of a structure in which a black matrix is formed around the pixel electrode with an opaque metal film, the polarities of the resist may be inverted with a photomask used for forming the black matrix. That is, if a positive resist is used when patterning the black matrix, a negative resist is used. Conversely, if a negative resist is used when forming the black matrix, a positive resist is used to cover only the drain-side connection hole with the resist. You can Then, a second interlayer insulating film 10 is formed on the first interlayer insulating film 9 as an upper layer.
Similar to the above, using SiH 4 system gas or TEOS system gas, by normal pressure CVD method or low pressure CVD method, 8000 to 10000Å
After the connection hole 15 is opened to be conductively connected to the drain 3 through the second connection hole 12 of the first interlayer insulating film, the ITO film to be the pixel electrode 16 is sputtered. 1000 Å ~ 2000 Å due to the connection hole 15 and the first
Is electrically connected to the drain 3 through the second connection hole 12 of the interlayer insulating film, and is formed by patterning so that the end portion of the pixel electrode is located above the data line to complete ( d). In this embodiment, the pixel electrode is formed by sputtering ITO.
Although a film was used, after metal indium or indium-tin alloy is deposited by a sputtering method, an evaporation method or a CVD method, dry oxidation or wet oxidation using water vapor is performed in an oxygen atmosphere or in air at 300 ° C to 500 ° C. Accordingly, the pixel electrode may be formed.
【０００９】従って、本液晶表示装置において、デ−タ
線形成時にドレイン側の接続孔はレジストで覆われてい
るため第１層間絶縁膜へのスパッタダメ−ジはなく接続
孔の形状異常を防止することができるため画素電極の断
線が防止でき表示品質および歩留りを向上させることが
可能である。Therefore, in the present liquid crystal display device, since the connection hole on the drain side is covered with the resist at the time of forming the data line, there is no sputter damage to the first interlayer insulating film and the shape abnormality of the connection hole is prevented. Therefore, disconnection of the pixel electrode can be prevented, and display quality and yield can be improved.
【００１０】[0010]
【発明の効果】本発明の液晶表示装置の製造方法におい
て前記のとおり、デ−タ線形成時にドレイン側の接続孔
をレジストで覆うことに特徴を有するので、以下の効果
を奏する。As described above, the method of manufacturing a liquid crystal display device of the present invention is characterized in that the drain side connection hole is covered with a resist when forming the data line, and therefore the following effects are obtained.
【００１１】デ−タ線形成時にドレイン側の接続孔が
レジストで覆われているため、第１層間絶縁膜へのスパ
ッタダメ−ジが軽減され第２層間絶縁膜に接続孔を開口
した時に第１及び第２層間絶縁膜の界面でのオ−バエッ
チングは発生しない。そのため接続孔は逆テ−パ−形状
にならず、画素電極の断線が防止されるため表示品質及
び歩留まりが向上する。Since the connection hole on the drain side is covered with the resist at the time of forming the data line, sputter damage to the first interlayer insulating film is reduced, and when the connection hole is opened in the second interlayer insulating film. Over-etching does not occur at the interface between the first and second interlayer insulating films. Therefore, the connection hole does not have a reverse taper shape, and the disconnection of the pixel electrode is prevented, so that the display quality and the yield are improved.
【００１２】ドレイン側の接続孔をレジストで覆う場
合のフォトマスクは画素電極のフォトマスクと共用で
き、あるいは画素電極の周囲にブラックマトリクスを形
成する場合はそのブラックマトリクスのフォトマスクと
も共用して使用できるため、この工程専用に新規にフォ
トマスクを作成する必要はない。The photomask for covering the drain side connection hole with a resist can be used also as the photomask for the pixel electrode, or when the black matrix is formed around the pixel electrode, it can also be used as the photomask for the black matrix. Therefore, it is not necessary to create a new photomask exclusively for this step.
【図１】本発明の一実施例を説明する図。 （ａ）第１層目の層間絶縁膜にＴＦＴのソ−ス及びドレ
インと導通接続するように接続孔を開口した図。 （ｂ）開口された接続孔のうちドレイン側の接続孔のみ
をレジストで覆った図。 （ｃ）ドレイン側の接続孔はレジストで覆われたままで
デ−タ線を形成した図。 （ｄ）完成図。FIG. 1 is a diagram illustrating an embodiment of the present invention. (A) The figure which opened the connection hole so that it may electrically connect with the source and drain of TFT in the first interlayer insulating film. (B) The figure which covered only the connection hole by the side of the drain among the contact holes opened. (C) A diagram in which a data line is formed while the connection hole on the drain side is still covered with resist. (D) Completion drawing.
【符号の説明】 １ 透明絶縁基板 ２ ソ−ス ３ ドレイン ４ 多結晶シリコン膜 ５ チャネル ６ ゲ−ト酸化膜 ７ ゲ−ト電極 ８ ＴＦＴ ９ 第１層目の層間絶縁膜 １０ 第２層目の層間絶縁膜 １１ 接続孔１ １２ 接続孔２ １３ レジスト １４ デ−タ線 １５ 接続孔 １６ 画素電極[Explanation of symbols] 1 transparent insulating substrate 2 source 3 drain 4 polycrystalline silicon film 5 channel 6 gate oxide film 7 gate electrode 8 TFT 9 first layer interlayer insulating film 10 second layer Interlayer insulating film 11 Connection hole 1 12 Connection hole 2 13 Resist 14 Data line 15 Connection hole 16 Pixel electrode
Claims (3)
トランジスタ（以下ＴＦＴと略す）を有する液晶表示装
置において、前記ＴＦＴのソ−ス及びドレインと導通接
続するための接続孔を第１の層間絶縁膜に開口する工程
と、次に開口された接続孔のうちドレイン側の接続孔を
レジストで覆う工程と、次にそのレジストを２００℃以
上で乾燥する工程と、次にデ−タ線を成膜し接続孔を介
してＴＦＴのソ−スと導通接続するようにパタ−ニング
し、ドレイン側の接続孔を覆っていたレジストを剥離す
る工程と、次に第２の層間絶縁膜を堆積し第１の層間絶
縁膜の接続孔を介してドレインと導通接続するように前
記第２の層間絶縁膜に接続孔を開口する工程と、次に透
明画素電極を成膜し、第１及び第２層間絶縁膜の接続孔
を介してＴＦＴのドレインに導通接続するようにパタ−
ニングする工程と、を有することを特徴とする液晶表示
装置の製造方法。1. A liquid crystal display device having a thin film transistor (hereinafter abbreviated as TFT) formed on the surface side of a transparent insulating substrate, wherein a first connection hole is provided for electrically connecting to a source and a drain of the TFT. A step of forming an opening in the interlayer insulating film, a step of covering the connection hole on the drain side of the connection hole that is opened next with a resist, a step of drying the resist at 200 ° C. or higher, and then a data line. And patterning so as to make conductive connection with the source of the TFT through the connection hole, and peeling off the resist covering the connection hole on the drain side, and then forming the second interlayer insulating film. A step of depositing and opening a connection hole in the second interlayer insulating film so as to be conductively connected to the drain through the connection hole of the first interlayer insulating film; Of the TFT through the connection hole of the second interlayer insulating film. Pattern so as to conductively connected to rain -
A manufacturing method of a liquid crystal display device, comprising:
覆うレジストのパタ−ンは画素電極と同一のフォトマス
クを使用することによってパタ−ニングされることを特
徴とする液晶表示装置の製造方法。2. A liquid crystal display device according to claim 1, wherein the pattern of the resist covering the drain side connection hole is patterned by using the same photomask as the pixel electrode. Method.
画素電極の周囲に形成する場合、ドレイン側の接続孔を
覆うレジストのパタ−ンはブラックマトリクスを形成す
る際のレジストとは反対の極性のレジストを用い、ブラ
ックマトリクスと同一のフォトマスクを使用することに
よってパタ−ニングされることを特徴とする液晶表示装
置の製造方法。3. When the black matrix is formed around the pixel electrode according to claim 1, the pattern of the resist covering the connection hole on the drain side has a polarity opposite to that of the resist used when forming the black matrix. A method for manufacturing a liquid crystal display device, characterized in that the patterning is performed by using the same photomask as the black matrix.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27610392A JP3127615B2 (en) | 1992-10-14 | 1992-10-14 | Liquid crystal device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27610392A JP3127615B2 (en) | 1992-10-14 | 1992-10-14 | Liquid crystal device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06130414A true JPH06130414A (en) | 1994-05-13 |
| JP3127615B2 JP3127615B2 (en) | 2001-01-29 |
Family
ID=17564847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27610392A Expired - Lifetime JP3127615B2 (en) | 1992-10-14 | 1992-10-14 | Liquid crystal device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3127615B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7517738B2 (en) | 1995-01-17 | 2009-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor |
| US8835271B2 (en) | 2002-04-09 | 2014-09-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor display device |
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-
1992
- 1992-10-14 JP JP27610392A patent/JP3127615B2/en not_active Expired - Lifetime
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|---|---|---|---|---|
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| US9406806B2 (en) | 2002-04-09 | 2016-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and display device using the same |
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Also Published As
| Publication number | Publication date |
|---|---|
| JP3127615B2 (en) | 2001-01-29 |
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