JPH0612881A - Driving method for semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a electrode common to respective memory cells and to attain high integration of the device by driving the device while always setting the voltage of the electrode of the ferroelectric capacitor placed on the opposite side of an FET of the respective memory cells to be Vp. CONSTITUTION:The electrode of a ferroelectric capacitor Cf of each memory cell placed opposite to an electrode connected to an FET 11 is connected to a common plate electrode 21 and the voltage of the electrode 21 is always set to be Vp. Writing of information on a memory cell is performed by setting the voltage of a word line 13 of the FET 11 of the relevant memory cell to be Vcc so that the FET 11 is turned on and changing the voltage of a bit line 15 to a prescribed voltage in this ON state. Reading of information is performed after changing the voltage of the bit line 15 of the relevant memory cell to a prescribed voltage for a fixed time, by floating the voltage and turning on the FET. Consequently, the electrodes of the respective memory cells are made to be a common electrode and the high integration is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a semiconductor memory device in which each memory cell has a capacitor made of a ferroelectric thin film.

[0002]

2. Description of the Related Art An example of a semiconductor memory device having a large number of memory cells and each memory cell having a ferroelectric capacitor is disclosed in, for example, the literature (Material Research).
Society Symposium Proceedings (Mat.Re
s.Soc.Symp.Proc.) Vol.200 (1990) pp.303-312). FIG. 4 is a circuit configuration diagram of one memory cell portion of this semiconductor memory device.

In this semiconductor memory device, each memory cell has a capacitor C _{f having} a structure in which a ferroelectric thin film is sandwiched by electrodes.
And a MOS field effect transistor 11 in which one of the source and the drain is connected to one electrode of the capacitor C _f . The word line 13 is connected to the gate electrode of the field effect transistor of each memory cell, the bit line 15 is connected to the other of the source and the drain, and further connected to the field effect transistor 11 of the capacitor C _f. The drive line 17 is connected to the electrode (the other electrode) on the opposite side to the open side. In FIG. 4, C _B represents the stray capacitance of the bit line. In this semiconductor memory device, the ferroelectric capacitor C _f is polarized to obtain a memory state of “1” or “0” depending on its sign.

In order to form such a storage state and read out the storage state, this semiconductor storage device has been driven as described below. 5, 6 and 7 are diagrams provided for the description. Here, FIG. 5A shows a case where “1” is written in the memory cell and FIG. 5B shows a case where a signal supplied to each part of the circuit in FIG. 4 is written “0”. It shows the timing and size. In addition, FIGS. 6A and 6B show signals supplied to or generated in each portion of the circuit in FIG. 4 when the information (“1” or “0”) stored in the memory cell is read to the outside. It shows the timing and size. Also,
FIG. 7 is a diagram (hysteresis curve) showing the relationship between the voltage applied to the ferroelectric capacitor C _f and the resulting polarization.

First, when writing "1" to the memory cell, the voltage V is applied to the word line 13 as shown in FIG.
_A positive pulse V _b is applied to the bit line 15 while _W is applied to make the field effect transistor 11 conductive and 0 V is applied to the drive line 17. In response to this positive pulse V _b , the polarization of C _f changes along the hysteresis curve shown in FIG. 6, and when V _b = 0, it comes to the point (2) in the hysteresis and −P _R of It becomes a value. In addition, when writing “0” to the memory cell, FIG.
As shown in FIG. 5, a positive pulse V _d is applied to the drive line 17 with the voltage V _W applied to the word line 13 to make the field effect transistor 15 conductive and OV applied to the bit line 15. To do. The polarization of the capacitor C _f changes according to the pulse V _d along the hysteresis curve of FIG. 7 and reaches the value of P _R at the point (1) in the hysteresis. The polarization state thus formed in the capacitor C _f causes rewriting to this memory cell, or
Unless the information in this memory cell is read out, it is held for a long time.

On the other hand, when reading information from the memory cell, as shown in FIG. 6A or 6B, the word line 1
The voltage V _d is applied to the drive line 17 in a state where the voltage V _W is applied to the field effect transistor 11 to make the field effect transistor 11 conductive. At this time, when the polarization of the capacitor C _f corresponds to the state in which the above “1” is written, the polarization is (2) →
Since (3) → (1), the stray capacitance C _b of the bit line in FIG. 4 is charged with 2P _r . Further, when the polarization of the capacitor C _f corresponds to the state in which the above “0” is written, the polarization changes along the hysteresis curve of FIG. 7 as (1) → (3) → (1). Therefore, the stray capacitance C _b of the bit line in FIG. 4 is charged with 0 charges. When the stray capacitance C _b is charged with 2P _{r and} the charge of 0 is charged, the voltage of the bit line becomes different, so that the storage state of the memory cell is “1”.
I was able to read out whether it was "0".

[0007]

However, in the conventional method of driving a semiconductor memory device, it is necessary to apply a pulse to the drive line 17 of each memory cell at the timing thereof during writing / reading. Therefore, since writing and reading must be performed simultaneously for all memory cells connected to one drive line, there is a problem that a so-called random access operation for individually accessing each memory cell cannot be performed. .

Further, since it is necessary to provide at least the same number of drive lines as the number of word lines, the normal DRA
There is also a problem that the required area per memory cell is increased as compared with M.

The present invention has been made in view of the above circumstances. Therefore, an object of the present invention is to enable random access to a semiconductor memory device having a capacitor using a ferroelectric thin film and the required number of drive lines. It is an object of the present invention to provide a driving method capable of reducing the above-mentioned problem.

[0010]

To achieve this object, according to the present invention, a capacitor having a structure in which a ferroelectric thin film is sandwiched between electrodes, and one of the source and the drain is provided on one electrode of the capacitor. A plurality of memory cells each including a field effect transistor connected to each other are provided, and a word line is connected to a gate electrode of the field effect transistor of each memory cell, and a bit line is connected to the other of the source and the drain. When driving the connected semiconductor memory device, the voltage of the other electrode of the capacitor of each memory cell is set to a certain value V _p, and the voltage of the bit line is usually set to the above-mentioned voltage V _p to write information to the memory cell. is either V ₁ is again changed to V _p the voltage of the bit line from V _p in the on state to turn on the field effect transistor of the relevant memory cell or V _p Performed by varying Luo V ₂ again V _p, information read from the memory cell, the voltage of the bit line of the corresponding memory cell by a predetermined time change from V _p to V _3, then the bit line is floating Further, the field effect transistor of the memory cell is turned on. However, V ₁
> V _p > V ₂ , and when the coercive voltage of the ferroelectric material used is V _C , V ₃ is V _p > V ₃ and V _p −V _C > V
It is a voltage that satisfies ₃ .

Here, a certain voltage V _p is, for example, V _CC / 2
Can be However, V _CC is the supply voltage to this semiconductor memory device. Also, the fixed time of changing for a fixed time is
It means the time required to discharge the electric charge accumulated in the bit line.

[0012]

According to the structure of the present invention, the voltage of each electrode (the other electrode) on the side opposite to the electrode connected to the field effect transistor of the ferroelectric capacitor of each memory cell is always V _p . To do. This is because the other electrodes of each memory cell can be connected to each other to form a common electrode (because it is not necessary to prepare a drive line for each memory cell), so that the semiconductor memory device can be highly integrated as compared with the conventional configuration. Can be achieved.

Further, the field effect transistor of the memory cell is turned on, and the voltage of the bit line is set to V _p in this on state.
When → V ₁ → V _p (where V _p <V ₁ ) is established, between the electrodes of the ferroelectric capacitor, the polarity of the electrode on the side of the field effect transistor is positive and V ₁ -V _p When a large voltage is applied and the voltage of the bit line is changed to V _p → V ₂ → V _p (where V _p > V ₂ ) when the field effect transistor is in the on state, the voltage between both electrodes of the ferroelectric capacitor is increased. , the magnitude voltage polarity is and V _p -V ₂ to its field effect transistor side of the electrode and the negative is applied. For this reason, polarization corresponding to these polarities occurs in the ferroelectric capacitor, so that the "1" state or the "0" state can be formed in this memory cell (information can be written).

In reading information from the memory cell, first, the voltage of the bit line of the memory cell is changed from V _p to a predetermined voltage V ₃ for a certain period of time. As a result, when the charge is accumulated in the floating capacitance of the bit line, it is discharged. Then, the bit line is floated (open state) and the field effect transistor of the memory cell is turned on. By turning on the field effect transistor in this way, the ferroelectric capacitor and the bit line are connected, and the stray capacitance of the bit line responds to the polarization of the ferroelectric capacitor (the storage state "1" or "of the memory cell"). 0 ”
(According to) and a voltage corresponding to the storage state "1" or "0" is generated on this bit line. Information can be read by measuring this voltage.

Further, since the information writing and the information reading as described above can be performed only by applying the pulse to the word line and the bit line, in the present invention, the information writing to the memory cell and the information reading from the memory cell are performed. It can be done in cell units.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for driving a semiconductor memory device according to the present invention will be described below with reference to the drawings. However, the drawings used for the description are only schematically shown so that the present invention can be understood.

FIG. 1 is a circuit diagram showing an example of a semiconductor memory device driven by the driving method of the present invention with respect to one memory cell portion thereof. The basic configuration of this semiconductor memory device is the same as that described with reference to FIG. The structural difference from the conventional one is the electrode on the side opposite to the electrode connected to the field effect transistor 11 of the ferroelectric capacitor C _f of each memory cell (this is referred to as “the other electrode”).
Is connected to a common electrode 21 (hereinafter referred to as "plate electrode 21").

In the driving method of the present invention, the plate electrode 2
The voltage of 1 is always V _p (V _p = V _CC / in this embodiment)
2. ). Therefore, in the conventional driving method described with reference to FIGS. 4 to 6, it is necessary to apply the voltage pulse independently to the other electrode of the capacitor C _f of each memory cell, but this is necessary in the present invention. Disappear. That is,
This semiconductor memory device has the same configuration as a normal DRAM except that the cell capacitor of each memory cell uses a ferroelectric thin film.

Also in this semiconductor memory device, the memory state is "1".
And “0” are formed by utilizing the polarization of the ferroelectric capacitor C _f , as in the conventional device described with reference to FIG. However, in order to form these memory states and to read these memory states to the outside, in the present invention, the semiconductor memory device shown in FIG. 1 is driven as follows. 2 (A) to (D) and FIG. 3 are diagrams provided for the description. Here, FIG. 2A shows a case where “1” is written in the memory cell and FIG. 2B shows a case where “0” is written in the memory cell. It shows the timing and size. Also,
2C and 2D show timings of signals supplied to or generated in each portion of the circuit in FIG. 1 when information (“1” or “0”) stored in a memory cell is read to the outside. It shows the size. FIG. 3 is a diagram (hysteresis curve) showing the relationship between the voltage applied to the ferroelectric capacitor C _f and the polarization generated thereby, in the ferroelectric capacitor C _f .

According to the driving method of the present invention, when writing "1" to a memory cell, as shown in FIG. 2A, the voltage V _W of the word line of the field effect transistor of the corresponding memory cell is set to V _CC . Te this transistor is turned on, pulsing V _b that varies the bit line 15 in the on state from the voltage V _p V ₁ (which is in this case V ₁ = V _CC.) again V _p. Therefore, the voltage across the capacitor C _f is 0 → −V in response to the pulse V _b.
CC / 2 → 0 changes (the difference between V _p and V _b is the capacitor C
_This is because it _depends on _f . ), The polarization of the capacitor C _f changes along the hysteresis curve shown in FIG. 3 and finally settles at −P _r . In addition, when writing “0” to the memory cell, as shown in FIG.
The word line voltage V _W of the field effect transistor of the corresponding memory cell is set to V _CC to turn on this transistor,
This and the voltage on the bit line 15 in the ON state (has this case V ₂ = 0.) V ₂ from V _p pulsing V _b that varies again V _p. Therefore, the voltage across the capacitor C _f is 0 → V _CC in accordance with the pulse V _b.
Since it changes from / 2 to 0, the polarization of the capacitor C _f changes along the hysteresis curve shown in FIG. 3 and finally settles at P _r .

On the other hand, when the information in the memory cell is read to the outside, as shown in FIG. 2C or 2D, the voltage of the bit line 15 of the corresponding memory cell is changed from V _p to V ₃ (this implementation). In the example, V ₃ = 0) is changed for a certain time T, and then the bit line 15 is set to a floating (open state) and the voltage V of the word line of the memory cell is changed.
_{W is set} to V _CC to turn on the field effect transistor. Since the field effect transistor is turned on, the ferroelectric capacitor C _f and the bit line 15 are connected to each other, so that the stray capacitance C _B of the bit line 15 is charged according to the polarization of the capacitor C _f , that is, the above-mentioned “1”. Alternatively, the electric charge corresponding to the state in which "0" is written is charged. As a result, the voltage of the bit line becomes the voltage corresponding to the storage state "1" or "0". The information in the memory cell can be read by measuring this voltage.

The voltage of this bit line is estimated as follows. The capacitance of the capacitor C _{f in} the state (1) of FIG.
₁ and the capacitance of the capacitor C _{f in} the state (2) of FIG. 3 is C ₂ , these are C ₁ = 2 (P _sat −P _r ) /
V _CC or C ₁ ≈2 (P _sat −P _r ) / V _CC , and C ₂ =
2 (P _sat + P _r ) / V _CC or C ₁ ≈2 (P _sat + P
_r ) / V _CC respectively. Therefore, the voltage read through the bit line 15 when the storage state of the capacitor C _f is “0” is 2C ₁ / (C ₁ + C
_B ) · V _CC , and the storage state of the capacitor C _f is “1”
In this case, the voltage read via the bit line 15 is 2C.
₂ / (C ₂ + C _B ) · V _CC . By selecting the ferroelectric material forming the capacitor C _f , C ₁ <<
Since it is possible to make C _B << C ₂ ,
By doing so, the voltage of the bit line 15 in the memory state “0” becomes ˜0 V, and the bit line 15 in the memory state “1” becomes.
The voltage can also be a ~V _CC / 2.

After the information is read in this way, if the information write pulse described with reference to FIG. 2A or 2B is applied to this semiconductor memory device, the information can be written again. it can.

In the above embodiment, V _p = V _CC /
2, V ₁ = V _CC , V ₂ = V ₃ = 0, and the voltage for turning on the field effect transistor was V _CC , but these values can be changed to other suitable values.

[0025]

As is apparent from the above description, according to the present invention, the electrode of the ferroelectric capacitor of each memory cell on the side opposite to the electrode connected to the field effect transistor (the other electrode) ) Since the semiconductor memory device is driven with each voltage always set to V _p , the other electrodes of each memory cell can be connected to form a common electrode. Therefore, a drive line is prepared for each memory cell. The semiconductor memory device can be highly integrated as compared with the conventional configuration.

Further, since information can be written in and read from the memory cell only by applying a pulse signal to the bit line and word line, a semiconductor memory device using a ferroelectric capacitor can be used as a memory cell. Each can be randomly accessed.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of a semiconductor memory device driven by a driving method according to an embodiment.

2A to 2D are diagrams for explaining a driving method according to an embodiment.

FIG. 3 is a diagram showing a hysteresis curve of a ferroelectric capacitor.

FIG. 4 is a diagram for explaining a conventional technique.

5A and 5B are signal waveform diagrams in a write mode in a conventional driving method.

6A and 6B are signal waveform diagrams in a read mode in a conventional driving method.

FIG. 7 is a diagram for explaining a conventional technique.

[Explanation of symbols]

C _f : Ferroelectric capacitor 11: MOS field effect transistor 13: Word line 15: Bit line 21: Plate electrode C _B : Bit line stray capacitance

Claims (1)

[Claims] 1. A memory cell comprising a capacitor having a structure in which a ferroelectric thin film is sandwiched between electrodes, and a field effect transistor in which one of a source and a drain is connected to one electrode of the capacitor. In driving the semiconductor memory device in which the word line is connected to the gate electrode of the field effect transistor of each memory cell and the bit line is connected to the other of the source and the drain, the other of the capacitors of each memory cell is driven. The voltage of the electrode of the memory cell is set to a certain value V _p, and the voltage of the bit line is normally set to V _{p as} well. To write information in a memory cell, the field effect transistor of the corresponding memory cell is turned on and the voltage of the bit line is the performed by changing from or V _p V ₁ is again changed to V _p from V _p V ₂ again V _p, the information from the memory cell Out is seen, varied predetermined time V ₃ the voltage of the bit line of the corresponding memory cell from V _p,
After that, the bit line is made floating and the field effect transistor of the memory cell is turned on to perform the driving method of the semiconductor memory device (provided that V ₁ > V _p > V ₂ and used. When the coercive voltage of the ferroelectric substance is V _C , V ₃ is V _p > V ₃ and V _p −
The voltage satisfies V _C > V ₃ . ).