JPH0612817B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device forming a gate turn-off thyristor (referred to as GTO).

[Technical background of the invention and its problems]

As is well known, a GTO is a thyristor that is turned on by forward biasing the gate and cathode and turned off by applying a reverse bias. Figure 1 shows the structure of a conventional GTO. This GTO includes a P-type anode emitter P ₁ , an N-type anode base H ₁ , a P-type cathode base P ₂ , and an N-type cathode emitter N _2.
The anode emitter has an anode electrode A, the cathode emitter has a cathode electrode K, and the cathode base has a gate electrode G surrounding the cathode emitter.
Is provided.

Figure 2 shows a conventional GTO with an amplification gate structure. This has an N-type auxiliary cathode emitter N ₃ in addition to the above structure, on which an electrode 1 is provided so as to perform an amplifying action,
Depending on the case, the diode 2 is connected between the electrode and the gate electrode G.

FIG. 3A shows a conventional thyristor having a vertical structure and a MOS gate structure. In the figure, 11 is an insulating layer and 12 is a metal layer. FIG. 3B shows a conventional thyristor having a MOS gate structure having a horizontal structure.

However, in the conventional GTO, in order to obtain a good turn-off characteristic as shown in FIG. 1, the gate electrode is formed so as to surround the cathode emitter N ₂ , and therefore the minimum gate trigger current is 1 A in the large capacity GTO. Also,
To obtain good turn-on characteristics, it is necessary to supply a gate current near 10A. In order to avoid this drawback, an amplification gate structure as shown in Fig. 2 has been devised, but the minimum gate trigger current is still several hundred mA, and a gate current of several amperes must be supplied to obtain good turn-on characteristics. There is a need to. At the time of turn-off, the reverse bias applied between the P ₂ and N ₃ junctions is small, and the controllable anode current drops. On the other hand, the MOS gate structure thyristor shown in FIG. 3 is a voltage drive type, and the current required for turn-on is μA.
The value is several orders of magnitude lower than the above value. However, gate turn-off is not possible with this structure.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and is a GT having good turn-on and turn-off characteristics with a small gate power.
It is intended to provide O.

[Outline of Invention]

The present invention separates an on-gate electrode from an off-gate electrode, uses an on-gate as a voltage drive type such as a MOS gate structure, and adds an amplifying gate to the on-gate to provide a good turn-on characteristic with a minute gate power. Then, an off-gate is arranged in parallel with this structure so that turn-off characteristics can be obtained.

Example of Invention

An embodiment of the present invention will be described below with reference to the drawings. Fourth
FIG. 7 to FIG. 7 show sectional views of the structure which is the basis of the present embodiment. Since this is an example in which the structure corresponds to that of the conventional example, the same reference numerals are used for corresponding parts. Is that shown in Figure 4, the layer N ₁ is formed on the layer P _1, further layer P ₂ formed therein, further forming a layer N ₂ therein. layer
An insulator 11 such as an oxide is arranged so as to straddle N ₁ , P ₂ and N ₂ , and a gate electrode 12 is formed thereon. The anode electrode A is formed on the layer P ₁ , the cathode electrode K is formed on the layer N ₂ , and the gate electrode G ₂ is formed on the layer P ₂ . Then, the gate G ₁ is forward biased (positively biased) with respect to the layer P ₂ in a state where a voltage is applied so that the anode A is positive with respect to the cathode K, thereby forming a channel in the layer P _2. Turn it on. In the ON state, the gate G ₂ is turned on by negatively biasing the gate G ₂ .

FIG. 5 has almost the same structure as FIG. 4, but the gate electrode G ₂ is taken out from the layer P _{2 at a} different place, and is taken out between the MOS gate and the cathode.

6 and 7 show an example in which the vertical GTO of FIGS. 4 and 5 is applied to a horizontal GTO. Also in FIGS. 5 to 7 described above, the method of applying each electrode bias and the point of forming a channel in the layer P ₂ are exactly the same as in the case of FIG.

FIG. 8 shows an embodiment of the present invention using an amplification gate structure (auxiliary thyristor) based on the above structure. In this case, the amplification gate portion serving as a pilot is a P-type layer P ₃ adjacent to the layer N ₁ , an N-type layer N ₃ adjacent to the layer P ₃ , and a layer.
It has a gate electrode 12 ₁ arranged via an insulating layer 11 ₁ formed over N ₁ , P ₃ , and N ₃ and has a P-type layer P ₃ (N ₃ is an N-type layer) immediately below a gate G _1. ), A channel is generated, and when it is turned on, the MOS of the main thyristor is
The potential of the gate portion, that is, the point a, need only be raised with respect to the layer P ₂ , and the on-gate of the main thyristor is of the MOS type, and the current path is cut off by the gate insulating film thereof. Do not latch, that is, do not keep on. Therefore, the diode 2 required for the conventional GTO with an amplification gate as shown in FIG. 2 is not necessary, there is no device destruction at turn-off via the conventional latching amplification gate, and the controllable anode current value decreases. There is nothing to do.

FIG. 9 shows an optically driven type of the amplification gate section. That is, light is applied to the amplification gate section, the amplification gate section is turned on to raise the potential at point a, and the main thyristor is turned on.

In FIG. 10, the amplification gate section is replaced with a transistor composed of layers N ₁ , P ₃ , and N ₃ , and the main thyristor section is of an anode short type. The anode short type structure shown in FIG. 10 can be applied to all the structures shown in FIGS. 4 to 9 except FIG.

Figure 11 is taken out of the gate electrode _{G 3} from the layer _{N 1,} positively biased and the gate _{G 3} with respect to the anode A upon turn-off, not only the joint portion of the layer _P 2, _{N 3,} the layer _N 1, P
_A reverse bias is also applied to the junction portion of _{No. 1} so that it is turned off earlier. The structure of FIG. 11 is applicable to all of FIGS. 4 to 9 except FIG.

The present invention is not limited to the embodiments, and various applications are possible. For example, in FIGS. 9 to 11, instead of irradiating the amplification gate section with light, an electric signal may be applied to the layer P ₃ to turn it on.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a GTO in which the on-gate power is several orders of magnitude smaller than that of the conventional one, and good turn-on is possible, and also good turn-off is possible.

[Brief description of drawings]

1 to 3 are sectional views showing the structure of a conventional GTO,
4 to 7 show the GTO which is the basis of the embodiment of the present invention.
And FIG. 8 to FIG. 11 are sectional views showing an embodiment of the present invention. P ₁ ... First semiconductor layer, N ₁ ... Second semiconductor layer, P
₂ ...... third semiconductor layer, _{N 2} ...... fourth semiconductor layer, _{P 3}
...... Fifth semiconductor layer, N ₃ ...... Sixth semiconductor layer, A ......
1st electrode, K ... 2nd electrode, G ₁ ... 3rd electrode,
G ₂ ... fourth electrode, G ₃ ... fifth electrode, 11, 11
₁ ... Insulating layer, 12, 12 ₁ ... Electrode layer.

Claims (4)

[Claims] 1. A first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type adjacent to the layer, and a third semiconductor layer having a first conductivity type adjacent to the layer. A semiconductor layer, a fourth semiconductor layer having a second conductivity type adjacent to the semiconductor layer, a first electrode connected to the first semiconductor layer, and a second electrode connected to the fourth semiconductor layer. And a third electrode as an on-gate provided via an insulating film formed over the second, third and fourth semiconductor layers, and a fourth semiconductor layer connected to the third semiconductor layer. A GTO body composed of a fourth electrode serving as an off-gate which is provided so as not to be connected to the second semiconductor layer; and a GTO body of a first conductivity type formed adjacent to the second semiconductor layer separated from the third semiconductor layer. 5 semiconductor layer and a sixth semiconductor layer of the second conductivity type formed adjacent to the fifth semiconductor layer. An electrode connected to the sixth semiconductor layer is connected to the third electrode, and a sixth electrode is provided via an insulating film formed over the second, fifth, and sixth semiconductor layers. A semiconductor device comprising: an amplification gate portion having the electrode of. 2. The GTO body comprises a part partially connected to the first electrode at a position where the second semiconductor layer faces the fourth semiconductor layer. The semiconductor device according to item 1. 3. A first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type adjacent to the layer, and a third semiconductor layer having a first conductivity type adjacent to the layer. A semiconductor layer, a fourth semiconductor layer having a second conductivity type adjacent to the semiconductor layer, a first electrode connected to the first semiconductor layer, and a second electrode connected to the fourth semiconductor layer. And a third electrode as an on-gate provided via an insulating film formed over the second, third and fourth semiconductor layers, and a fourth semiconductor layer connected to the third semiconductor layer. A fourth electrode as an off-gate provided so as not to be connected to the second electrode,
A GTO body in which a semiconductor layer is partially connected to the first electrode; a fifth of the first conductivity type formed adjacent to the second semiconductor layer and separated from the third semiconductor layer; A semiconductor layer and a sixth semiconductor layer of the second conductivity type formed adjacent to the fifth semiconductor layer, and an electrode connected to the sixth semiconductor layer is connected to the third electrode. And the first electrode is connected to the second semiconductor layer, and the second, fifth, and sixth semiconductor layers each include an amplification gate section that operates as a transistor. . 4. A first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type adjacent to the layer, and a third semiconductor layer having a first conductivity type adjacent to the layer. A semiconductor layer, a fourth semiconductor layer having a second conductivity type adjacent to the semiconductor layer, a first electrode connected to the first semiconductor layer, and a second electrode connected to the fourth semiconductor layer. And a third electrode as an on-gate provided via an insulating film formed over the second, third and fourth semiconductor layers, and a fourth semiconductor layer connected to the third semiconductor layer. A GTO body composed of a fourth electrode as a first off-gate and a fifth electrode as a second off-gate connected to the second semiconductor layer, the GTO body being provided so as not to be connected to the third semiconductor layer; A fifth semiconductor layer of a first conductivity type formed adjacent to the second semiconductor layer separated from the semiconductor layer; An amplification gate section including a sixth semiconductor layer of the second conductivity type formed adjacent to the fifth semiconductor layer, and an electrode connected to the sixth semiconductor layer is connected to the third electrode. A semiconductor device comprising: