JPH06125230A - High frequency band/high output amplifier - Google Patents

High frequency band/high output amplifier

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Publication number
JPH06125230A
JPH06125230A JP4272192A JP27219292A JPH06125230A JP H06125230 A JPH06125230 A JP H06125230A JP 4272192 A JP4272192 A JP 4272192A JP 27219292 A JP27219292 A JP 27219292A JP H06125230 A JPH06125230 A JP H06125230A
Authority
JP
Japan
Prior art keywords
input
output
amplifier
level
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4272192A
Other languages
Japanese (ja)
Other versions
JP2903905B2 (en
Inventor
Takushi Mochizuki
拓志 望月
Osamu Yamamoto
修 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27219292A priority Critical patent/JP2903905B2/en
Publication of JPH06125230A publication Critical patent/JPH06125230A/en
Application granted granted Critical
Publication of JP2903905B2 publication Critical patent/JP2903905B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To reduce the distortions in a large amplitude input state by controlling the output impression voltage of the amplifier element of the final stage in the feedback of an envelope. CONSTITUTION:With regard to a field-effect transistor FET 1, the output voltage of an error amplifier 7 is increased to the large amplitude input by the operation of an envelope feedback circuit 9 and by the input follow-up. The increased output voltage of the amplifier 7 is reached as the input voltage of the FET 1 via a choke coil 13 which feeds the preceding increased output voltage as the input voltage of an inverted amplifier 10 and an adder 12. Thus the input of the FET 1 (source grounded) is pinched off (B-class) or deeply biased at the negative side (C-class). Meanwhile the output voltage of the amplifier 7 is reduced to the medium amplitude input by the operation of the circuit 9 and by the input follow-up. This reduced output voltage reaches as the input voltage of the FET 1. Thus the input voltage of the FET 1 is shallowly biased in the negative side and an A-class operating point is secured.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高周波帯高出力増幅器に
関し、特に増幅器における最終増幅段の高効率,低歪化
を計るために改良された高周波帯高出力増幅器に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency band high-power amplifier, and more particularly to a high-frequency band high-power amplifier improved in order to achieve high efficiency and low distortion of the final amplification stage of the amplifier.

【0002】[0002]

【従来の技術】従来の高周波帯高出力増幅器の回路構成
は、図3に示すように、高周波信号の入力端子15と、
この高出力増幅器の増幅信号の出力端子16との間に最
終段の増幅素子のデプレッション型電界効果トランジス
タ(以後FETという)1と、励振アンプ2と、FET
1の入力側に設けられた入力検波回路3,FET1の出
力側に設けられた減衰器4を含む出力検波回路5,入力
検波回路3の出力電圧と出力検波回路5の出力電圧との
差分を抽出する差分検出器6,差分を無くすべくFET
1の出力印加電圧となる出力電圧を誤差方向に追従して
可変する機能を有する誤差増幅器7,誤差増幅器7の出
力電圧をFET1の出力へ導く出力側電圧フィード用の
チョークコイル8から成るFET1用飽絡線帰還回路9
と、FET1のゲートにVgs電圧20を供給するチョ
ークコイル13とから構成される。
2. Description of the Related Art As shown in FIG. 3, the circuit configuration of a conventional high-frequency band high-output amplifier has a high-frequency signal input terminal 15 and
The depletion-type field effect transistor (hereinafter referred to as FET) 1 of the final stage amplification element, the excitation amplifier 2, and the FET are connected between the amplified signal output terminal 16 of the high-power amplifier.
The difference between the output voltage of the output detection circuit 5 including the attenuator 4 provided on the output side of the FET 1 and the output voltage of the output detection circuit 5 Difference detector to extract 6, FET to eliminate the difference
For the FET1, which includes an error amplifier 7 having a function of varying the output voltage to be the output applied voltage of No. 1 in the error direction and an output side voltage feed choke coil 8 for guiding the output voltage of the error amplifier 7 to the output of the FET1. Saturation line feedback circuit 9
And a choke coil 13 that supplies the Vgs voltage 20 to the gate of the FET 1.

【0003】次に図3の従来回路の動作を図4,図5の
動作説明図により説明する。一般にA級動作の増幅器に
比して優れた効率を持つB級及びC級動作の増幅素子に
対して、飽絡線帰還を施す事によって高効率化ならびに
低歪化を計っている。飽絡線帰還回路9は図4に示すよ
うに、変調波の飽絡線に沿って無帰還の場合に一定の出
力印加電圧であったものを、飽絡線の大振幅,中振幅,
小振幅に合わせて、飽絡線帰還による振幅素子出力印加
電圧を変えている。
Next, the operation of the conventional circuit of FIG. 3 will be described with reference to the operation explanatory diagrams of FIGS. Generally, the efficiency is improved and the distortion is reduced by performing the satiation feedback on the amplifier elements of class B and class C operation, which have excellent efficiency as compared with the amplifier of class A operation. As shown in FIG. 4, the saturating-wire feedback circuit 9 has a constant output applied voltage when there is no feedback along the saturating wire of the modulated wave.
The amplitude element output applied voltage by saturating line feedback is changed according to the small amplitude.

【0004】次に図5のFET1を含む飽絡線帰還回路
9の動作特性図5を参照して説明する。図5はFET1
のV−I特性であり、B級、C級動作点のピンチオフ点
では、ほぼ半波の小振幅,中振幅,大振幅入力が印加さ
れる。一方V−I特性はピンチオフ点に近い方の非線形
領域とV=0までの線形領域とを有している。主に非線
形領域で動作する中振幅,小振幅が波形歪を受け、時に
中振幅では図5に示すように、波形歪の無い場合の中振
幅出力に対して波形歪有りの中振幅出力が振幅圧縮され
て出力される。このようにB級、C級等の非線形動作に
より歪んだ増幅後の信号を飽絡線検波し、同様に入力側
でも検波した歪みのない入力信号とを差分検出器6にて
比較した後に、その差異をなくすべく誤差増幅器7の出
力電圧を増幅素子FET1の出力印加電圧として帰還さ
せる事によって、低歪率の入力信号に基づく増幅素子出
力制御が行なわれ結果としてB級、C級の高効率を保持
しながら、非線形性による増幅後の振幅歪みが増幅素子
出力電圧制御により軽減される事となる。なお、従来例
の飽絡線帰還を施した場合に、変調信号の飽絡線に追従
して増幅素子への出力印加電圧が可変される事により、
平均消費電力が低減され高効率化の一助を成している。
Next, the operation characteristic of the saturated wire feedback circuit 9 including the FET 1 of FIG. 5 will be described with reference to FIG. Figure 5 shows FET1
At the pinch-off points of the B-class and C-class operating points, a small-amplitude, medium-amplitude, and large-amplitude input of approximately half a wave is applied. On the other hand, the VI characteristic has a non-linear region closer to the pinch-off point and a linear region up to V = 0. Medium amplitude and small amplitude, which operate mainly in the non-linear region, are subject to waveform distortion. At medium amplitude, as shown in FIG. 5, the medium amplitude output with waveform distortion is the amplitude of the medium amplitude output with no waveform distortion. It is compressed and output. In this way, the amplified signal distorted by the non-linear operation of class B, class C, etc. is subjected to the saturating line detection, and similarly, the undetected input signal detected on the input side is compared by the difference detector 6, In order to eliminate the difference, the output voltage of the error amplifier 7 is fed back as the output applied voltage of the amplifying element FET1 to control the amplifying element output based on the low distortion input signal, resulting in high efficiency of class B and class C. While holding, the amplitude distortion after amplification due to the non-linearity is reduced by controlling the output voltage of the amplification element. When the saturating line feedback of the conventional example is performed, the output applied voltage to the amplifying element is changed by following the saturating line of the modulation signal.
The average power consumption is reduced, contributing to higher efficiency.

【0005】しかしながら入出力信号飽絡線検波に基づ
く増幅素子出力電圧制御のみを行なった場合の歪は、F
ET1への入力印加電圧Vgs電圧20を固定としてい
たので、出力変調信号の中出力領域では波形歪みが発生
する点で改善の余地があった。すなわち、FET1自身
の持つV−I特性において、中振幅の出力時はB,C級
動作により出力半波スイングと大部分は非線形領域であ
る立ち上がり特性の湾曲領域で動作するので、出力波形
に歪みが生じる。一方、小信号時の歪は、信号自身が小
さいので、発生量としては無視し得る。又、大信号時は
出力半波スイングの殆どは線形領域で動作するので、V
−I特性の非線形領域の影響は表面化しない。ただし、
クリッピングを起こさない入出力状態での条件である。
However, the distortion in the case where only the amplification element output voltage control based on the input / output signal saturation detection is performed is F
Since the input applied voltage Vgs voltage 20 to the ET1 is fixed, there is room for improvement in that waveform distortion occurs in the medium output region of the output modulation signal. That is, in the V-I characteristic of the FET 1 itself, at the time of outputting a medium amplitude, the output waveform is distorted because the output half-wave swing and most of it operates in the bending region of the rising characteristic which is a non-linear region when the medium amplitude is output. Occurs. On the other hand, since the signal itself is small, the distortion at the time of a small signal can be ignored as the amount of generation. Also, when a large signal is output, most of the output half-wave swing operates in the linear region, so V
The influence of the non-linear region of the −I characteristic is not surfaced. However,
This is a condition in the input / output state where clipping does not occur.

【0006】[0006]

【発明が解決しようとする課題】上述した従来の高周波
高出力増幅器は、増幅素子への入力印加電圧VgsをB
級あるいはC級に固定としていたので、中信号入力時に
おける変調信号の中出力領域において増幅素子のV−I
特性の非線形領域で波形歪みが発生する欠点があった。
In the above-mentioned conventional high frequency and high output amplifier, the input applied voltage Vgs to the amplifying element is set to B.
Since it is fixed to class C or class C, the V-I of the amplifying element in the medium output region of the modulated signal at the time of medium signal input
There is a drawback that waveform distortion occurs in the nonlinear region of characteristics.

【0007】[0007]

【課題を解決するための手段】本発明の高周波帯高出力
増幅器は入力される小振幅,中振幅,大振幅の高周波信
号を増幅する励振増幅器と、この励振増幅器の出力レベ
ルの一部を分岐して検出する入力検波回路と、前記励振
増幅器の出力信号を入力して電力増幅する高周波増幅素
子と、この高周波増幅素子の出力信号の一部を分岐して
検出する出力検波回路と、前記入力検波回路の検波レベ
ルと前記出力検波回路の検波レベルとを入力して差のレ
ベルを検出する差分検出器と、この差分検出器の出力を
増幅した後にチョークコイルを通して前記高周波増幅素
子の出力端子に帰還する第1のレベルを供給する高周波
帯高出力増幅器において、前記第1のレベルを反転し第
2のレベルを生成する反転増幅器と、前記高周波増幅素
子のゲートソース間電圧に対応するオフセット電圧とな
る第3のレベルと前記第2のレベルとを相加する加算器
と、この加算器の出力レベルを前記高周波増幅素子の入
力端子に供給する。
The high frequency band high output amplifier of the present invention is an excitation amplifier for amplifying a small amplitude, medium amplitude and large amplitude high frequency signal to be inputted, and a part of the output level of this excitation amplifier. An input detection circuit for detecting the input signal, a high-frequency amplification element for inputting and amplifying the power of the output signal of the excitation amplifier, an output detection circuit for branching and detecting a part of the output signal of the high-frequency amplification element, and the input A difference detector for detecting the difference level by inputting the detection level of the detection circuit and the detection level of the output detection circuit, and an output terminal of the high frequency amplification element through a choke coil after amplifying the output of the difference detector. In a high frequency band high power amplifier for supplying a first level to be fed back, an inverting amplifier for inverting the first level to generate a second level, and a gate source of the high frequency amplifying element A third level and the second level and to additive the adder becomes the offset voltage corresponding to the voltage, and supplies the output level of the adder to the input terminal of the high-frequency amplifying device.

【0008】[0008]

【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の一実施例の回路構成を示すブロック
図である。図1において図3の従来例と同一の符号は同
一の構成と機能を有する。すなわち、本実施例は動作点
制御回路14を追加している。この動作点制御回路14
は、誤差増幅器7の出力電圧を反転増幅する直流増幅器
10、小信号時の入力オフセット印加電圧(Vgs)1
1を直流増幅器10の出力電圧に加算する加算器12
と、FET1の入力印加電圧となる加算器12の出力電
圧をFET1の入力へ導くチョークコイル13を有する
入力側電圧フィード線とからなるFET1用動作点制御
回路14とで構成されている。
The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention. 1, the same reference numerals as those in the conventional example of FIG. 3 have the same configurations and functions. That is, in this embodiment, the operating point control circuit 14 is added. This operating point control circuit 14
Is a DC amplifier 10 that inverts and amplifies the output voltage of the error amplifier 7, and an input offset applied voltage (Vgs) 1 at the time of a small signal.
Adder 12 for adding 1 to the output voltage of the DC amplifier 10
And an operating point control circuit 14 for the FET 1 including an input side voltage feed line having a choke coil 13 for guiding the output voltage of the adder 12 which is the input applied voltage of the FET 1 to the input of the FET 1.

【0009】次に本実施例の動作を説明する。FET1
は、大振幅入力に対しては飽絡線帰還回路9の動作によ
り入力追従して誤差増幅器7の出力電圧は大きく、これ
が反転増幅器10、加算器12の入力側電圧としてフィ
ードするチョークコイル13を経てFET1の入力電圧
として到達し、FET1(ソース接地)の入力をピンチ
オフ状態(B級)あるいはさらに負の側に深くバイアス
する(C級)。ここでB,C級の設定は反転増幅器10
の利得を可変する事により行なわれる。入力印加電圧に
よりFET1はBあるいはC級上で従来例と同様に飽絡
線帰還の作動でFET1の出力電圧に帰還がかかり、高
効率化・低歪化が計られる。又、中振幅入力に対しては
同様に飽絡線帰還回路9の動作により入力追従して誤差
増幅器7の出力電圧は小さく、これがFET1の入力電
圧として到達する事により、FET1の入力電圧は負の
側に浅くバイアスされる事となり、動作点はA級とな
る。したがって中振幅スイングがV−I特性上の線形動
作領域で行なわれる事から従来例のB級、C級固定入力
バイアス時に比して波形歪みは改善される。前述の動作
点の移動を図2のV−I特性上にて示す。さらに小振幅
入力時には、FET1への入力印加電圧は0Vの方向に
移動し、より浅い動作点となるが、反転増幅器10の出
力電圧が0Vになったとしても、加算器12に加算され
た入力オフセット印加電圧11より浅い入力印加電圧に
はならず、中振幅入力から小振幅入力にかけてのA級動
作を保証している。上述した様に本発明は中小振幅入力
に対しては高効率化のメリットは少ないので、低歪化を
主眼として特性の改良をはかっている。なお、この入力
信号振幅に対してのダイナミックな最終段増幅素子の入
出力印加電圧制御回路は多様な変調波振幅に即応した高
周波帯高出力増幅器の高効率化・低歪化を行なう事がで
きる。
Next, the operation of this embodiment will be described. FET1
For a large-amplitude input, the output voltage of the error amplifier 7 is large by following the input by the operation of the saturation line feedback circuit 9, and the choke coil 13 that feeds this as the input side voltage of the inverting amplifier 10 and the adder 12 is used. After that, the voltage reaches the input voltage of the FET1 and the input of the FET1 (source ground) is pinched off (class B) or further deeply biased to the negative side (class C). Here, the setting of B and C is the inverting amplifier 10
This is done by changing the gain of. By the input applied voltage, the FET 1 is in the B or C class, and the output voltage of the FET 1 is fed back by the operation of the saturating line feedback similarly to the conventional example, and the efficiency and the distortion are reduced. Similarly, for a medium-amplitude input, the output voltage of the error amplifier 7 is small by following the input by the operation of the saturating wire feedback circuit 9, and this reaches as the input voltage of the FET 1, so that the input voltage of the FET 1 is negative. Is biased to the side of, and the operating point is class A. Therefore, since the medium amplitude swing is performed in the linear operation region on the VI characteristic, the waveform distortion is improved as compared with the conventional class B and class C fixed input bias. The above-mentioned movement of the operating point is shown on the VI characteristic of FIG. Further, when a small amplitude is input, the input voltage applied to the FET1 moves in the direction of 0V to reach a shallower operating point, but even if the output voltage of the inverting amplifier 10 becomes 0V, the input added to the adder 12 is added. The input applied voltage is shallower than the offset applied voltage 11, and the class A operation is guaranteed from the medium amplitude input to the small amplitude input. As described above, the present invention has little merit of increasing the efficiency with respect to small and medium amplitude inputs, and therefore aims at improving the characteristics with a focus on reducing distortion. It should be noted that the input / output applied voltage control circuit of the final-stage amplifying element which is dynamic with respect to this input signal amplitude can realize high efficiency and low distortion of the high-frequency band high-power amplifier that immediately responds to various modulated wave amplitudes. .

【0010】[0010]

【発明の効果】以上説明した様に本発明は、飽絡線帰還
での最終段増幅素子の出力印加電圧制御により大振幅入
力時の低歪化を計ると共に、入力信号振幅に対応して増
幅素子入力印加電圧も制御する事により、大振幅入力時
には最終段増幅素子の動作をB級として高効率化し、中
振幅から小振幅入力時は動作点をA級へと移行させ波形
歪を低減する事を可能とする効果がある。したがって通
信端局の小型・軽量化及び歪による変調波サイドローブ
に起因した隣接チャンネル間干渉等を問題とする小チャ
ンネル・スペーシングを要求されるシステムの実現に対
しても効果を有する。
As described above, according to the present invention, by controlling the output applied voltage of the final stage amplifier element in the saturating line feedback, distortion can be reduced at the time of inputting a large amplitude, and amplification can be performed corresponding to the input signal amplitude. By controlling the element input applied voltage as well, the operation of the final stage amplification element is set to class B for high efficiency input, and the operating point is changed to class A for medium amplitude to small amplitude input to reduce waveform distortion. It has the effect of making things possible. Therefore, the present invention is also effective for realizing a system requiring small channel spacing, which is a problem in that the communication terminal station is small and lightweight, and interference between adjacent channels due to side waves of modulated waves due to distortion is a problem.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

【図2】本実施例の動作説明図である。FIG. 2 is an operation explanatory diagram of the present embodiment.

【図3】従来例のブロック図である。FIG. 3 is a block diagram of a conventional example.

【図4】本実施例と従来例を比較する説明図である。FIG. 4 is an explanatory diagram comparing this embodiment with a conventional example.

【図5】従来例の動作説明図である。FIG. 5 is an operation explanatory diagram of a conventional example.

【符号の説明】[Explanation of symbols]

1 増幅素子(FET) 2 励振アンプ 3 入力検波回路 4 減衰器 5 出力検波回路 6 差分検出回路 7 誤差増幅器 8,13 チョークコイル 9 飽絡線帰還回路 10 反転増幅器 11 オフセット印加電圧 12 加算器 14 動作点制御回路 15 入力端子 16 出力端子 17 コンデンサ 18 同調回路 1 Amplifier element (FET) 2 Excitation amplifier 3 Input detection circuit 4 Attenuator 5 Output detection circuit 6 Difference detection circuit 7 Error amplifier 8,13 Choke coil 9 Saturation line feedback circuit 10 Inversion amplifier 11 Offset applied voltage 12 Adder 14 Operation Point control circuit 15 Input terminal 16 Output terminal 17 Capacitor 18 Tuning circuit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 入力される小振幅,中振幅,大振幅の高
周波信号を増幅する励振増幅器と、この励振増幅器の出
力レベルの一部を分岐して検出する入力検波回路と、前
記励振増幅器の出力信号を入力して電力増幅する高周波
増幅素子と、この高周波増幅素子の出力信号の一部を分
岐して検出する出力検波回路と、前記入力検波回路の検
波レベルと前記出力検波回路の検波レベルとを入力して
差のレベルを検出する差分検出器と、この差分検出器の
出力を増幅した後にチョークコイルを通して前記高周波
増幅素子の出力端子に帰還する第1のレベルを供給する
高周波帯高出力増幅器において、前記第1のレベルを反
転し第2のレベルを生成する反転増幅器と、前記高周波
増幅素子のゲートソース間電圧に対応するオフセット電
圧となる第3のレベルと前記第2のレベルとを相加する
加算器と、この加算器の出力レベルを前記高周波増幅素
子の入力端子に供給することを特徴とする高周波帯高出
力増幅器。
1. An excitation amplifier that amplifies a high-frequency signal of small amplitude, medium amplitude, and large amplitude that is input, an input detection circuit that branches and detects a part of the output level of the excitation amplifier, and an excitation amplifier of the excitation amplifier. A high frequency amplifying element for inputting an output signal to amplify the power, an output detecting circuit for branching and detecting a part of the output signal of the high frequency amplifying element, a detection level of the input detecting circuit and a detection level of the output detecting circuit. And a high-frequency band high output for supplying a first level which is fed back to the output terminal of the high-frequency amplifier element through a choke coil after amplifying the output of the difference detector. In the amplifier, an inverting amplifier that inverts the first level to generate a second level, and a third level that becomes an offset voltage corresponding to a gate-source voltage of the high-frequency amplifier element. A high-frequency band high-output amplifier, wherein an adder for adding the second level and the output level of the adder is supplied to an input terminal of the high-frequency amplification element.
【請求項2】 前記加算器の出力レベルが前記入力され
る小振幅,中振幅に対応して前記高周波増幅素子をB級
C級動作の方向に制御することを特徴とする請求項1記
載の高周波帯高出力増幅器。
2. The high frequency amplifying device is controlled in the direction of class B or class C operation in accordance with the input small and medium amplitudes of the output level of the adder. High frequency high power amplifier.
JP27219292A 1992-10-12 1992-10-12 High frequency band high power amplifier Expired - Lifetime JP2903905B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27219292A JP2903905B2 (en) 1992-10-12 1992-10-12 High frequency band high power amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27219292A JP2903905B2 (en) 1992-10-12 1992-10-12 High frequency band high power amplifier

Publications (2)

Publication Number Publication Date
JPH06125230A true JPH06125230A (en) 1994-05-06
JP2903905B2 JP2903905B2 (en) 1999-06-14

Family

ID=17510375

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27219292A Expired - Lifetime JP2903905B2 (en) 1992-10-12 1992-10-12 High frequency band high power amplifier

Country Status (1)

Country Link
JP (1) JP2903905B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6111461A (en) * 1997-10-15 2000-08-29 Nec Corporation High frequency amplifier circuit
JP2007116259A (en) * 2005-10-18 2007-05-10 Hitachi Kokusai Electric Inc Amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6111461A (en) * 1997-10-15 2000-08-29 Nec Corporation High frequency amplifier circuit
JP2007116259A (en) * 2005-10-18 2007-05-10 Hitachi Kokusai Electric Inc Amplifier

Also Published As

Publication number Publication date
JP2903905B2 (en) 1999-06-14

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