JPH06125077A - Insulated-gate type thyristor - Google Patents

Abstract

PURPOSE:To provide an insulated-gate type thyristor which has a fast turn-off speed, easy turn-on and easy manufacture while maintaining low gate driving current characteristics. CONSTITUTION:An insulated-gate type thyristor comprises a p-n-p-n type thyristor structure formed of a first conductivity type semiconductor region p1, a second conductivity type first semiconductor region n1, a first conductivity type second semiconductor region p2 and a second conductivity type second semiconductor region n2 of a semiconductor substrate. An anode electrode 11 is brought into contact with the first conductivity type first semiconductor region, and a cathode electrode 12 is brought into contact with both the region n2 and a first conductivity type third semiconductor region p3. A groove 15 which reaches the region n1 from the surface of the other side of the substrate and has parts exposed with the regions n2 and p2 and exposed with n1 on an inner surface is provided, and a gate electrode 17 is provided in the groove through an insulating film 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate thyristor.

[0002]

2. Description of the Related Art A conventional insulated gate thyristor has a problem that a so-called pnpn thyristor has had, that is, a large gate drawing current (charge amount) at turn-off, and circuits of different systems for ON operation and OFF operation. Was devised to eliminate the need for.

FIG. 2 shows a main structure of a conventional insulated gate thyristor. This insulated gate thyristor 51
In the semiconductor substrate 52 of, the p-type region 5 is formed on the back surface on the anode side.
3, an n-type region 54 for the first base region is provided above the p-type region 53, and a p-type region 55 for the second base region is formed on the surface portion of the n-type region 54. An n-type region 56 is formed on the surface of the p-type region 55, and a p-type region 57 is further formed on the surface of the n-type region 56. And p on the back side
The anode electrode 63 is in contact with the surface of the mold region 53, and the cathode electrode 66 is in contact with the n-type region 56 and the p-type region 57 on the surface side.
A gate electrode 68 is provided above the n-type region 56 and the n-type region 56 via a gate oxide film 67.

The turn-on operation of this insulated gate thyristor 51 is as follows. When the positive voltage is applied to the gate electrode 68 while the positive voltage is applied to the anode electrode 63 when the thyristor 51 is in the cutoff state, the MOS including the n-type region 56, the p-type region 55 and the n-type region 54 is formed.
The transistor T3 is turned on, and the MOS transistor T4 including the p-type region 57, the n-type region 56 and the p-type region 55 is turned off.

In this case, a current flows from the anode electrode 63 to the cathode electrode 66 via the n-type region 54 and the transistor T3. At this time, the cathode electrode 66
More electrons are injected, and as a result, the n-type region 54 and the p-type region 55 are in the forward bias state. Of course, the transistor T1 including the p-type region 53, the n-type region 54, and the p-type region 55 and the transistor T2 including the n-type region 54, the p-type region 55, and the n-type region 56 have positive feedbacks therebetween. With such a configuration, the current from the anode electrode 63 is applied to the p-type region 53, the n-type region 54, the p-type region 55, n.
It flows in the mold region 56 according to a normal thyristor operation, and is self-held even if the voltage applied to the gate electrode 68 is zero, and the thyristor is maintained in the on (conducting) state.

The turn-off operation of this insulated gate thyristor 51 is as follows. When a negative voltage is applied to the gate electrode 68 when the thyristor 51 is in the conductive state,
The MOS transistor T4 is turned on, and a part of the main current (holes reaching the p-type region 55) is part of the MOS transistor T4.
Flowing through the channel of the cathode electrode 66. In this case, the current that can be held by the positive feedback loop cannot be secured, and as a result, the transistors T1, T
2 is turned off and the thyristor is cut off.

Thus, the insulated gate thyristor 51 is
Has an advantage that the gate drive current is small because it can be controlled independently for ON and OFF by applying positive and negative voltages to the same gate electrode and is an insulated gate.

[0008]

However, the insulated gate thyristor 51 has a problem that the turn-off speed becomes slow when the current capacity is large, although the drive current amount at turn-off is small. A p-channel resistor (on-resistance of the p-channel MOS transistor T4) is provided in the path of the current flowing through the MOS transistor T4 when turned off.
When there is a large amount of main current to be cut off, p
The turn-off speed becomes slower because the influence of the channel resistance increases.

Of course, by reducing the channel length (width), the resistance of the p-channel can be reduced, but from the viewpoint of manufacturing or large current capacity, it is impossible to reduce the turn-off speed sufficiently. In addition, the insulated gate thyristor 51 is additionally manufactured in order to control the threshold value of the MOS transistors T3 and T4 of different types of p-channel and n-channel under the same gate electrode and to form a triple diffusion region. There is also the problem that it is not easy.

In view of the above circumstances, the present invention has a high turn-off speed while maintaining a low gate drive current characteristic.
Moreover, it is an object to provide an insulated gate thyristor that is easy to turn on and easy to manufacture.

[0011]

In order to solve the above problems, an insulated gate thyristor according to the present invention is provided with a first conductivity type first semiconductor region for an anode region on one side of a semiconductor substrate. A first conductivity type semiconductor region on the first semiconductor region;
A second conductive type first semiconductor region for the base region, and a first conductive type second semiconductor region for the second base region and a cathode in a certain portion above the second conductive type first semiconductor region. A second conductive type second semiconductor region for the region, which is provided in order, and is provided on the other portion of the second conductive type first semiconductor region so that its surface is exposed on the other side of the semiconductor substrate. A pnpn thyristor structure including a conductive third semiconductor region, the anode region, the first and second base regions, and the cathode region is formed, and the first conductive first semiconductor region is in contact with an anode electrode, A cathode electrode is in contact with the second conductivity type second semiconductor region and the first conductivity type third semiconductor region, and the second conductivity type first semiconductor region is reached from the surface on the other side of the semiconductor substrate to the second conductivity type inside. Type number A groove having a semiconductor region, a portion where the first conductivity type second semiconductor region is exposed, and a portion where the first conductivity type first semiconductor region is exposed is provided, and a gate electrode is provided in this groove through an insulating film. It has a different structure.

In the insulated gate thyristor of the present invention,
A preferred configuration is one in which the groove reaching the second conductivity type first semiconductor region for the first base region extends into the second conductivity type first semiconductor region. Note that the number of grooves is not limited to one and may be plural. In the present invention, of course, when the first conductivity type is p-type, the second conductivity type is n-type, and conversely, when the first conductivity type is n-type, the second conductivity type is p-type.
It is a type.

[0013]

The insulated gate thyristor according to the present invention is
Since turn-off is performed by applying a voltage to the gate electrode provided via the insulating film, the gate drive current at turn-off is extremely small. The insulated gate thyristor according to the present invention basically has a so-called pnpn thyristor structure and does not require the triple diffusion region forming step required in the conventional thyristor of FIG. 2, and the MOS transistor is also formed under the same gate electrode. Since two p-channels and n-channels do not coexist, but only one type of channel exists, the situation in which it is difficult to control the threshold value is solved.

In the insulated gate thyristor according to the present invention, the carriers remaining in the semiconductor region for the base region at the time of turn-off are rapidly extracted from the cathode electrode through the third semiconductor region of the first conductivity type with which the cathode electrode contacts, and the positive feedback is provided. The loop stops and turns off. Of course, the turn-off speed is related to the gate voltage, the impurity concentration of the third semiconductor region of the first conductivity type with which the cathode electrode contacts, the depth of the groove, and the like, but the extraction speed of residual carriers of the MOS transistor is limited. Since it does not need to depend on only the channel, relatively free setting (improvement of turn-off speed) becomes possible.

The insulated gate thyristor according to the present invention applies a positive voltage to the gate electrode at the time of turn-on,
By turning on the MOS transistor formed in the second conductivity type second semiconductor region, the first conductivity type second semiconductor region, and the second conductivity type first semiconductor region, the thyristor is quickly turned on. When the groove reaching the second conductivity type first semiconductor region for the first base region extends to the inside of the second conductivity type first semiconductor region, the carrier remaining in the base region can be extracted more quickly. Will be done.

[0016]

Embodiments of the present invention will be described below. Of course,
The present invention is not limited to the embodiments described below. -Embodiment- FIG. 1 is a cross-sectional view showing a main configuration of an insulated gate thyristor according to an embodiment.

In the insulated gate thyristor 1 of the embodiment,
The back surface side (one side) of the semiconductor substrate 2 is provided with a p-type region P1 (first conductivity type first semiconductor region) for the anode region,
An n-type region n1 (second conductivity type first semiconductor region) for the first base region is provided on the type region p1.
A p-type region p2 (first conductivity type second semiconductor region) for the second base region and an n-type region n2 (second conductivity type second semiconductor region) for the cathode region are sequentially provided in a certain portion on the type region n1. In addition, a p-type region p3 (second conductivity type third semiconductor region) provided so that its surface is exposed on the front side (other side) of the semiconductor substrate 2 is provided in another portion on the n-type region n1.
P composed of four semiconductor regions stacked in order, that is, an anode region, first and second base regions, and a cathode region.
An npn thyristor structure is formed. p-type region p
The positive feedback is applied between the transistor composed of the n-type region n1 and the p-type region p2 and the transistor composed of the n-type region n1, the p-type region p2 and the n-type region n2. .

The anode electrode 1 is formed in the p-type region p1.
1 is in contact, and the cathode electrode 12 is in contact with the n-type region n2 and the p-type region p3. That is, the n-type region n2 and the p-type region p3 are short-circuited by the cathode electrode 12. On the other hand, in the semiconductor substrate 2, the groove 15 reaching the n-type region n1 from the front surface is formed,
The inner surface of the groove 15 has a portion where the n-type region n2 and the p-type region p2 are exposed (left side surface portion in FIG. 1) and a portion where the p-type region p3 is exposed (right side surface portion in FIG. 1). ing. The gate electrode 17 is provided in the groove 15 with the insulating film 16 interposed therebetween.

Next, the turn-on operation of the insulated gate thyristor 1 will be described. The turn-on is the same as the so-called four-layer pnpn thyristor, in which a positive voltage is applied to the anode electrode 11 and the thyristor is in the blocking state (when the n-type region n1 and the p-type region p2 are in the reverse bias state). When a positive voltage is applied to the gate electrode 17, the n-channel MOS transistors in the n-type region n1, p-type region p2 and n-type region n2 are turned on, and the current from the anode 11 is p-type region p1-n-type region n1- p-type region p2-
A transistor composed of a p-type region p1, an n-type region n1 and a p-type region p2 which flow to the n-type region n2 and form a positive feedback loop, and an n-type region n1, a p-type region p2 and an n-type region n2. A saturated current flows through the transistor to shift to the thyristor-on state, and the transistor remains in the on state even if the voltage of the gate electrode 17 is set to zero.

Next, the turn-off operation of the insulated gate thyristor 1 will be described. Turn-off applies a negative voltage to the gate electrode 17 when the thyristor is on.
Then, the p-type region p3 adjacent to the gate oxide film 16 is formed.
Holes are induced by the electric field and extracted from the cathode electrode 12 that contacts the p-type region p2. That is, a part of the main current is discharged from the p-type region p3 and becomes less than the holding current of the positive feedback loop, so that the thyristor is turned off. At this time, holes remaining in the p-type region p2 and the n-type region n1 do not pass through the channel of the MOS transistor and are immediately discharged from the p-type region p3, so that the turn-off speed is high. The hole discharge speed is related to the impurity concentration of the p-type region p3 (usually higher than that of the p-type region p2 and the n-type region n1), the gate voltage, and the depth of the trench 15, but the magnitude of the main current and It may be set appropriately according to the short-circuit current amount (charge amount) at turn-off.

Of course, since the gate electrode 17 is an insulated gate, the driving current at turn-on and turn-off can be driven by a simple low-voltage circuit with a small amount. The groove 15 is
The holes enter the n-type region n1, and in this case, holes in the n-type region n1 in addition to the p-type region p3 are promptly extracted from the cathode electrode 12. However, the groove 15 may have a depth just reaching the upper surface of the n-type region n1.

The present invention is not limited to the above embodiment. For example, in FIGS. 1 and 2, the p-type and n-type inversion configurations can be mentioned as other examples. Further, another example in which the groove 15 is formed in a V shape can be cited.

[0023]

In the insulated gate thyristor according to the present invention, since the gate electrode is an insulated gate, low gate drive current characteristics are maintained, and there is no triple diffusion region forming step or difficult threshold control. It is easy to manufacture, and the carriers remaining in the base region at the time of turn-off are quickly extracted, so that the turn-off speed can be improved.
It is very useful because it can be easily turned on by the insulated gate.

The groove that extends into the second conductivity type first semiconductor region for the first base region functions to more quickly extract the carriers remaining in the base region, so that the turn-off speed can be further improved. Become.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a main part configuration of an insulated gate thyristor according to an embodiment.

FIG. 2 is a schematic cross-sectional view showing a configuration of a main part of a conventional insulated gate thyristor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Insulated gate type thyristor 2 Semiconductor substrate 11 Anode electrode 12 Cathode electrode 15 Groove 16 Insulating film 17 Gate electrode p1 p type region (first conductivity type first semiconductor region) n1 n type region (second conductivity type first semiconductor region) p2 p-type region (first conductivity type second semiconductor region) n2 n-type region (second conductivity type second semiconductor region) p3 p-type region (first conductivity type third semiconductor region)

Claims (2)

[Claims] 1. A first conductive type first semiconductor region for an anode region is provided on one side of a semiconductor substrate, and a second conductive type first semiconductor region for a first base region is provided on the first conductive type first semiconductor region. A second conductive type second semiconductor region for the second base region and a second conductive type second semiconductor for the cathode region, which is provided with a semiconductor region and in a certain portion above the second conductive type first semiconductor region. Regions are provided in order, and a first conductivity type third semiconductor region is provided on the other portion of the second conductivity type first semiconductor region so that the surface thereof is exposed on the other side of the semiconductor substrate. A pnpn thyristor structure including an anode region, first and second base regions, and a cathode region is formed, and an anode electrode is in contact with the first conductivity type first semiconductor region and the second conductivity type second semiconductor region and the second conductivity type second semiconductor region. 1 conductivity type third semiconductor region Is in contact with the cathode electrode and from the surface on the other side of the semiconductor substrate to the second conductivity type first
A groove having a second conductivity type second semiconductor region, a part exposing the first conductivity type second semiconductor region, and a part exposing the first conductivity type first semiconductor region is provided on the inner surface reaching the semiconductor region; An insulated gate thyristor in which a gate electrode is provided in this groove via an insulating film. 2. The insulated gate thyristor according to claim 1, wherein a groove reaching the second conductivity type first semiconductor region for the first base region extends into the second conductivity type first semiconductor region.