JPH06124206A - Branching instruction estimation processor and processing method therefor - Google Patents

Abstract

PURPOSE:To perform branching estimation even immediately after applying a power source and at the time of resetting. CONSTITUTION:All the contents of a branching estimation table 10 are '0' immediately after applying the power source and at the time of resetting, however, prescribed data can be set to the respective entries of the branching estimation table 10 by a branching estimation table changing instruction execution part 11 before executing a program. Thus, the branching estimation is performed by using the data inside the branching estimation table 10 immediately after starting the execution of the program. Also, before executing a new job, the data matched with job can be set to the respective entries of the branching estimation table 10 by the branching estimation table changing instruction execution part 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a branch instruction prediction processing apparatus for predicting the branch direction and branch destination of a branch instruction before the execution result of the branch instruction is known, thereby fetching the instruction immediately following the branch instruction. It relates to the processing method.

[0002]

2. Description of the Related Art Conventionally, branch instruction prediction has been performed by the following method. First, as a first method, there is a method in which a branch direction is uniquely determined and predicted in advance. This always predicts in one direction regardless of past instruction execution results, and there are methods that predict branching (taken prediction) and methods that predict not branching (not-taken prediction). However, in these methods, since the branching direction is fixed, the prediction hit rate was low.
In addition, the prediction is limited to the branch direction, and the instruction at the branch destination cannot be fetched in advance. Therefore, branch prediction is a method in which the prediction of the branch direction is performed dynamically at the time of execution, and the branch target instruction can be fetched in advance before the execution of the branch instruction is completed and the branch direction and the branch target address are determined. A method using a table has been proposed.

FIG. 2 is an explanatory diagram of the branch prediction table. The illustrated branch prediction table is composed of four fields of a branch instruction address, a branch destination address, a branch direction prediction, and Valid. For branch direction prediction,
Johnny KFLee, Alan Jay Smith "Branch Prediction S
trategies and Branch target Buffer Design "IEEE CO
Detailed in MPUPER January 1984. The information for predicting the branch direction is usually composed of 2 bits.
Then, for example, it is updated by an algorithm that changes the branch direction prediction when the prediction is missed twice. Also, V
The "alid" bit normally indicates that the entry is valid when "1", and indicates that the entry is invalid when "0". By using such a branch prediction table, it becomes possible to predict the branch destination when the branch instruction is fetched, faster than executing the branch instruction to judge the branch condition and calculate the branch destination address. . This eliminates unnecessary waiting time until the branch instruction execution result is obtained. If this prediction is not successful, the branch destination is predicted and the result executed in advance is discarded.

Such a branch prediction table is updated every time a branch instruction is processed. In other words, when a certain branch instruction has an address corresponding to the branch instruction address field and the Valid field of the entry is "1", the branch direction prediction field of the entry causes the branch instruction to branch. The value obtained by a certain algorithm is written depending on whether or not it is performed. For example, if this branch instruction has always taken a branch in the past, the branch direction prediction field is "11", and if a branch is not taken as a result of executing this new branch instruction, this field is set to "1".
Changes to 0 ".

Furthermore, the branch destination address when the branch is executed by the branch instruction is written in the branch destination address field of the entry. If there is no corresponding address in the branch instruction address field and the Valid fields of all the entries are “1”, the entry having the oldest accessed branch instruction address is deleted and the branch instruction address relating to the new branch instruction address is deleted. Write information. If the branch instruction address does not have a corresponding address and there is an entry whose Valid field is "0", one of those entries is selected and used. Here, in the branch prediction table, Valid
When the value of the field is "1" but the address corresponding to the fetched branch instruction address does not exist in the branch instruction addresses, the result of executing the branch instruction is:
Consider what happens when you have to branch.

FIG. 3 is an explanatory diagram of an example of an instruction sequence and instruction execution timing. In the illustrated example, the instruction of FIG. 3A indicates that the branch is performed when the content of the condition register is "0", and the branch destination address is held in the register R10. The instruction of FIG. 3B is an instruction of an address immediately after the instruction of FIG. 3A, and indicates that the sum of the contents of the registers R11 and R12 is obtained and written in R13. Figure 3 (c)
3 is an address instruction having the contents of R10, and FIG.
Similar to (b), it is shown that the sum of the contents of the registers R21 and R22 is obtained and written to R23. In the apparatus for executing the execution as shown in FIG. 3, the execution is f (instruction fetch), d (instruction decode, read operand from register), e.
(Instruction execution, branch condition judgment, branch destination address calculation),
Pipeline processing represented by four stages of w (writing of results) is performed.

While the instruction of FIG. 3A is being fetched, the branch instruction address of the branch prediction table is searched. However, since there is no corresponding instruction address, in the next stage, the address fetched earlier is selected. Instructions at consecutive addresses are fetched. However, it is assumed that the branch condition is determined at the e stage of the instruction of FIG. 3A and it is found that the branch condition is satisfied. In this case, the content of the condition register is "0". Then, since the branch destination address is further calculated, the branch destination instruction of FIG. 3C is fetched in the next stage, and thereafter, the instruction of this address is successively processed. However, execution of the instruction of FIG. 3B is stopped only when it has advanced to the d stage. At this time, there is a delay of two stages as compared with the case where the branch prediction is successful.

[0008]

However, the above-mentioned conventional technique has the following problems. That is, the initial states of the Valid fields in the branch prediction table are all "0", and when the computer starts executing the program immediately after power-on and reset, branch prediction cannot be performed at all. Further, when the computer starts a new job, the execution of an instruction at an address completely different from that before that is started, so that even if the Valid field of the branch prediction table is all "1", the corresponding instruction is executed. The address does not exist in the branch instruction address field of the branch prediction table, and a state in which branch prediction cannot be performed occurs. Therefore, there is a problem that the processing speed of the computer is reduced. The present invention has been made in view of the above points, and provides a branch instruction prediction processing device and a processing method thereof capable of performing branch prediction even when a computer starts execution immediately after power-on and reset. It is intended to be provided.

[0009]

A branch instruction prediction processing device of the present invention, when fetching an instruction following a branch instruction sequentially executed by a computer, determines the branch direction and branch destination of the branch instruction by the branch instruction. In a branch instruction prediction processing device that fetches an instruction immediately following a branch instruction by predicting before the execution result of is known, when the branch instruction is executed, a branch is performed by the address of the branch instruction and the branch instruction. Information indicating whether or not the branch instruction is stored, and the address of the branch destination instruction of the branch instruction, and the contents of the branch prediction table can be explicitly rewritten before the computer executes the program normally. And a branch prediction table change instruction execution unit.

The branch instruction prediction processing method of the present invention records a branch direction of each branch instruction with respect to a branch during program execution, and a branch prediction table for recording the address of the branch instruction and the address of the branch destination instruction. Prepare,
Before the program is executed normally by the computer, preliminary execution for recording the branch direction, the address of the branch instruction and the address of the branch destination instruction in the branch prediction table is performed once or more to execute the regular program. The branch direction for branch prediction at that time, the address of the branch instruction, and the address of the branch target instruction are set in advance in the branch prediction table.

[0011]

In the branch instruction prediction processing apparatus and the processing method thereof according to the present invention, the preparatory program is executed immediately after the power is turned on and after the reset, and when a new job is started. The preparation program may be a regular execution program or a program including a special instruction for changing the branch prediction table. As a result, when the program is to be executed normally, the branch prediction table entry corresponding to the branch instruction to be executed is already set. Therefore, even if the branch instruction is fetched immediately after the power is turned on, the branch prediction is immediately performed and the branch prediction destination instruction is fetched.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of an information processing device including a branch instruction prediction processing device of the present invention. The illustrated information processing apparatus includes an instruction memory 1, an instruction buffer 2, an arithmetic processing unit 3, a register file 4, a memory control unit 5, a data memory 6, an instruction fetch control unit 7, a branch instruction execution unit 8 and a branch instruction prediction processing unit. It consists of nine. Further, the branch instruction prediction processing unit 9 includes a branch prediction table 10 and a branch prediction table change instruction execution unit 11. The instruction memory 1 is
The instruction as shown in FIG. 3 or FIG. 7 is stored.

The instruction buffer 2 is a memory for temporarily storing instructions to be executed. The arithmetic processing unit 3 executes the instruction fetched from the instruction buffer 2. The register file 4 is composed of general-purpose registers and the like. The memory control unit 5 controls data transfer between the data memory 6 and the register file 4. The data memory 6 stores the data processed by the arithmetic processing unit 3. The instruction fetch control unit 7 controls the transfer of instructions from the instruction memory 1 to the instruction buffer 2.
The branch instruction execution unit 8 executes the branch instruction fetched from the instruction buffer 2, and when branching, transfers the instruction at the branch destination address from the instruction memory 1 to the instruction buffer 2. On the other hand, when not branching, the instruction at the address next to the branch instruction is transferred from the instruction memory 1 to the instruction buffer 2.

The branch instruction prediction processing unit 9 predicts the branch direction from the address of the branch instruction before the branch instruction execution unit 8 executes the branch instruction, and causes the instruction fetch unit 7 to fetch the next instruction in advance. The branch prediction table 10 includes a branch destination address, a branch direction prediction,
Stores Valid. The branch prediction table change instruction execution unit 11 can explicitly rewrite the instruction address, the branch destination address, and the branch direction prediction in the branch prediction table 10 by a predetermined instruction executed by the arithmetic processing unit 3.

FIG. 4 is a diagram showing an example of a program for setting the branch prediction table. That is, this figure shows an example of an instruction sequence for writing to the branch prediction table. In this instruction, movi is an instruction to write the value indicated by the second argument into the field of the branch prediction table indicated by the first argument. bp, bpa, and bpt respectively represent the fields of the branch prediction, branch instruction address, and branch prediction address of the branch prediction table. When the arithmetic processing unit 3 recognizes that the instruction is a branch prediction table changing instruction, it notifies the branch prediction table changing instruction executing unit 11 of the branch instruction prediction processing unit 9 of this. In the branch prediction table change instruction execution unit 11,
One entry in which the Valid field is "0" is selected, and the contents of each field of the entry are rewritten.
In this case, if there is no entry in which the Valid field is "0", the one that is valid in the Valid field and is used last is searched, and the contents of each field of the entry are rewritten.

When the branch prediction table is set as shown in FIG. 4 while the branch prediction table is in the state shown in FIG. 2, the branch prediction table is rewritten as shown in FIG. That is, the branch prediction table 10 shown in FIG.
The entry shown in the third line is added. FIG. 5 is a flowchart illustrating a procedure for determining a branch prediction table entry. That is, this flowchart shows the procedure of the method for determining the entry to be written in the branch prediction table and writing it in the branch prediction table. In determining each entry, first, a job program to be accelerated is executed (step S1). Furthermore, a branch instruction is searched during execution (step S2), and if there is a branch instruction, the branch instruction address is recorded (step S3). Further, the result of the branch instruction is collected (step S4), and the branch destination address and branch direction of the branch instruction are recorded (step S4).
5). As described above, for each of the recorded items, the record of the execution of the branch instruction twice each is extracted for the same number of branch instruction addresses as the number of branch prediction table entries from the start of execution (steps S6, S7, S8).

FIG. 6 is an explanatory diagram of a method of determining a branch direction prediction field. As shown in the figure, the value of the upper bit of the branch direction prediction field is "1" if the branch is the first time.
become. If the branch is the second time, the value of the lower bit of the branch direction prediction field is "1". FIG. 7 is a diagram showing an example of an instruction sequence including branch instructions and execution timing according to the present invention. That is, this figure shows the timing when the same instruction as the instruction shown in FIG. 3 is executed after rewriting the branch prediction table as described above. Less than,
The execution timing shown in FIG. 7 will be described with reference to FIG.

First, at the stage f for fetching a branch instruction, the branch prediction table 10 fetches an address from the instruction fetch control unit 7 and compares it with the branch instruction address of each entry in the branch prediction table 10. At this time, the branch instruction address of the branch prediction table 10 has an entry written by the program as described above, and this matches the instruction address currently fetched. Therefore,
After confirming that the Valid field of the entry is "1", the branch direction prediction is read. Since the branch direction prediction is "11" at this time, it is predicted that the branch will be taken. Therefore, the branch destination address of the entry is notified to the branch instruction execution unit 8 together with the branch direction prediction. The branch instruction execution unit 8 notifies the instruction fetch control unit 7 of this address. In the next stage, the instruction address is changed to the branch prediction destination address and the instruction is fetched. In the next stage, the branch instruction condition is judged,
If the above-mentioned branch prediction is correct, the execution is continued as shown in FIG.

[0019]

As described above, according to the branch instruction prediction processing apparatus and the processing method thereof of the present invention, the branch instruction prediction processing apparatus is already executed immediately after the power is turned on and reset, and when a new job is started. Since the branch prediction table corresponding to the branch instruction is set, the branch prediction can be immediately performed when the branch instruction is fetched, and the branch prediction destination instruction can be fetched. Therefore,
Even if the contents of the branch prediction table are all invalid, or if the processor starts a new job and the address of the following instruction is not registered in the branch prediction table, high-speed processing can be started immediately. It will be possible.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an information processing device including a branch instruction prediction processing device of the present invention.

FIG. 2 is an explanatory diagram of a configuration of a branch prediction table.

FIG. 3 is an explanatory diagram of an example of an instruction string including a branch instruction and a conventional execution timing.

FIG. 4 is an explanatory diagram of an example of a program that sets a branch prediction table.

FIG. 5 is a flowchart illustrating a procedure for determining a branch prediction table entry.

FIG. 6 is an explanatory diagram of a method for determining a branch direction prediction field.

FIG. 7 is an explanatory diagram of an example of an instruction sequence including a branch instruction and execution timing according to the present invention.

[Explanation of symbols]

 1 instruction memory 2 instruction buffer 3 arithmetic processing unit 4 register file 5 memory control unit 6 data memory 7 instruction fetch control unit 8 branch instruction execution unit 9 branch instruction prediction processing unit 10 branch prediction table 11 branch prediction table change instruction execution unit

Claims (2)

[Claims] 1. When fetching an instruction subsequent to a branch instruction that is sequentially executed by a computer, the branch direction and branch destination of the branch instruction are predicted before the execution result of the branch instruction is known, so that the branch is executed earlier. In a branch instruction prediction processing device for fetching an instruction following an instruction, when executing the branch instruction, an address of the branch instruction,
A branch prediction table that holds information indicating whether or not a branch was taken by the branch instruction, and the address of the branch destination instruction of the branch instruction, and the branch prediction table before the computer executes the program normally. And a branch prediction table changing instruction execution unit capable of explicitly rewriting the contents of the branch instruction prediction processing apparatus. 2. A branch prediction table for recording the branch direction of each branch instruction and the address of the branch instruction and the address of the branch destination instruction is prepared for the branch at the time of executing the program, and the program is normalized by a computer. Prior to execution, preparatory execution for recording the branch direction, the address of the branch instruction and the address of the branch destination instruction in the branch prediction table is performed one or more times. A branch instruction prediction processing method, wherein a branch direction, a branch instruction address, and a branch target instruction address are preset in the branch prediction table.