JPH06124155A - Keyboard - Google Patents

Abstract

PURPOSE:To realize a function which prevents a ghost key generation at the time of a multiple key. CONSTITUTION:A resistance type key matrix 1 is scanned by a resistance matrix driver 6 which outputs the scanning signal of a CMOS level. The scanned detection signal is converted into digital data by an A/D converter 5. Afterwards, the digital data are compared with threshold data having a hysteresis characteristic, and the turning-ON/OFF of a switch part constituting a switch unit 2 is judged, so that an N-key roll over function can be realized. And also, the threshold data are varied based on the number of the turning-ON of the switch part, so that a noise margin in a normal state can be ensured, and the N-key roll over function can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a keyboard widely used as an input device of an information processing apparatus, and more particularly, to a function of preventing a ghost key that malfunctions as a key that is not turned on when multiple keys are pressed. The present invention relates to a keyboard provided with (N-key rollover function).

[0002]

2. Description of the Related Art Conventionally, in such a keyboard, generation of a ghost key due to multiple keystrokes has been a problem.
Hereinafter, the generation of a ghost key due to this multiple keystroke will be mainly described.

FIG. 8 is a circuit diagram of a conventional keyboard. As shown in FIG. 8, the conventional keyboard has a key matrix 1a in which switchy sections S00 to S97 are arranged in a 10 × 8 matrix, and this key matrix 1a.
The matrix driver 23 that sequentially outputs high levels to the plurality of scanning lines X0 to X9 connected in the row direction via the diode 24 and the plurality of detection lines Y0 to Y7 connected in the column direction of the key matrix 1a. The matrix receiver 22 receives signals, the control unit 4a controls the matrix driver 23 by the signals of the matrix receiver 22, and load resistors RL0 to RL7.

Here, with the high level output from the matrix driver 23 to the scanning line X0 (all other scanning lines are at low level), S00, S10,
If S11 is turned on, the ghost current IG flows in the order of X0 → Y0 → X1 → Y1 → load resistance RL1, as shown in the figure. Therefore, the detection line Y1 rises to a high level, so that a voltage that causes the switch S01 that is not turned on to be turned on is generated. This is the mechanism of ghost key generation.

The function of preventing the occurrence of the above-mentioned ghost key and always confirming the ON state of one switch in the ON order of the switch is called N-key rollover. Conventionally, it is common to mount one diode on each switch instead of row by row.

FIG. 9 is a circuit diagram of a keyboard showing another conventional example. As shown in FIG. 9, this keyboard implements an N-key rollover by mounting a diode 24, and here also a basic circuit is shown. As in the configuration shown in FIG. 8, the configuration includes a key matrix 1a, a matrix driver 23, a matrix receiver 22, a control unit 4a, and load resistors RL0 to RL7. In particular, a diode 24 is mounted in series on each switch section of the key matrix 1a. According to this keyboard, even if S00, S10, and S11 of the switch section are turned on in the state where the matrix driver 23 outputs a high level to X0 (all the other scanning lines are at a low level), S1
The diode 24 mounted at 0 is reverse biased. Therefore, the current does not flow from Y0 to X1, so that Y1 does not go high and no ghost key is generated.

[0007]

In the above-mentioned conventional keyboard, in order to realize the N-key rollover function, one diode must be mounted for each key or each row, so that the number of keys or each row cannot be changed. However, it is difficult to reduce the size of the diode, and the material cost of the diode and the number of mounting work steps increase.

SUMMARY OF THE INVENTION An object of the present invention is to provide a keyboard which easily realizes an N-key rollover function and which is compact and inexpensive.

[0009]

The keyboard of the present invention comprises:
Operational signals of a CMOS level are sequentially output from a resistance type key matrix in which switch units in which resistance elements are connected in series to a switch unit are arranged in a matrix, and a plurality of scanning lines connected in the row direction of the resistance type key matrix. A resistance matrix driver, an A / D converter for receiving an analog signal based on ON / OFF of the switch unit from a plurality of detection lines connected in the column direction of the resistance type key matrix and converting the analog signal into digital data, A resistance matrix driver and a control unit for controlling the A / D converter, the control unit controlling the A / D converter and a group of command words for outputting an operation signal to the resistance matrix driver. The digital data and threshold data A read-only memory for storing a command word group for determining ON / OFF of the switch unit, a random access memory capable of storing / writing the digital data converted by the A / D converter, and the read The A / D converter is provided with a control circuit that reads out a command word group stored in a dedicated memory and generates control information based on each command word, and a calculation circuit that performs a calculation operation in response to the control information. It is configured by connecting the reference voltage to the power supply voltage.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram of a keyboard showing an embodiment of the present invention. As shown in FIG. 1, in the present embodiment, a resistance type key matrix 1, a resistance matrix driver 6 connected to the resistance type key matrix 1, an A / D converter 5, these drivers 6, and an A / D converter. Control unit 4 for controlling 5 and load resistances RL0-R
L7 and. The control unit 4, the resistance matrix driver 6 and the A / D converter 5 form a one-chip microcomputer 3 integrated on one chip. Further, the resistance type key matrix 1 has R00 to R
A switch unit 2 in which 97 resistance elements and S00 to S97 switch units are connected in series is arranged on a 10 × 8 matrix. This resistive key matrix 1
The scanning lines X0 to X9 in the row direction are connected to the resistance matrix driver 6, and the detection lines Y0 to Y7 in the column direction of the resistance type key matrix 1 are connected to the A / D converter 5 and the load resistances RL0 to RL7. Is pulled down to the signal ground (hereinafter, abbreviated as SG). on the other hand,
The control unit 4 includes a ROM 9 in which a command group for controlling the resistance matrix driver 6 and the A / D converter 5 and processing data is written, and a RAM capable of reading and writing at least the data of the A / D converter 5.
10, an ALU 12 for performing various calculations, an input / output channel 7 for interfacing with the A / D converter 5, an output channel 8 for interfacing with the resistance matrix driver 6, and a RAM 10 for reading out command words from the ROM 9. , ALU 12, input / output channel 7, output channel 8 and a control circuit 11 for transmitting / receiving data to / from control lines, and an internal bus 13.
The internal bus 13 is composed of ROM9, RAM10, ALU1.
2, input / output channel 7, output channel 8 and control circuit 11 are connected to each other. The reference voltage VREF of the A / D converter 5 is supplied from the power supply voltage VCC.

FIG. 2 is a block diagram of the A / D converter shown in FIG. As shown in FIG. 2, this A / D converter 5
Constitutes a successive approximation type 8-bit A / D converter.
The 8-input analog signals AN0 to AN7 are selected as 1 input by the analog multiplexer 14 and held by the latch 15. This analog data is the reference voltage VREF and S
While being compared with the value divided by the tap decoder of the series resistor string 17 connected between G, the successive approximation register 18 converts the value into 8-bit digital data. The converted data is stored in the buffer 19. The tap decoder of the series resistor string 17 sets the voltage between the reference voltages VREF and SG to the 8th power of 2 (= 256).
Can be divided into The sequence controller 16 also includes an analog multiplexer 14 and a latch 15.
And the successive approximation register 18 and the buffer 19 are controlled. Data stored in these buffers 19 and signals from the sequence controller 16 are transferred to the input / output channel 7. Moreover, VREF
Is connected to VCC, analog signals AN0 to AN0
The analog data input to AN7 is converted into digital data as represented by the following equation (1).

[0013]

FIG. 3 is a block diagram of the resistance matrix driver shown in FIG. As shown in FIG. 3, the resistance matrix driver 6 includes a sequence controller 21 driven by data from an output channel 8 and a plurality of buffers 20.
And a MOS transistor. In particular, the sequence controller 21 controls the buffer 20 corresponding to the scanning lines X0 to X9 and drives the output circuit composed of MOS transistors. Since this output circuit is composed of CMOS, the high level is equal to VCC and the low level is S.
Equal to G.

The operation of the above circuit will be described below with reference to FIGS.

First, based on the instruction group written in the ROM 9, the resistance matrix driver 6 causes the scanning lines X0 to X9.
Are sequentially set to a high level, and the other scanning signals are set to a low level to output to the resistance type key matrix 1. In synchronization with this scanning signal, one line in the row direction is set to a high level, and the analog multiplexer 14 of the A / D converter 5
Are sequentially selected, and the detection signal levels of the detection lines Y0 to Y7 are sequentially A / D converted. RA of the digital data
Store in M10.

4 (a) to 4 (c) are equivalent circuit diagrams for explaining the operation when the same Y-line multiple keys are tapped in FIG. First, as shown in FIG. 4A, for example, a state in which a high level is output to X0 (signal level: VC
When the switch unit S00 is turned on in C), a detection signal V00 which is determined by the resistance ratio of the resistor R00 connected to S00 and the load resistor RL0 of the Y0 line is output. This detection signal V00 can be expressed by the following equation (2).

[0018]

Here, VCC = 5V, RL0 = 100k
Assuming that Ω and R00 = 10 kΩ, the detection signal is V00.
= 4.55V.

The detection signal converted into digital data by the equation (1) is V00 (digital) = 233.
(= E8h). Further, assuming that all the switch units arranged on the X0 line other than S00 are OFF, the RAM 10 assigned to the detection lines Y0 to Y7 of the X0 line stores E8h only for Y0 and Y1 to Y1.
00h is stored in Y7. The ON / OFF of the switch is determined by comparing the data stored in the RAM 10 with the threshold data set in the procedure described below.

Next, as shown in FIG. 4 (b), assuming that the high level is output to X0 (signal level = VCC) and the switch sections S00 and S10 are turned on, X
Since a low level is output to 1 (signal level: SG), V00 can be expressed by the following equation (3).

[0022]

If R00 = R10 in the above equation (3), the equation (3) is transformed into the following equation (4).

[0024]

Similarly, as shown in FIG. 4C, the O of the switch section (S00 to S90) mounted on the Y0 line is turned on.
Resistor element (R00 to R90)
When the resistance values of all are the same (R00 = R10 = ... = R90), the detection signal V00 at this time can be expressed by the following equation (5).

[0026]

Here, using the above equation (1), (5)
V0 obtained by converting the detection signal V00 of the formula into digital data
When 0 (digital) is calculated, the following equation (6) is obtained.

[0028]

Since there is no term depending on VCC in this equation (6), V00 (digital) is the power supply voltage (VCC).
It turns out that it is constant regardless of.

FIG. 5 is a characteristic diagram of the detected voltage when the same Y-line multiple keys are tapped in FIG. As shown in FIG. 5, this characteristic is shown in FIG. 4 (c), VCC = 5V, RL0 = 100k.
Assuming that Ω and R00 = 10 kΩ, the result of calculating the above-mentioned formula (6) is shown. 8-bit data representing V00 (digital) in hexadecimal is the data stored in the RAM 10. Therefore, all the switches arranged on the Y line are turned on (N in FIG. 5).
= 10) so that the detection voltage V00 (digital) is at a high level, the first threshold data (threshold data for determining whether the switch section is ON → OFF)
To set.

FIG. 6 is an equivalent circuit diagram for multiple keystrokes for explaining the ghost key generation pattern in FIG.
As shown in FIG. 6, this circuit is in a state in which a high level is output to X0 (signal level: VCC) and the switch unit S
An equivalent circuit is shown when 00, S10, and S11 are ON. Even in this state, the detection voltage of Y1 (V01)
It is possible to prevent the generation of ghost keys by setting the second threshold data (threshold data for judging whether the switch section is from OFF to ON) as shown in FIG. is there.

As described above, even if all the switch parts arranged on the same line are turned on, the first threshold data must have a value as low as possible in order for the detection voltage to have a high level. The second threshold data that prevents ghost keys should be as high as possible. Therefore, the threshold is provided with a hysteresis characteristic, and the first threshold data and the second threshold data are set separately. That is, the first threshold data (1
1: 0.21V when VCC = 5V) and second threshold data (17: 0.3 when VCC = 5V)
3V) indicates the threshold set by the method described above.

Since the threshold described above is considerably lower than the TTL level and the CMOS level which are generally widely used, it can be seen that it is necessary to sufficiently consider noise countermeasures. In particular, the second threshold data for discriminating between OFF and ON of the switch unit is about 1/6 as compared with the high level threshold (2V) of TTL, and the switch unit which is not turned ON due to insufficient noise margin. There is a high possibility that will be erroneously recognized as if it is turned on due to noise.

FIG. 7 is a detection voltage characteristic diagram in which threshold data is set to the detection voltage characteristic at the same Y line multiple keystroke in FIG.

Conventionally, the keyboard has an O switch
In order to determine N / OFF, a means corresponding to each switch and storing the state (ON / OFF) of each switch is provided, but the keyboard of this embodiment similarly determines the state of the switch section. After executing, change the status of each switch to R
It is possible to store the data in the AM 10 and selectively use the first threshold data and the second threshold data depending on the state of each switch unit, and manage the number of switches ON on the same Y line.

Therefore, as shown in FIG. 7, in this detection voltage characteristic, at least the second threshold data shown in FIG. 5 is made variable data according to the number of key ONs,
When the number of key ONs is small, the level of the second threshold data is increased. For example, for each Y line, an up / down counter corresponding to the number of ONs of the switch unit is set in the RAM 10 by 1 byte (total 8 bytes), and is incremented by 1 each time the switch unit is turned ON for each Y line. The number of switches ON can be determined by setting -1 each time the switch section is turned OFF. Therefore, when the switch section of the first key is turned on, the second threshold (1
90: When VCC = 5V, only data that exceeds 3.7V is valid, and when the switch part of the second key is turned on, the second threshold (90: VCC = 5V, 1.7V) Only the data that exceeds) is valid. Normal,
Assuming that the number of switches that turn on the same Y line in the state of using the keyboard is at most 1 or 2 keys, at least the noise margin in the state of normal use is TT.
It can be made to be almost equal to the L level, and even if all the switch parts of the same Y line are turned ON (N = 10), the N key rollover function is guaranteed because it does not fall below the first threshold. .

[0037]

As described above, in the keyboard of the present invention, the resistance matrix is scanned by the resistance matrix driver that outputs a CMOS level scanning signal, and the detection signal is converted into digital data by the A / D converter. By comparing with threshold data having a hysteresis characteristic and determining ON / OFF of the switch unit, there is an effect that the N key rollover function can be easily realized, and the size and cost can be reduced. Further, the present invention has an effect that the N-key rollover function can be realized while securing the noise margin in the normal use state by making the threshold data variable depending on the number of the switch sections that are turned on. .

[Brief description of drawings]

FIG. 1 is a circuit diagram of a keyboard showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of the A / D converter shown in FIG.

FIG. 3 is a configuration diagram of a resistance matrix driver shown in FIG.

FIG. 4 is an equivalent circuit diagram for explaining the operation when the same Y-line multiple keys are tapped in FIG.

5 is a characteristic diagram of a detected voltage when multiple keys are tapped on the same Y line in FIG.

6 is an equivalent circuit diagram at the time of multiple keystrokes for explaining the ghost key generation pattern in FIG.

7 is a detection voltage characteristic diagram in which threshold data is set to the detection voltage characteristic at the time of multiple keystrokes on the same Y line in FIG.

FIG. 8 is a circuit diagram of a keyboard showing a conventional example.

FIG. 9 is a circuit diagram of a keyboard showing another conventional example.

[Explanation of symbols]

 1 resistance type key matrix 2 switch unit 3 one-chip microcomputer 4 control unit 5 A / D converter 6 resistance matrix driver 7 input / output channel 8 output channel 9 ROM 10 RAM 11 control circuit 12 ALU 13 internal bus 14 analog multiplexer 15 latch 16, 21 sequence controller 17 series resistor string 18 successive approximation register 19, 20 buffer

Claims (4)

[Claims] 1. A resistance-type key matrix in which switch units in which resistance elements are connected in series to a switch unit are arranged in a matrix, and a plurality of scanning lines connected in the row direction of the resistance-type key matrix are sequentially arranged in a CMOS level. A / A that receives an analog signal based on ON / OFF of the switch unit from a resistance matrix driver that outputs an operation signal and a plurality of detection lines connected in the column direction of the resistance type key matrix, and converts the analog signal into digital data. A D converter and a control unit that controls the resistance matrix driver and the A / D converter, and the control unit controls a group of command words that outputs an operation signal to the resistance matrix driver and the A / D converter. And for A / D converted digital data and threshold Compare the data, and switch the O
A read-only memory for storing a command word group for determining N / OFF, a random access memory for storing / writing the digital data converted by the A / D converter, and a read-only memory A control circuit that reads out a group of command words that are generated and generates control information based on each command word; and a calculation circuit that performs a calculation operation in response to the control information, and supplies the reference voltage of the A / D converter as a power supply. A keyboard characterized by being connected to a voltage. 2. The keyboard according to claim 1, wherein the control unit, the resistance matrix driver, and the A / D converter constitute a one-chip microcomputer integrated on one chip. 3. The control unit has an output channel and an input / output channel for connecting to the resistance matrix driver and the A / D converter, respectively, and the output channel and the input / output channel are connected to the read-only memory or the like. The keyboard according to claim 1, wherein the keyboard is connected via an internal bus. 4. The read-only memory of the control unit includes, as the threshold data, first threshold data for judging a change from ON to OFF of the switch unit and from OFF to ON of the switch unit. 2. The keyboard according to claim 1, further comprising: a second threshold data for determining a change in the switch, having a hysteresis characteristic, and changing the second threshold based on the number of the switch units turned on.