KR101391670B1 - Key input device and keyboard having the same - Google Patents

Abstract

Disclosed are a key input device, which detects a switching operation within a switching matrix where a plurality of switches such as a keyboard are provided, and a keyboard having the same. The key input device is connected to a key matrix including a plurality of switches. The key input device includes a column scanning controller and a row scanning controller. The column scanning controller includes a plurality of column switch units corresponding to column scanning lines one-to-one, and (i) selectively receives one of a first input voltage (Vup) and a second input voltage (VA) in each column in normal scanning mode and (ii) performs a column scanning operation for each mode according to a switching operation of a column switch unit, which receives holding voltage (Vh), in power saving mode, according to column scanning signals and enable signals (EN) of a CPU. The row scanning controller is synchronized with a column scanning signal of the column scanning controller in the normal scanning mode to perform row scanning according to row scanning signals of the CPU, and is operated in the power saving mode according to EN. The column scanning controller includes a first variable resistor, which is arranged between reference voltage and each of the column switch units and varies a first input voltage (Vup) and supplies the varied input voltage to each of the column switch units.

Description

[0001] KEY INPUT DEVICE AND KEYBOARD HAVING THE SAME [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a key input device and a keyboard including the same, and more particularly, to a key input device for detecting a switching operation in a switching matrix having a plurality of switches such as a keyboard and a keyboard including the same.

Generally, a keyboard in a computer system is one of the primary means for receiving input from the outside. In many computer systems, data entry into the central processing system is done by keying on the keyboard.

The keyboard usually has a keyboard interface including a control organization for controlling input information from a key. The keyboard interface includes a scan out line output from a micom and a scan out line from a micom. A line (scan in line) is connected to the system interface.

The system interface transmits the status signal to the keyboard interface through the scan out line, and the scan in line and the scan out line are connected according to the key input to determine the key input.

The above-described input method has a problem that a keyboard is called a ghost key or a phantom key. The ghost key phenomenon occurs when three key buttons are simultaneously pressed on the keyboard, It is a phenomenon that a button is recognized as being pressed.

Such a ghost key phenomenon can be recognized by pressing three keys at a time even if the key is pressed one by one in the case of a person typing very quickly, so that an input of a key not pressed by the user occurs.

In order to prevent this, when the third key pressed after the second pressed key is detected, the method is used in which the key is not pressed.

In addition, when three key combinations such as a shift key, a control key, and an alt key are operated simultaneously, the key arrangement is made special so that even if three key buttons are pressed simultaneously, Is not displayed.

However, even if the above-described method is used, there is a problem in that a program such as a game can not be operated when a combination of three or more general key buttons is pressed instead of a specific key button. That is, in a game played on a PC, in the case of a shooting game, three key presses are required in combination with a general key, not a combination with a special key such as a control key (Ctrl) or alt key (Alt).

For example, if you want to fire with 'W' moving upwards, 'E' moving left, 'P' launching and so on, moving upwards left, three key buttons must be pressed at the same time.

However, with the conventional ghost key removal method, three keys can be disabled.

1 is a block diagram for explaining a general key input device for ghost key removal.

Referring to FIG. 1, a plurality of switching devices S1... Each including a resistor 6 and a switching device 5 connected in series are constituted in the key matrix 3. Here, 49 switching devices are manufactured.

One end of each of the switching devices S1 ... in the key matrix 3 is connected to one of the row scan lines X10 to X16 (or X line), and the other end is connected to the column scan lines Y30- Y36) (or Y line).

One end of each of the row syllables X10 to X16 is connected to the row decoder 2.

One end of each of the column scan lines Y30 to Y36 is connected to the column decoder 1 and the other end is connected to the selector 7 of the detection circuit 4 (or a data selector having an analog switching system).

The column decoder 1 serves to open one line selected from the column scan lines Y30 to Y36 and to apply a predetermined constant voltage to the remaining lines. Here, the constant voltage may be set to 3V.

An overcurrent preventing resistor r4 and a reverse current preventing diode Di and a zener diode ZDi for providing a constant voltage are provided between one end of each of the column decoder 1 and the column scanning lines Y30 to Y36. Here, in order to output the voltage from the column decoder 1 and the comparison voltage of the voltage comparator 8, a large amount of expensive diodes must be used as shown in Fig. It can be seen that the diode connected to the column decoder 1 must use a large amount as many as the number of switches.

The other end of each of the column scan lines Y30 to Y36 is connected to the selector 7. [ The selector 7 selects one of the column scan lines Y30 to Y36 successively and connects it to the voltage comparator 8 which is a voltage detecting circuit for the switching operation.

The column decoder 1 and the selector 7 perform a scanning operation on the column scanning lines Y30 to Y36 in synchronization with the clock pulse. Therefore, a line selected from the column scanning lines Y30 to Y36 by the column decoder 1, for example, the column scanning line Y30, is simultaneously selected by the selector 7 and connected to the voltage comparator 8. [

On the other hand, an appropriate voltage is applied to the input terminal N1 of the voltage comparator 8 from the power supply Vcc (for example, 5 V) through the impedance R. [ The voltages of the row sine selected by the selector 7 are also applied to the terminal N1.

The resistor r3 for limiting the detection reference voltage (for example, 2.5 to 3.0 V) and the zener diode ZDi are connected to the other input terminal N2. Here, the detection reference voltage is set to 2.6V.

One end of each of the row syllables X10 to X16 is connected to the row decoder 2. The row decoder 2 performs a scanning operation in synchronization with the scanning operation of the selector 7 and the column decoder 1 as described above and also sets the voltage of the selected line from the row scan lines X10 to X16 to OV While leaving the remaining lines open.

When one column scan line Y30 is selected by the selector 7 and the column decoder 1 and one column scan line X10 is selected by the row decoder 2, Is maintained at 5V while the voltage of the remaining column scanning lines Y31 to Y36 is maintained at 3V.

On the other hand, when the row sine X10 is selected by the row decoder 2, the voltage of the row sine X10 is set to OV and the remaining row sine X11 to X16 are opened.

In such a situation, when the switch S1 is pressed, the column scan line Y30 and the row scan line X10 are connected, and the voltage of the column scan line Y30 held at VCC (5V) drops to OV, A voltage is applied to the input terminal N1 of the voltage comparator 8. [

Strictly speaking, the voltage of the input terminal N2 does not drop to the full OV. This is because the resistance component r of the resistor 6 and the internal resistance component of the column scan line Y30 are present in the switching device S. [ However, when the resistance component r of the resistor 6 is set to a value smaller than that of the impedance R, for example, a value of 1/10 of R, the input voltage to the input terminal N1 is regarded as OV .

This is based on the fact that the value of the impedance R and the resistance component r of the resistor 6 can be varied independently of the present invention as described below.

Therefore, in the input detecting apparatus having such a configuration, the detection voltage of the row sine to which the switching device is connected by pressing only one switch, for example, the switch S1, appears as OV, so that the fact can be detected. This is because the detection voltage OV is lower than the detection reference voltage of 2.6V.

On the other hand, if the other switch devices S2 to S4 are erroneously pressed at the same time without depressing the switch S1, the input voltage to the input terminal N1 of the voltage comparator 8 appears to be at least 3V or more.

Therefore, the occurrence of leakage passing signal current can be detected.

Therefore, it is possible to prevent an error such that the leakage signal voltage is generated by mistakenly depressing the switching devices S1 to S4 instead of the switching device S1, as if the switching device S1 was pressed improperly.

However, when the desired switching device and a plurality of other switching devices are simultaneously pressed, the leakage passing signal voltage is generated through the diode connected to the other switching device, so that the detection voltage is increased.

Therefore, there arises a problem that the operation of the desired switching device can not be detected.

The leakage signal voltage in the above-described situation will be described below.

In FIG. 1, when the switching devices S2 to S8 are erroneously pressed at the same time as the desired switching device S1, the leakage passing signal voltage V8 indicated by Equation 1 below is detected as about 1.9V.

[Equation 1]

This voltage is much smaller than the detection reference voltage 2.6V to be discriminated.

Therefore, the operation of pressing the switch S1 can be accurately detected.

For example, the switching device S1 and the switching devices S3 to S11, that is, a total of 10 switches, are closed at the same time by pressing the desired switching device S1 and nine other switching devices at the same time, The leakage pass signal voltage V10 is detected as about 2.05V.

[Equation 2]

This voltage is much smaller than the detection reference voltage (2.6V) to be discriminated. Therefore, the operation of pressing the switch S1 can be accurately detected.

However, since the conventional method of removing the ghost key phenomenon requires a separate column decoder and a selector among the array of the switch matrix, the area of the system is increased and the production cost of the product is increased. Also, there is a problem in commercialization because there is no definition of the power saving mode.

Further, since a large number of the common diodes Di and the constant voltage supply Zener diodes ZDi have to be used as the number of the column scanning lines Y30 to Y36 on the switch array, there is a problem that the manufacturing cost is increased, .

In consideration of this point, Patent Registration No. 10-0971580 discloses a key input device capable of controlling a key matrix by using a switch having a simple configuration to eliminate a ghost key phenomenon, operate in a power saving mode, .

However, when the keyboard employing such a key input device includes a membrane key matrix printed with carbon, the printing tolerance of the carbon increases and the resistance variation increases. If the resistance variation increases, there is a problem of reducing the resistance detection efficiency. For example, when the keyboard is pressed with a weak keystroke, the touch position of the key button is not normally detected.

Korean Patent No. 10-0971580 Korean Patent Publication No. 2005-0072493 US registered patent US 7,256,768 B2

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to provide a key input device that is easy to mass- The present invention provides a key input device capable of detecting the position of a key button smoothly even if a resistance variation occurs.

Another object of the present invention is to provide a keyboard including the key input device.

In order to realize the object of the present invention described above, a key input device according to an embodiment is connected to a key matrix including a plurality of switches connected to column scan lines and row scan lines. The key input device includes a column scan control device and a row scan control device. The column scan control device includes a plurality of column switch units corresponding one-to-one to the column scan lines. The column scan control device includes: (i) (Ii) receiving a holding voltage (Vh) in a power saving mode, and performing a column scanning operation in accordance with the switching operation of the column switch unit . Wherein said row scan controlling device performs row scanning in accordance with a row scan signal of said CPU in synchronization with a column scan signal of said column scan control device in said normal scan mode and controls said power saving mode in accordance with said enable signal . The column scan control apparatus includes a reference voltage and a first variable resistor which is disposed between each of the column switch units and varies the first input voltage Vup to provide the reference voltage to each of the column switch units.
In one embodiment, the thermal scan control apparatus may include a thermal control, a plurality of switch units, a power supply, and a voltage comparator. The column controller outputs a column scan signal and an enable signal EN under the control of the CPU. The switch units are connected in a one-to-one correspondence to the column scan lines to perform column scanning by switching the column scan lines selected by the column scan signal of the column control unit and the remaining unselected column scan lines according to the input voltage. Wherein the power supply unit is selectively enabled and disabled according to an enable signal of the thermal control unit to supply the first input voltage Vup, the second input voltage VA, and the holding voltage Vh to the normal scan mode And selectively outputs to the switch unit according to the power saving mode. Wherein the voltage comparator is enabled in the normal scan mode by being enabled according to an enable signal of the thermal controller and is disabled in accordance with an enable signal of the thermal controller to operate in the power saving mode, R1, R2) and the first input voltage (Vup), and outputs the result to the CPU.

According to another aspect of the present invention, there is provided a keyboard according to an embodiment of the present invention includes a key matrix including a plurality of switches connected to column scan lines and row scan lines, and a key input device connected to the key matrix . The key input device includes a column scan control device and a row scan control device. The column scan control device includes a plurality of column switch units corresponding one-to-one to the column scan lines. The column scan control device includes: (i) (Ii) receiving a holding voltage (Vh) in a power saving mode, and performing a column scanning operation in accordance with the switching operation of the column switch unit . Wherein said row scan controlling device performs row scanning in accordance with a row scan signal of said CPU in synchronization with a column scan signal of said column scan control device in said normal scan mode and controls said power saving mode in accordance with said enable signal . The column scan control apparatus includes a reference voltage and a first variable resistor which is disposed between each of the column switch units and varies the first input voltage Vup to provide the reference voltage to each of the column switch units.

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In one embodiment, the key matrix may be a membrane switch sheet.

In one embodiment, the key matrix may be a force sensing resister (FSR) sheet.

In one embodiment, the keyboard may further include an external resistor, one end of which is connected to the output terminal of the thermal switch, and an external switch, one end of which is connected to the other end of the external resistor and the other end thereof is grounded.

According to the key input device and the keyboard including the key input device, the first input voltage Vup is varied and provided to the thermal switch parts, so that even if the resistance deviation increases, the printing tolerance increases in the membrane key matrix printed with carbon, Can be prevented from decreasing. Accordingly, the key input device according to the present invention can be used for a key matrix having a small resistance or a key matrix having a large resistance.

1 is a block diagram for explaining a general key input device for ghost key removal.
2 is a block diagram illustrating a key input device according to an embodiment of the present invention.
3 is a block diagram for explaining an example of the column scan control device shown in FIG.
Fig. 4 is a block diagram for explaining an example of the row scan controlling apparatus shown in Fig. 2. Fig.
5A is a schematic diagram for explaining voltages applied to the voltage comparator of the column scan control device corresponding to the key matrix shown in FIG.
FIG. 5B is a waveform diagram for explaining scan signals applied to the key matrix shown in FIG. 5A.
5C is a waveform diagram of the area A shown in FIG. 5B enlarged.
6A is a circuit diagram for explaining current flow when three switches are pressed.
Fig. 6B is an equivalent circuit diagram in which the circuit shown in Fig. 6A is simplified.
7A is a circuit diagram for explaining current flow when six switches are pressed.
Fig. 7B is an equivalent circuit diagram in which the circuit shown in Fig. 7A is simplified.
8 is a circuit diagram for explaining a power saving mode in operation of FIG.
9 is a block diagram for explaining an example of the power supply unit shown in FIG.
10 is a block diagram for explaining another example of the power supply unit shown in FIG.
11 is a block diagram for explaining another example of the column scan control device shown in Fig.
12 is a block diagram for explaining the analog-digital converter shown in FIG.
13 is a block diagram for explaining a keyboard according to an embodiment of the present invention.
14 is a block diagram for explaining a keyboard according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail with reference to the accompanying drawings. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. The singular expressions include plural expressions unless the context clearly dictates otherwise.

In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Also, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

2 is a block diagram illustrating a key input device according to an embodiment of the present invention.

2, the key input device according to the embodiment of the present invention includes a key matrix 12, a seventh column Y30 to Y36, and a seventh column Y30 to Y36, each of which includes seven columns Y30 to Y36 and seven rows X10 to X16, And a row scanning control device 13 connected to the column scanning control device 11 and the seventh row X10 to X16 for controlling the column scanning of the key scanning to control the row scanning of the key scanning. The column scan control device 11 and the row scan control device 13 may be implemented in an integrated circuit (IC) type.

The key input device may further include a CPU 10 for applying a control signal for controlling the column scan control device 11 and the row scan control device 13. The CPU 10 can generally use a microcontroller unit.

The key matrix 12 includes a plurality of switching devices S1, S2, S3, S4,... Each including a switching device 121 and a switching resistor 122 connected in series. In the present embodiment, 49 switching devices can be manufactured since 7 rows and 7 columns. The key matrix 12 may be a key matrix including a membrane sensor or a key matrix including a force sensing resister (FSR) sensor.

One end of each switching device S1, S2, S3, ... is connected to one column scan line of a plurality of column scan lines X10 to X16, and the other end thereof is connected to a plurality of column scan lines Y30- Y36) is connected to one of the rows of rows.

One end of the row scan lines X10 to X16 is connected to the row scan control device 13 and one end of the column scan lines Y30 to Y36 is connected to the column scan control device 11. [

The column scan control device 11 serves to open one column scan line selected from the column scan lines Y30 to Y36 while applying a predetermined constant voltage to the remaining column scan lines. In this embodiment, the constant voltage may be, for example, 3V.

In addition, the column scan control device 11 sequentially selects one of the column scan lines to constitute a voltage comparator (reference numeral 16 in Fig. 3) which is a voltage detection circuit for a switching operation.

The column scan control device 11 performs a scanning operation on the column scan lines Y30 to Y36 under the control of the CPU 10. One end of each of the column scan lines X10 to X16 is connected to the column And performs a scanning operation in synchronization with the scanning operation of the column scanning control device 11. [ In addition, the row scan control device 13 sets the voltage of the selected row line out of the row line drivers X10 to X16 to OV, and controls the remaining row line drivers to be in the open state.

3 is a block diagram for explaining an example of the column scan control device 11 shown in Fig.

2 and 3, the column scan control device 11 includes a column control unit 14, a power supply unit 15, a pull-up resistor Rh, a first variable resistor R0, a plurality of column switch units, A buffer B, a fixed resistor R2, a second variable resistor R1 and a voltage comparator 16. [

The column controller 14 outputs a column scan signal and an enable signal EN under the control of the CPU 10. [

The power supply unit 15 and the voltage comparator 16 are enabled or disabled according to the enable signal EN of the thermal control unit 14. [

The pull-up resistor Rh is disposed between the reference voltage VCC and each of the thermal switch parts to provide a holding voltage Vh to each of the thermal switch parts.

The first variable resistor R0 is disposed between the reference voltage VCC and each of the thermal switch units and is varied by a third adjustment value adj2 provided by the thermal controller 14, (Vup) to each of the thermal switch parts.

The thermal switch units include a first column switch unit 17a to a seventh column switch unit 17g and are connected to one column scan line selected by the column scan signal of the column control unit 14 and six column scan lines Each column scan line is switched to perform a column scan operation. In FIG. 3, only the first column switch portion 17a and the seventh column switch portion 17g are shown, and the remaining second to sixth column switch portions are omitted.

The buffer B temporarily stores the first input voltage Vup for a predetermined time and provides the CPU 10 with an interrupt signal INT. Accordingly, the CPU 10 receives the interrupt signal INT from the buffer B and exits from the power save mode, operates in the normal scan mode, which is the general key input detection state, And recognizes the pressed key value by grasping the position of the key pressed by the user.

One end of the fixed resistor R2 is commonly connected to the input terminal of each of the thermal switch units to which the second input voltage VA is applied and the other end thereof is connected to one end of the second variable resistor R1, And are commonly connected to negative polarity terminals.

One end of the second variable resistor R1 is commonly connected to the other end of the fixed resistor R2 and the negative terminal of the voltage comparator 16. [

The fixed resistor R2 and the second variable resistor R1 are connected in parallel to each other by a variable voltage Vref generated by voltage division of a second input voltage VA input to each of the thermal switch units 17a to 17g, To the negative terminal of the comparator 16.

The voltage comparator 16 is connected to each of the thermal switch units 17a to 17g and is enabled by an enable signal EN. The voltage comparator 16 compares the first input voltage Vup applied to each of the thermal switch units with the variable voltage Vref and outputs the comparison result to the CPU 10. In the present embodiment, the voltage comparator 16 has a hysteresis characteristic in order to reduce the noise margin. That is, it reduces malfunction due to noise of the input signal. This hysteresis comparator may include a Schmitt trigger.

A first external resistor Rx0 to a seventh external resistor Rx6 and a first external switch SW0 are provided between the output terminals of the first to seventh column switch parts 17a to 17g and the column scan lines Y30 to Y36, ) To the seventh external switch SW6. The first to seventh external resistors Rx0 to Rx6 and the first to seventh external switches SW0 to SW6 may be arranged in a column scan control device 11 provided in IC form. The first to seventh external resistors Rx0 to Rx6 and the first to seventh external switches SW0 to SW6 may be disposed outside the column scan control device 11 provided in IC form have.

One end of each of the first to seventh external resistors Rx0 to Rx6 is commonly connected to the output ends of the first to seventh column switches 17a to 17g and the column scan lines Y30 to Y36, Are connected to the first to seventh external switches SW0 to SW6. Each of the first to seventh external switches SW0 to SW6 is turned on or off in response to the switch signals SS0 to SS6 provided by the column controller 14. [ For example, when the first external switch SW0 is turned off by the first switch signal SS0, the first external switch SW0 floats, and the first external switch SW0 is turned on by the first switch signal SS0 SW0 are turned on, the other end of the first external resistor Rx0 is grounded.

The first to seventh external resistors Rx0 to Rx6 are connected to an application circuit disposed outside the IC so that when the FSR sensor or the membrane sensor has a large on-resistance value that the IC can not accommodate, And adjusts the resistance value of the seventh external resistors Rx0 to Rx6 to adjust the range of the first input voltage Vup by the key pressing applied to the input terminal of the voltage comparator 16. [ Here, a large on-resistance value at a level that the IC can not accommodate can be generated by key depression.

In the power saving mode, the first to seventh external switches SW0 to SW6 are turned off so that the reference voltage VCC, the first variable resistor R0, the first to seventh external resistors Rx0 to Rx6), the first to seventh external switches SW0 to SW6, and the ground GND, or the reference voltage VCC, the pull-up resistor Rh, The seventh external resistors Rx0 to Rx6, the first to seventh external switches SW0 to SW6, and the ground GND. Thus, it is possible to prevent the IC from unnecessarily consuming current.

As described above, the printing tolerance increases in the membrane key matrix printed with carbon, and the first input voltage Vup is varied to provide the same to the thermal switch units even if the resistance deviation increases, thereby preventing the resistance detection efficiency from being reduced can do. Therefore, the key input device according to the present invention can be used for a key matrix having a small resistance or a key matrix having a large resistance.

Fig. 4 is a block diagram for explaining an example of the row scan controlling device 13 shown in Fig.

2 and 4, the row scanning control device 13 includes a row control unit 18 for controlling the key matrix 12 to perform a row scanning operation in response to a row scanning signal under the control of the CPU 10, And seven switches 19 .... connected to seven rows to perform row scanning by the row scanning signals SC0 to SC6 from the control unit 18. [ In Fig. 4, only the switch 19 in the first row and the switch in the last row of each switch are shown, and the switches in the remaining rows are omitted. In Fig. 4, the switch 19 may comprise an NMOS transistor. The NMOS transistor is turned on when a high voltage is applied through the gate and turned off when a low voltage is applied.

The row control unit 18 sequentially outputs the row scan signals SC0 to SC6 to the switches 19 under the control of the CPU 10. [ At this time, the on-resistance value of the switch 19 of the selected row among the seven rows of switches 19 .... is set to 0 ohm (ohm) according to the row scan signal, the switch of the remaining row is opened, And performs a row scan operation in synchronization with the operation.

In the normal scan mode, the row control unit 18 sequentially controls the row scan lines to 0V under the control of the CPU 10. In the power save mode, the row scan lines are all connected to 0V Function.

FIG. 5A is a circuit diagram for explaining the column scan control device 11 and the column scan control device 13 connected to the key matrix 12 shown in FIG. 5B is a waveform diagram for explaining scan signals applied to the key matrix 12 shown in FIG. 5A. 5C is a waveform diagram of the area A shown in FIG. 5B enlarged. In Fig. 5A, reference numeral Rh denotes a pull-up resistor, R0 denotes a first variable resistor, and 16 denotes a voltage comparator. In this embodiment, the power source voltage VCC is 5.0 V, the second input voltage VA outputted from the power supply unit 15 (shown in FIG. 3) is 3.0 V, the first variable resistor R0 is a resistor having a maximum of 100KOhm Value. ≪ / RTI > In some cases, the first variable resistor R0 can have a maximum of 200KOhm.

5A to 5C, as the scan operation is started in the normal scan mode, the ON level voltages Scan Out0 to Scan Outn are sequentially applied to the gates of the NMOS transistors included in the scan control device 13 . Thus, the NMOS transistors are sequentially turned on.

The first input voltage Vup is sequentially applied to the column scan lines and the second input voltage VA is applied to the column scan lines to which the first input voltage Vup is not applied during the period in which the NMOS transistors are turned on. Is applied. The first input voltage Vup applied to the column scan line is applied to the positive terminal of the voltage comparator 16 and the variable voltage Vref is applied to the negative terminal of the voltage comparator 16. [

The voltage comparator 16 compares the first input voltage Vup with the variable voltage Vref to determine whether a key input has been generated, and outputs a signal of a high level or a low level.

For example, if the first input voltage Vup is higher than the variable voltage Vref, the voltage comparator 16 outputs a high-level signal. On the other hand, if the first input voltage Vup is lower than or equal to the variable voltage Vref, the voltage comparator 16 can output a low level signal.

When the key input is generated, the first input voltage Vup is lower than the variable voltage Vref, and when the key input is not generated, the first input voltage Vup is equivalent to the variable voltage Vref.

On the other hand, if there is no key input of the user's key matrix for a predetermined time, the power saving mode is entered. When entering the power saving mode, the holding voltage Vh is applied to all of the column scan lines, and the voltage of the column scan lines is maintained at the level of 5V. All the NMOS transistors of the row scan control device 13 are turned on to keep the row scan lines at 0V.

On the other hand, when a key input is generated by the user in the power saving mode, the row scan line and the column scan line corresponding to the switching element corresponding to the key input maintain 0V. Since the specific column scan line maintains 0 V, the holding voltage Vh of the column scan line has a value near 0 V, that is, a low level. The holding voltage Vh of the low level is applied to the buffer B shown in Fig. 3 and the buffer B outputs the interrupt signal INT to the CPU 10 (shown in Fig. 3) Up controller 11 and the row scanning control device 13. [

Hereinafter, the operations of the column scan control device 11 of FIG. 3 and the row scan control device 13 of FIG. 4 will be described in more detail.

3, the column control unit 14 applies an enable signal EN to the first to seventh column switch units 17a to 17g in response to the column scan signal of the CPU 10, The seventh column switch units 17a to 17g are enabled. The column controller 14 applies each of the first to sixth select signals SL0 to SL6 sequentially to the first to seventh column switch units 17a to 17g to sequentially output the first to seventh columns And selects one of the switch portions 17a to 17g.

Each of the first to seventh column switch units 17a to 17g switches to apply the first input voltage Vup to the selected column scan line in response to the first to sixth select signals SL0 to SL6, And switches the second input voltage VA to be applied to the unselected column scan line.

Each of the first through seventh column switch units 17a through 17g is connected to the power supply unit 15 (i.e., the first power supply unit 15a, the second power supply unit 15b, In the normal scan mode in which the first to sixth select signals SL0 to SL6 and the enable signal EN are applied from the column controller 14, Or the second input voltage VA, and performs a switching operation to receive the holding voltage Vh in the power saving mode. The power supply unit 15 may vary the second input voltage VA in response to the first adjustment value adj0 of the thermal controller 14 and output the second input voltage VA.

The voltage comparator 16 compares the variable voltage Vref with the first input voltage Vup to determine whether a key input by the switch S1 has occurred. For example, when a key input is generated by the switch S1, the first input voltage Vup input to the voltage comparator 16 is lower than the variable voltage Vref. On the other hand, if no key input is generated by the switch S1, the first input voltage Vup input to the voltage comparator 16 is a voltage equivalent to the power supply voltage VCC. Here, the ratio of each resistance value is determined so that the first input voltage Vup is generated to be lower than the variable voltage Vref.

That is, the resistance value of the first variable resistor R0 of FIG. 3 and the resistance value of the switching resistor 122 of FIG. 2 are adjusted to determine the first input voltage Vup input to the voltage comparator 16 And adjusts the resistance value of the fixed resistor R2 and the resistance value of the second variable resistor R1 having the fixed value in Fig. 3 to determine the variable voltage Vref. Here, in the case of the voltage comparator 8 of FIG. 1 of the existing system, an expensive high-power diode and resistors for limiting the current of the diodes must be used to generate a voltage.

However, according to the present embodiment, a fixed resistor R2 having a fixed value and a second variable resistor R1 having a variable value are simply adjusted to generate a variable voltage Vref of the voltage comparator 16 .

Hereinafter, the relationship between the resistors and the voltage will be described in more detail using the following equation.

The power supply voltage VCC is set to 5.0 V, the first variable resistor R0 is set to 10 KOHm, the switching resistance 122 is set to 7 KOHm (expressed as r in the following equation) and the second input voltage VA is set to 3.0 V, When the on-resistance value of the switch 19 shown in Fig. 4 is set to 0 Ohm (which is not 0 ohm in practice but can be ignored as a relatively small resistance value), when a row and column scan occurs, The first input voltage Vup1 is expressed by Equation 3 below.

[Equation 3]

At this time, the second input voltage VA of the power supply unit 15 is set to 2.5 V (Vref) of the voltage comparator 16 using the ratio of the fixed resistor R2 and the second variable resistor R1 Since the first input voltage Vup1 is less than 2.5V, it can be recognized that the corresponding key S1 is pressed.

If no key is pressed, the voltage of the first input voltage Vup1 is close to the power supply voltage VCC, so that the voltage of the first input voltage Vup1 is higher than the variable voltage Vref and the key button is not pressed.

Therefore, the power supply voltage VCC is the highest voltage, the second input voltage VA of the power supply unit 15 is the intermediate voltage, and the variable voltage Vref is the lowest voltage among the three voltages. The following equation (4) is satisfied.

[Equation 4]

VCC> VA> Vref

In addition, when one or more key buttons are pressed, the first input voltage Vup always has the relationship expressed by the following equation (5).

[Equation 5]

Vref> Vup

In addition, when no key button is depressed, the first input voltage Vup always has the relationship expressed by the following equation (6).

[Equation 6]

Vref < Vup, Vup = VCC

In addition, according to the present invention, even if a certain number of key buttons for generating a ghost key phenomenon are simultaneously pressed, the relational expressions (4) to (6) are maintained so that the unpressed key button can not be recognized as a key pressed by the ghost key phenomenon It is necessary to maintain a system that can not be depressed even if the ten key buttons are pressed in combination to cause the ghost key phenomenon at the same time.

6A is a circuit diagram for explaining a touch panel when three switches are simultaneously pressed. 6B is an equivalent circuit diagram for explaining a touch panel when three switches are simultaneously pressed. In particular, it will be described that when the three points are depressed and the first switch is not depressed, the first switch is not depressed.

6A and 6B, when the second switch S2, the third switch S3 and the fourth switch S4 are simultaneously pressed, one current path is set. Here, the current path is a path via the third switch S3, the fourth switch S4, and the second switch S2. 6A and 6B, it is assumed that R is set to 10 KOhm, and r is set to 7 KOhm.

At this time, if the second input voltage VA is not applied, the detection voltage VO is calculated by the following expression (7).

[Equation 7]

On the other hand, when the second input voltage VA is applied, the detection voltage VO is calculated by the following expression (8).

[Equation 8]

If the variable voltage Vref is 2.5 V, it is recognized that the first switch S1 is not pressed in both cases.

Therefore, when the second input voltage VA is supplied, the noise margin is excellent because the detection voltage VO is higher than when the second input voltage VA is supplied.

When the variable voltage Vref of the voltage comparator 16 is set to 2.5 V, it can be determined that the first switch S1 is not pressed. However, when the second input voltage VA is applied, the detection voltage VO detected in comparison with the second input voltage VA is higher in any case. Therefore, if the variable voltage Vref of the voltage comparator 16 is set lower than the second input voltage VA, it is possible to detect whether the key is stable or not.

Considering the processing errors of the membrane sensor and the FSR sensor, the variation due to the environment, and the manufacturing tolerance of the IC, the second input voltage VA is supplied to obtain a stable operation result. Here, the amount of change due to the processing error and the environment is a case where the resistance value increases or decreases due to aging.

7A is a circuit diagram for explaining a touch panel when six switches are simultaneously pressed. 7B is an equivalent circuit diagram for explaining a touch panel when six switches are simultaneously pressed. In particular, it will be described that when six points are depressed and the first switch is not depressed, the first switch is not depressed.

7A and 7B, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, Is pressed at the same time, two current paths are set. That is, one current path is a first current path via the third switch S3, the fourth switch S4, and the second switch S2, and the other current path is connected to the fifth switch S5), the sixth switch (S6), and the second switch (S2). 7A and 7B, it is assumed that R is set to 10 KOhm, and r is set to 7 KOhm.

The parallel resistor (A) corresponding to the first current path is defined by the following equation (9).

[Equation 9]

Therefore, A = r.

At this time, if the second input voltage VA is not applied, the detection voltage VO is calculated by the following expression (10).

[Equation 10]

On the other hand, the parallel resistor (B) corresponding to the second current path is defined by the following expression (11).

[Equation 11]

Therefore, B = 0.5r.

At this time, when the second input voltage VA is applied, the detection voltage VO is calculated by the following expression (12).

[Equation 12]

If the variable voltage Vref of the voltage comparator 16 is 2.5 V, it is recognized that the first switch S1 is not pressed in both cases.

Therefore, when the second input voltage VA is supplied, the noise margin is excellent because the detection voltage is higher than when the second input voltage VA is supplied.

When the variable voltage Vref of the voltage comparator 16 is set to 2.5 V, it can be determined that the first switch S1 is not pressed. However, when the second input voltage VA is applied, the detection voltage VO detected in comparison with the second input voltage VA is higher in any case. Therefore, if the variable voltage Vref of the voltage comparator 16 is set lower than the second input voltage VA, it is possible to detect whether the key is stable or not.

Considering the processing errors of the membrane sensor and the FSR sensor, the variation due to the environment, and the manufacturing tolerance of the IC, the second input voltage VA is supplied to achieve a more stable operation. Here, the amount of change due to the processing error and the environment is a case where the resistance value increases or decreases due to aging.

The power saving mode among the operations of the power supply unit 15 and the first column switch unit 17a will be described in more detail with reference to FIG.

8 is a circuit diagram for explaining a power saving mode in operation of FIG.

The power save mode occurs when there is no key input of the key matrix 12 of the user for a predetermined time or when the USB keyboard enters a suspend mode. In the power save mode, the enable signal EN output from the column controller 14 is disabled and the power supply unit 15 and the voltage comparator 16 are disabled to change to a sleep state .

The first to seventh column switch units 17a to 17g are connected to the column scan lines Y30 to Y36 (shown in FIG. 2) So that the voltage of the power supply voltage VCC level is maintained in all the column scan lines Y30 to Y36. Then, all the switches 19 ... of the row scanning control device 13 are turned on to keep the row scan lines X10 to X16 (shown in Fig. 2) at 0V. In this manner, the power saving mode is entered, and the CPU 10 enables the interrupt and stops the clock generation.

Referring to Fig. 8, the power saving mode is a state in which the switching element rs0 (the physical switching element 121 in the key matrix 12 in Fig. 2) is opened. At this time, all the column scan lines Y30 to Y36 are pulled up by the pull-up resistor Rh, and all of the row scan lines X10 to X16 are connected to the N channel open drain N- channel Open Drain) is enabled and has a voltage near 0V. At this time, the interrupt signal INT has a value near the power supply voltage VCC in the same manner as the voltage of the column scan line, so that the holding voltage Vh has a high level.

Meanwhile, when a key input is generated by the user in the power saving mode, the switching element rs0 or 121 in Fig. 2 is connected to the pull-up resistor Rh, the switching resistor rm (122 in Fig. 2) The on resistance rs1 of the NMOS transistor 19 connected to the power supply voltage VCC and the 0V voltage is formed in series. At this time, since the resistance value of the pull-up resistor Rh is sufficiently larger than the switching resistance rm in the key matrix 12 and the resistance value of the on-resistances rs0 and rs1 of the switches is larger than the resistance value of the pull- (rm), the holding voltage Vh has a value near 0 V, that is, a low level. At this time, since the holding voltage Vh is a value near 0V, the CPU 10 outputs an interrupt signal INT to the CPU 10 to indicate that the interrupt signal INT is wake-up It informs.

The CPU 10 generates a clock again by the interrupt signal INT and controls the column scan control device 11 and the column scan control device 13 to perform the column scan control operation and the row scan control operation.

3, the holding voltage Vh of FIG. 3 is changed from the high level to the low level by the user's key input in the power saving mode, and the buffer B (shown in FIG. 3) ). Accordingly, the CPU 10 receives the interrupt signal INT from the buffer B and exits from the power save mode, operates in the normal scan mode, which is the normal key input detection state, and performs a column scan operation And recognizes the position of the key pressed by the user by performing the row scanning operation.

The power supply unit 15 shown in FIG. 3 may be constituted by a constant voltage regulator system or a current amplifier system by resistance distribution.

9 is a block diagram for explaining an example of the power supply unit shown in FIG. Particularly, a power supply portion constituted by a constant voltage regulator system is shown.

9, the power supply unit 15 of the constant voltage regulator type includes a reference voltage generating circuit 20, an amplifier 21, a PMOS transistor Tr, a series resistor Rr, and a variable resistor Rv.

The amplifier 21 receives the variable voltage Vref of the second input voltage VA to be output from the reference voltage generating circuit 20 and outputs a series resistor Rr Source voltage Vgs of the appropriate PMOS transistor by controlling the current flowing across the PMOS transistor using the comparison between the divided voltage of the variable resistor Rv and the variable voltage Vref, Thereby generating an input voltage VA.

10 is a block diagram for explaining another example of the power supply unit shown in FIG. Particularly, a power supply section constituted by a current amplifier system by resistance distribution is shown.

10, the current supply unit 15 of the current amplifier type includes a series resistor Rr having one end connected to the power supply voltage VCC, a variable resistor Rv having one end connected to the other end of the series resistor Rr, And a PMOS transistor Tr and an amplifier 22 connected to the other end of the resistor Rv.

The variable voltage Vref divided by the series resistor Rr and the variable resistor Rv from the power supply voltage VCC is supplied to the variable input terminal of the amplifier 22 via the negative feedback of the amplifier 22, Is equal to the voltage Vref but amplifies only the supply capability of the current to generate and output the second input voltage VA.

The power supply unit 15 shown in FIG. 9 or 10 may be enabled to disable the operation by receiving the enable signal EN in order to operate in the power saving mode, thereby reducing the current consumption at the time of disable have. In addition, the power supply unit 15 shown in FIG. 9 or 10 can vary the value of the output voltage generated by the first adjustment value (adj0) input from the CPU 10. FIG.

11 is a block diagram for explaining another example of the column scan control device 11 shown in Fig.

2 and 11, the column scan control device 11 includes a column control unit 14, a power supply unit 15, a pull-up resistor Rh, a first variable resistor R0, a plurality of column switch units, (B), a fixed resistor (R2), a second variable resistor (R1) and an analog-to-digital converter (116). The column scan control device 11 shown in Fig. 11 is substantially the same as the column scan control device 11 shown in Fig. 3 except for the analog-to-digital converter 116, so that the same components are given the same reference numerals A detailed description thereof will be omitted.

The analog-to-digital converter 116 is connected to each of the thermal switch units 17a to 17g, and is enabled by the enable signal EN. The analog-to-digital converter 116 compares the first input voltage Vup applied to each of the thermal switch units with the variable voltage Vref, and outputs the result to the CPU 10.

12 is a block diagram for explaining the analog-digital converter shown in FIG. In particular, a fully-differential analog-to-digital converter is shown.

12, the analog-to-digital converter 116 includes a first digital-to-analog converter (DAC) 116a, a second digital-to-analog converter 116b, a voltage output from the converters 116a and 116b And a comparator 116c and a successive approximation register (SAR) 116d.

In operation, the first digital-to-analog converter 116a and the second digital-to-analog converter 116b convert the digital signal into an analog voltage and output it.

The comparator 116c compares the output voltage value of the first digital-to-analog converter 116a with the output voltage value of the second digital-to-analog converter 116b, And outputs it to the approximation register 116d as one digital value.

13A is an exploded perspective view illustrating a keyboard according to an embodiment of the present invention. 13B is an exploded perspective view for explaining the membrane switch sheet shown in FIG. 13A. In particular, a keyboard in which the key matrix is composed of a membrane switch sheet is shown.

13A and 13B, a membrane switch keyboard according to an embodiment of the present invention includes a lower case 100, an upper case 200, a rubber dam sheet 300, a membrane switch sheet 400, and a micro control unit Micro Control unit 500).

The lower case 100 provides a base 110 on which the above components are stacked. In the present embodiment, the lower case 100 is a rectangular flat plate, a plurality of bolt holes H for screw assembly are formed on the back surface portion, and a slope of the membrane switch keyboard 100 is formed on the left and right upper sides of the back surface portion. (Not shown) is hingedly connected to the left and right lower sides of the rear portion, and a leg made of a rubber member (not shown) for preventing slippage is fixedly installed.

A plurality of key buttons 210 are disposed in the upper case 200 and the membrane switch sheet 400, the micro control unit 500 and the rubber dome sheet 300 ).

The rubber dam sheet (300) is disposed on the membrane switch sheet (400). A plurality of rubber dome 310 are formed on the rubber dam sheet 300.

The membrane switch sheet 400 includes a lower sheet 410, a spacer sheet 420 disposed on the lower sheet 410, and an upper sheet 430 disposed on the spacer sheet 420.

A plurality of spacer holes are formed in the spacer sheet 420. The area where the spacer holes are not formed can prevent a short circuit between the scan line formed in the lower sheet 410 and the scan line formed in the upper sheet 430. If the scan line formed in the lower sheet 410 is a thermal scan line, the scan line formed in the upper sheet 430 is a scan line. Of course, the reverse is also possible.

The lower sheet 410 includes a lower base film 412 and a first conductive ink layer 414 printed on one side of the lower base film 412 in a first direction. The first conductive ink layer 414 may be printed on the front surface of the base film 412 or may be printed on a rear surface. In this embodiment, the front surface of the base film 412 is adjacent to the upper sheet 430, and the rear surface of the base film 412 is opposite to the front surface.

The first conductive ink layer 414 may include carbon. The carbon is cheaper than silver. The first conductive ink layer 414 is also printed at one degree to form the column scan lines 414a and the first contact electrodes 414b. The column scan line 414a is printed, for example, in the horizontal direction (or the X-axis direction). Each of the first contact electrodes 414b branches at the column scan line 414a. A plurality of first contact electrodes 414b are connected to one column scan line 414a.

The first contact electrode 414b may have various shapes including a circular shape. If the first contact electrode 414b has a circular shape, the diameter of the first contact electrode 414b may be larger than the width of the column scan line 414a. For example, the diameter of the first contact electrode 414b may be two, three, or four times the width of the column scan line 414a.

The spacer sheet 420 is disposed on the lower sheet 410, and a plurality of spacer holes 422 are formed corresponding to each of the key button regions. If the membrane switch keyboard is a 103 keyboard, the number of spacer holes is 103.

The upper sheet 430 is disposed on the spacer sheet 420 and includes an upper base film 432 and a second conductive ink layer 434 printed on the lower surface of the upper base film 432 in a second direction, . The second conductive ink layer 434 may include carbon.

The second conductive ink layer 434 is also printed to form the first and second contact electrodes 434a and 434b. The row spacing 434a is printed in the vertical direction (or the Y-axis direction), for example. Each of the second contact electrodes 434b is formed in the row sine line 434a so as to extend beyond the width of the row sine line 434a. A plurality of second contact electrodes 434b are connected to one row of scan lines 434a.

The second contact electrode 434b may have various shapes including a circular shape. If the second contact electrode 434b has a circular shape, the diameter of the second contact electrode 434b may be larger than the width of the row contact line 434a. For example, the diameter of the second contact electrode 434b may be two, three, or four times the width of the row sine ring 434a. In this embodiment, for the coordinate detection of the pressed key button, the column scan line carries a square wave transmission signal for coordinate detection, and the square line sensor can transmit a square wave reception signal for coordinate detection have. On the other hand, for the coordinate detection of the pressed key button, the row sine line transmits a transmission signal for coordinate detection, and the column scanning line can transmit a reception signal for coordinate detection.

The row scan line 434a and the column scan line 414a may intersect each other when viewed on the XY plane. Each of the second contact electrodes 434b may overlap each of the first contact electrodes 414b when viewed on the XY plane. At this time, a spacer hole 422 formed in the spacer sheet 420 is disposed between the overlapped second contact electrode 434b and the first contact electrode 414b.

The row scan line 434a and the second contact electrode 434b may correspond to a transmission line and the column scanning line 414a and the first contact electrode 414b may correspond to a reception line . Of course, the reverse is also possible.

For example, when the specific first contact electrode 414b and the specific second contact electrode 434b are close to each other, the capacitance between the first contact electrode 414b and the second contact electrode 434b is changed. The changed capacitance is provided to the microcontrol unit 500 (shown in FIG. 1) through a row line connected to the second contact electrode 434b so that the specific coordinate whose capacitance has changed can be recognized.

The micro control unit 500 calculates key coordinates based on the capacitance sensing signal provided from the membrane switch sheet 400 and provides the computed key coordinates to a computer main body (not shown).

When the key is pressed, the key presses the rubber dome of the rubber dome sheet, and the pressed rubber dome presses the upper sheet below. When the upper sheet is pressed, the contact electrode is connected to the lower sheet, and the keystroke is recognized. That is, when the user presses a specific key, data such as [the intersection of the x-th column and the y-th row] is input to the keyboard to determine the key coordinate.

14A is an exploded perspective view illustrating a keyboard according to another embodiment of the present invention. 14B is an exploded perspective view for explaining the membrane switch sheet shown in FIG. 14A. In particular, a keyboard is shown in which the key matrix is composed of a force sensing resister (FSR) member.

14A and 14B, an FSR keyboard according to another embodiment of the present invention includes a lower case 100, an upper case 200, a rubber dam sheet 300, an FSR member 600, and a microcontrol unit 500, . Since the keyboard shown in Fig. 14A is the same as the keyboard shown in Fig. 13A except for the FSR member 600, the same components are denoted by the same reference numerals, and a detailed description thereof will be omitted.

The FSR member 600 includes a lower substrate 610, a spacer sheet 620 disposed on the lower substrate 610, and an FSR sheet 630 disposed on the spacer sheet 620.

The lower substrate 610 includes a base substrate, a first conductive ink layer printed on one side of the base substrate in a first direction, and a second conductive ink layer printed on the other side of the base substrate in a second direction.

The base substrate may include a rigid PCB substrate or a flexible flexible substrate.

The first conductive ink layer may include carbon. The carbon is cheaper than silver. The first conductive ink layer is printed once to form the column scan lines and the first contact electrodes. The column scan lines are printed in, for example, the horizontal direction (or the X-axis direction). Each of the first contact electrodes is branched at the column scan line. A plurality of first contact electrodes are connected to one column scan line. The first contact electrode may have various shapes including a circular shape. If the first contact electrode has a circular shape, the diameter of the first contact electrode may be larger than the width of the column scan line. For example, the diameter of the first contact electrode may be two, three or four times the width of the column scan line.

The second conductive ink layer is also printed to form the first contact electrodes and the second contact electrodes. The row sagittal is printed in the vertical direction (or Y axis direction), for example. Each of the second contact electrodes is formed to extend in a width direction of the row of the row electrodes. A plurality of second contact electrodes are connected to one row of scan lines. The second contact electrode may have various shapes including a circular shape. If the second contact electrode has a circular shape, the diameter of the second contact electrode may be larger than the width of the first contact electrode. For example, the diameter of the second contact electrode may be twice, three times, or four times as large as the width of the row electrode. In this embodiment, for the coordinate detection of the pressed key button, the column scan line carries a square wave transmission signal for coordinate detection, and the square line sensor can transmit a square wave reception signal for coordinate detection have. On the other hand, for the coordinate detection of the pressed key button, the row sine line transmits a transmission signal for coordinate detection, and the column scanning line can transmit a reception signal for coordinate detection.

The row scan lines and the column scan lines may intersect each other when viewed on the XY plane. Each of the second contact electrodes may overlap each of the first contact electrodes when viewed on an XY plane. At this time, the spacer holes 622 formed in the spacer sheet 620 are disposed corresponding to the second contact electrodes and the first contact electrodes overlapping each other.

In this embodiment, the row scan line and the second contact electrode may correspond to the transmission line, and the column scanning line and the first contact electrode may correspond to the reception line. Of course, the reverse is also possible.

For example, when a specific first contact electrode and a specific second contact electrode are close to each other, capacitance between the first contact electrode and the second contact electrode is changed. The changed electrostatic capacity is provided to the microcontrol unit 500 via a row line connected to the second contact electrode, so that the specific coordinate whose capacitance is changed can be recognized.

The spacer sheet 620 is disposed on the lower substrate 610, and a plurality of spacer holes 622 are formed corresponding to each of the key button regions. If the switch keyboard is a 103 keyboard, the number of spacer holes is 103.

The FSR sheet 630 is disposed on the spacer sheet 620. The FSR sheet 630 may be formed of polyethylene in which conductive carbon particles are mixed.

When a user presses a key button, a specific portion of the FSR sheet 630 is pressed so that a resistive conductive path is formed between the first contact electrode and the second contact electrode formed on the lower substrate 610 through the FSR do. Where the resistance value depends on the force the user presses the key button. For example, if the force pressing the key button is 10 grams, the resistance value of the FSR may be 1 MOhm, and if the force of pressing the key button is 500 grams, the resistance value of the FSR may be 1 kOhm.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. You will understand.

As described above, according to the present invention, by varying the first input voltage Vup and providing the first input voltage Vup to the thermal switch units, the printing tolerance increases in the membrane key matrix printed with carbon, Can be prevented. Accordingly, the key input device according to the present invention can be used for a key matrix having a small resistance or a key matrix having a large resistance.

In addition, the key matrix can be controlled by using a switch having a simple structure to eliminate the ghost key phenomenon, operate in a power saving mode, and reduce manufacturing cost.

10: CPU 11: column scan control device
13: a row scanning control device 14:
15: power supply unit 16: voltage comparator
18: row control unit 20: reference voltage generation circuit
21, 22: amplifier Rh: pull-up resistor
R0: first variable resistor R2: fixed resistor
R1: second variable resistor B: buffer
R2: fixed resistor R1: second variable resistor
Rr: series resistance Rv: variable resistance
16: analog-to-digital converter 110, 120: digital-to-analog converter
130: Comparator 140: Decision approximation register
100: Lower case 200: Upper case
300: Rubber dam sheet 400: Membrane switch sheet
410: lower sheet 420: spacer sheet
430: upper sheet 500: microcontroller unit
600: FSR member 610: lower substrate
620: spacer sheet 630: FSR sheet

Claims (16)

In a key input device connected to a key matrix including a plurality of switches connected to column scan lines and row scan lines,
(I) a first input voltage Vup for each column in the normal scan mode, and (ii) a second input voltage Vup for each column in the normal scan mode, according to the column scan signal and the enable signal EN of the CPU. And a second input voltage VA; and (ii) a column scan unit for performing a column scan operation for each mode in accordance with a switching operation of a column switch unit receiving the holding voltage Vh in a power- Device; And
A scan driver for performing a row scan in accordance with a row scan signal of the CPU in synchronization with a column scan signal of the column scan control device in the normal scan mode, Device,
Wherein the thermal scan control device includes a reference voltage and a first variable resistor which is disposed between each of the thermal switch units and varies the first input voltage Vup to provide the reference voltage to each of the thermal switch units Key input device. The apparatus of claim 1, wherein the column scan control device
A column controller for outputting a column scan signal and an enable signal EN under the control of the CPU;
A plurality of switch units connected in a one-to-one correspondence with the column scan lines to perform column scanning by switching the column scan lines selected by the column scan signal of the column control unit and the remaining unselected column scan lines according to an input voltage;
The second input voltage VA and the holding voltage Vh are selectively enabled and disabled in accordance with an enable signal of the thermal control unit so that the first input voltage Vup, A power supply unit selectively outputting power to the switch unit according to a mode; And
And the reference voltage generating resistors (R1, R2) are enabled according to an enable signal of the column control unit and are operated in the normal scan mode and are disabled according to an enable signal of the column control unit, And a voltage comparator for comparing the variable voltage generated based on the resistance value of the first input voltage Vup with the first input voltage Vup and outputting the result to the CPU. 3. The key input device of claim 2, wherein the voltage comparator has a hysteresis characteristic. 3. The key input device of claim 2, wherein the voltage comparator includes an analog-to-digital converter. The power supply unit according to claim 2, wherein when the enable signal (EN) is enabled under the control of the CPU in the normal scan mode, the power supply unit supplies the first input voltage (Vup) Wherein the switching matrix is selectively supplied to each column scan line of the switching matrix. The power supply unit according to claim 2, wherein when the enable signal (EN) is disabled under the control of the CPU in the power saving mode, the power supply unit supplies the holding voltage (Vh) And the key input device is connected to the key input device at the same time. The method of claim 6, wherein the column scan control device is configured to control the column scan control device such that the holding voltage (Vh) supplied from the power supply unit is connected in the power saving mode, And generates an interrupt signal (INT) to the CPU when a key input is generated by a user. The method as claimed in claim 7, wherein the interrupt signal does not generate an interrupt signal in the normal scan mode, and generates an interrupt signal only when a user's key input occurs in the power saving mode. . The method according to claim 7, wherein in the normal scan mode, the row scan control device performs a function of sequentially connecting the scan line signal lines to 0V under the control of the CPU, and in the power saving mode, And a row controller for performing a function of connecting the input signal to the input terminal. 3. The key input device of claim 2, wherein the thermal controller disables the enable signal (EN) applied to the power supply and the voltage comparator to minimize power consumption in the power saving mode. A key matrix including a plurality of switches to which column scan lines and row scan lines are connected; And
And a key input device connected to the key matrix,
(I) a first input voltage Vup for each column in the normal scan mode, and (ii) a second input voltage Vup for each column in the normal scan mode, according to the column scan signal and the enable signal EN of the CPU. And a second input voltage VA; and (ii) a column scan unit for performing a column scan operation for each mode in accordance with a switching operation of a column switch unit receiving the holding voltage Vh in a power- Device; And
A scan driver for performing a row scan in accordance with a row scan signal of the CPU in synchronization with a column scan signal of the column scan control device in the normal scan mode, Device,
Wherein the thermal scan control device includes a reference voltage and a first variable resistor which is disposed between each of the thermal switch units and varies the first input voltage Vup to provide the reference voltage to each of the thermal switch units keyboard. 12. The keyboard according to claim 11, wherein the key matrix is a membrane switch sheet. 12. The keyboard according to claim 11, wherein the key matrix is a force sensing resister (FSR) sheet. 12. The method of claim 11,
An external resistor whose one end is connected to the output terminal of the thermal switch; And
Further comprising an external switch, one end of which is connected to the other end of the external resistor, and the other end of which is grounded. The apparatus of claim 11, wherein the column scan control device
A column controller for outputting a column scan signal and an enable signal EN under the control of the CPU;
A plurality of switch units connected in a one-to-one correspondence with the column scan lines to perform column scanning by switching the column scan lines selected by the column scan signal of the column control unit and the remaining unselected column scan lines according to an input voltage;
The second input voltage VA and the holding voltage Vh are selectively enabled and disabled in accordance with an enable signal of the thermal control unit so that the first input voltage Vup, A power supply unit selectively outputting power to the switch unit according to a mode; And
And the reference voltage generating resistors (R1, R2) are enabled according to an enable signal of the column control unit and are operated in the normal scan mode and are disabled according to an enable signal of the column control unit, And a voltage comparator for comparing the variable voltage generated based on the resistance value of the first input voltage Vup with the first input voltage Vup and outputting the result to the CPU. 16. The method of claim 15,
An external resistor whose one end is connected to the output terminal of the thermal switch; And
Further comprising an external switch having one end connected to the other end of the external resistor and the other end grounded,
When the key matrix has a large on-resistance value of a level that the IC can not accommodate, the resistance of the external resistor is adjusted so that the first input voltage Vup by the key push applied to the input terminal of the voltage comparator ) Of the keyboard is adjusted.

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