JPH06124150A - Driving controller for microprocessor - Google Patents

Abstract

PURPOSE:To reduce an unnecessary power consumption without apparently decreasing the processing capacity and processing speed of a microprocessor at all, and to apply a power saving control to a microprocessor in which a clock frequency can not be switched like a step during an operation. CONSTITUTION:A state discriminating circuit 7 discriminates whether a microprocessor 2 is in an idle state or a non-idle state by monitoring the program executing state of the microprocessor 2. In a clock generating part 3, each time the discriminated signal is inverted, the clock frequency is gradually changed at a small change rate less than a normal value between a prescribed high frequency and a prescribed low frequency, and the microprocessor can be moved between a high speed mode and a low speed mode without generating any malfunction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor-based device such as a battery-powered portable personal computer, and more particularly to a microprocessor for reducing power consumption without deteriorating the substantial capability of the microprocessor. The present invention relates to a drive control device for a processor.

[0002]

2. Description of the Related Art As disclosed in, for example, Japanese Unexamined Patent Publication No. 2-178818, depending on the operating state of each part of a computer system, power supply to a part in a dormant state in which no work is actually performed is stopped. By doing so, there is a technique of reducing the power consumption of the entire system, which is concretely implemented in various forms. Especially for battery-powered portable personal computers, in order to operate as long as possible with a small and lightweight battery,
This kind of power saving technology is being actively researched.

Some conventional personal computers have two types of standby functions called a rest mode and a sleep mode. In rest mode, if the CPU is not operating for a certain period of time, the operating frequency is automatically set to 16M.
It is a function to reduce from Hz to 1 MHz. After a certain period of time, the sleep mode is automatically entered. In sleep mode, power supply is stopped. No matter which mode you are operating in, you can press any key to return to normal mode. The time to enter the standby mode can be arbitrarily set by the user.

Here, "the CPU does not operate for a certain period of time" is a condition for shifting to the power saving state (the above-mentioned standby mode). Specifically, when an external factor such as an input from a keyboard or an input from a communication controller for starting the work of the CPU does not occur for a predetermined time or longer, the power saving state is entered.

[0005]

When an application software such as a Japanese word processor or a spreadsheet is executed on a general personal computer, the processing speed of a recent high-performance microprocessor (CPU) is keyboard input by an operator. It is much faster than the speed, and the CPU usually waits for the next work activating factor, that is, the idle state frequently occurs. If it is possible to shift to the power saving state (state in which both the power consumption and the processing speed of the CPU are small) by catching such an idle state of the CPU, it is very effective. It is highly desirable to further advance this kind of power saving control technology so that unnecessary power consumption in actual operation can be reduced without reducing the substantial processing capacity and processing speed of the microprocessor. There is.

Further, since a microprocessor having a large processing capacity and a high processing speed consumes a large amount of power and thus generates a large amount of heat, reducing unnecessary power consumption of the microprocessor increases the battery's usage time. Not only is this advantageous in terms of the thermal design of the microprocessor-using device, but it is easy to reduce the size and weight of so-called notebook personal computers and electronic notebooks.

An important point in designing a drive control device for a microprocessor for the purpose of power saving of this kind is that an algorithm for accurately and accurately detecting an idle state and a power saving control will cause a malfunction. There is no reliability. In the conventional device, when the idle state is detected by some method, the clock frequency is switched from 16 MHz to 1 MHz, for example. In some microprocessors, even if the clock frequency is switched during operation in this way, malfunction does not occur and continuity of operation is guaranteed, but in another microprocessor, the clock frequency cannot be switched during operation. .

For example, in the microprocessors 80486DX, DX2, SX manufactured by Intel Corporation of the United States, a value of 0.1% or less is required as the cycle stability of the clock signal in operation, and if the clock cycle fluctuates beyond this specified value. Normal operation is not guaranteed. Therefore, it is not possible to apply the power saving control of switching the clock frequency in two stages between the idle state and the non-idle state to this type of microprocessor.

The present invention has been made in view of the above technical problems. An object of the present invention is not necessary depending on the program execution state even for a microprocessor that cannot switch the clock frequency between two stages during operation. It is to be able to apply the power saving control of reducing power consumption.

[0010]

A drive control device for a microprocessor according to the present invention comprises a state monitoring means for monitoring a program execution state by the microprocessor to determine whether the microprocessor is in an idle state or not. When the state monitoring means determines that the state has changed from the non-idle state to the idle state, the frequency of the clock signal supplied to the microprocessor is gradually reduced at a rate of change below a specified value to change to a predetermined low frequency. When it is determined that the clock frequency gradually decreasing means and the state monitoring means have changed from the idle state to the non-idle state, the frequency of the clock signal supplied to the microprocessor is gradually increased at a rate of change equal to or less than a specified value to a predetermined value. And a means for gradually increasing the clock frequency for changing the frequency to a higher frequency.

[0011]

Even if the microprocessor is required to have a stability of the clock frequency of 0.1% or less, there is no possibility of malfunction if the clock frequency is gradually changed by 0.1%. If the prescribed high frequency is 50 MHz, the prescribed low frequency is 16 MHz, and the prescribed rate of change is 0.1%, it takes about 1140 clocks to reach 50 MHz to 1 MHz.
It can be changed up to 6 MHz.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a schematic configuration of a drive control device for a microprocessor according to an embodiment of the present invention. In this embodiment, a microprocessor 8 manufactured by Intel Corp.
A notebook personal computer system 1 using 0486SX as the CPU 2 is assumed.

The clock signal of the CPU 2 is supplied from the clock generator 3. The clock generator 2 has a state determination circuit 7
The clock frequency is changed in the range of 50 MHz to 16 MHz as described in detail below in accordance with the determination signal from. The system bus 6 of the computer system 1 includes a state determination circuit 7, an address monitoring circuit 8 and an address detection circuit 9.
Are connected to monitor the program execution state of the CPU 2 and output a determination signal indicating whether the CPU 2 is in the idle state to the clock generation unit 3.

The address monitor circuit 8 operates in either the address storage mode or the address comparison mode in response to the control signal from the state determination circuit 7. In the address storage mode, the stored contents are first cleared, and then the address accessed by the CPU 2 is stored at an appropriate address resolution (when the CPU 2 accesses an address, "1" is set to the corresponding storage cell in the circuit 8. ). The address group stored in this address storage mode will be referred to as a learning address below. Also, the address monitoring circuit 8
Operates in the address comparison mode, the address accessed by the CPU 2 is sequentially compared with the learning address described above, and when an address other than the learning address is newly accessed, the address monitoring circuit 8 outputs a mismatch signal to the state determination circuit 7. Will be output.

The system 1 of this embodiment is provided with MS-DOS as an operating system. MS-DO operating at low power of 80486SX
The S application program performs processing using the interrupt vector table assigned to a specific address. In this interrupt vector table, a software interrupt function for fetching input data in response to a keyboard input, a software interrupt function for checking the presence / absence of keyboard input, and the like are set. The address detection circuit 9 of FIG. 1 is a circuit for individually detecting that the two software interrupt vectors in the interrupt vector table have been accessed, and the detection signal thereof is as follows.
Therefore, it is used for control.

FIG. 3 is a flowchart showing a processing procedure of monitoring the program execution state of the CPU 2 and the power saving control by the state determination circuit 7.

As shown in FIG. 3, a first step 100
Then, as the initial setting, the determination signal is H, which indicates a non-idle state.
The level is set to a level (as will be described later, in the non-idle steady state, the clock signal of 50 MHz is output from the clock generator 3 and the CPU 2 operates in the high speed mode). Then, in step 101, the learning time Tx is set to the lower limit value 100 μsec. In the next step 102, after the address monitoring circuit 8 is cleared, it is operated in the address storage mode for the learning time Tx. As a result, the address block accessed by the CPU within the time Tx is stored in the address monitoring circuit 8 (this is the learning address).

In the next step 103, the timer for the monitoring time Ty (which is a value appropriately larger than Tx) set according to the learning time Tx is started, and the address monitoring circuit 8 is operated in the address comparison mode. Then, the Ty timer monitors whether or not the CPU accesses other than the learning address within the time Ty (steps 103, 10).
4). When the address other than the learning address is addressed within the time Ty, the process proceeds from step 104 to step 105 at that time, and the value obtained by adding 100 μsec to the learning time Tx is added to the new learning time T.
x, and the learning time Tx is the upper limit value of 10 m in step 106.
Check whether it exceeds sec. Tx is 10
If it is within msec, the process returns to step 102 to execute the learning process. If Tx exceeds 100 msec, the process returns to step 101 to set Tx to the lower limit value of 100 μsec and then proceeds to step 102.

In steps 100 to 106, the learning process of step 102 and the monitoring processes of steps 103, 104 and 105 are repeated while gradually increasing the learning time Tx and the monitoring time Ty from the lower limit value to the upper limit value. This means that the repetitive access state that "other than the learning address is not accessed within the time Ty" is detected.

When a repetitive access state is detected in which "only the learning address is not accessed within the time Ty",
Proceeding from step 104 to step 107, it is determined whether the program execution state of the CPU 2 meets the following exclusion conditions. If not, the process proceeds to step 108 and the determination signal is inverted to the L level indicating the idle state. After that, in step 109, the CPU 2 continues to monitor whether or not the repeat access state is exited. If the repeat access state is exited, the process returns to the first step 100 and the determination signal is set to the H level (indicating a non-idle state). Flip to
The processing described above is performed again. As will be described later, in the idle steady state, a 16 MHz clock signal is output from the clock generator 3, and the CPU 2 operates in the low speed mode.

By the way, the exclusion condition in step 107 is that the address of the software interrupt vector for checking the keyboard input is past when the address of the software interrupt vector for fetching the keyboard input is accessed within a predetermined time immediately before. The case where it is not accessed for a certain time or more is the case where the address allocated as the video memory space is accessed.

In step 109, the escape of the repeated access state is specifically detected as follows. The address monitoring circuit 8 is operated in the comparison mode and continues to monitor whether or not a learning address other than the learned address stored by the execution of step 102 is accessed. If an address other than the learning address is accessed, it is determined that the repeated access state has been exited.
Also, even if the addresses other than the learning address are not accessed, even if the address of the software interrupt vector for reading the keyboard input is accessed, it is immediately determined that the repeated access state is exited.

In this way, the CPU 2 has a capacity of about 20 mse.
The CPU 2 detects the state of repeatedly accessing only the address group within the time range of c or less, and the CPU 2 during the period of detecting such a repeated access state (except when the above exclusion condition is satisfied). Operate in low speed mode.

The configuration and operation of the state monitoring means in this embodiment have been described above. The effects of this will be described in detail below.

In the above-mentioned conventional technique, it is determined that the CPU is in the idle state because "the factor for starting the work of the CPU does not occur for a certain period of time", and the mode is shifted to the power saving mode (low speed mode). . When applying this conventional technology to a general personal computer,
It is necessary to set the above "certain time" to several tens of seconds or more, and there is a problem that a sufficient power saving effect cannot be obtained. For example, assume that a word processor software is being used. When the operator inputs a key while thinking about sentences, the processing speed of the CPU is often overwhelmingly faster than the key input speed, and several tens of milliseconds to several seconds are required between one key input and the next key input. There are so many opportunities to cause a real hibernation of. However, if the "constant time" in the conventional power saving control method described above is set to, for example, 1 second to several seconds, the power saving state can be achieved while doing work such as moving documents and organizing dictionary files that take a little time. Will move to. Therefore, in consideration of sufficient safety, it is necessary to set the "constant time" to be sufficiently long and set to several tens of seconds to several minutes. Then, the power saving function does not work for the frequently occurring short-term real dormant state, and a sufficient power saving effect cannot be obtained.

When compared with the prior art as described above, the state monitoring means of this embodiment has the following operational effects.

When the CPU repeatedly executes a loop-type program, the address at which the instruction group forming the loop is stored is unique to most instructions. Therefore, when the loop program is being executed, the CPU repeatedly accesses only a certain limited address group. Assuming that the repetition period is T, at least (2
The repeated access state can be detected by monitoring the transition status of the access address of the CPU for a time of × T + α).

In an idle state where the system is waiting for keyboard input, the CPU is in a very short cycle, repetitive access state. Therefore, when the repeated access state is detected within the time range set appropriately, C
The operation mode of the PU is switched from the high speed mode to the low speed mode. When some valid work is activated, the CPU exits the repeated access state and enters the non-idle state, at which time the operation mode is returned to the high speed mode. By doing so, a very short power saving period can be frequently created without any hindrance to the operation of the system.

Next, the structure and operation of the clock generator 3 including the clock frequency gradually decreasing means and the gradually increasing means will be described in detail with reference to the waveform diagram of FIG.

The clock generator 3 of the embodiment shown in FIG. 1 buffers the determination signal output from the state determination circuit 7 and appropriately amplifies it, and an integrator 32 that integrates the determination signal passed through the buffer 31. A limiter 33 for limiting the integrated output within a range of predetermined upper limit value and lower limit value, and this limiter 3
3 is a voltage-controlled variable frequency oscillator (VCO) 34 that uses the output of 3 as a control voltage, and the oscillation output of the VCO 34 is C
It becomes the clock signal of PU2.

As shown in FIG. 2, when the output of the buffer 31 changes from the L level (idle state) to the H level (non-idle state), the output of the integrator 32 gradually has a characteristic according to its integration time constant. When it increases and conversely changes from H level to L level, the integrated output gradually decreases. The upper limit value set in the limiter 33 is equal to the control voltage for setting the output frequency of the VCO 34 to 50 MHz, and the lower limit value is VC.
It is equal to the control voltage that brings the output frequency of O34 to 16 MHz. The output of the integrator 32 changes beyond the range of the upper limit value and the lower limit value, but the output of the limiter 33 gradually increases from the lower limit value to the upper limit value in response to the decision signal being inverted from the L level to the H level. Also, in response to the decision signal being inverted from the H level to the L level, it gradually decreases from the upper limit value to the lower limit value. The rate of change of the gradual increase / decrease is determined by the integration characteristic of the integrator 32, but the rate of change of the frequency of the VCO 34 that changes in response to the changing output voltage of the limiter 33 is 0.1.
% (The stability of the clock frequency set in the CPU 2) is not exceeded, the integral characteristic is set.

Therefore, when the determination signal is inverted from the H level to the L level, the clock frequency does not change stepwise from 50 MHz to 16 MHz, but gradually within the range where the frequency change rate does not exceed 0.1%. Change, C
The PU 2 shifts from the high speed mode to the low speed mode to some extent, and no malfunction occurs. Similarly, the change of the clock frequency at the time of shifting from the low speed mode to the high speed mode is gradually made, and no malfunction occurs.

FIG. 4 shows another embodiment of the clock generator. In this embodiment, a 50 MHz reference oscillator 41 and a 16 MHz reference oscillator 41 are provided, and when the determination signal is at the H level, the 50 MHz reference signal is input to the frequency-voltage (FV) converter 44 via the switching circuit 43. , When the judgment signal is L level, the reference signal of 16MHz is FV
Input to the converter 44. Further, the output of the VCO 46 that generates the clock signal of the CPU is input to the FV converter 47 having the same characteristics as the FV converter 44, and both FV converters 44 and 4 are supplied.
The voltage output of 7 is compared by the comparator 45.

Further, the change point of the determination signal is the rising detector 4
8 and the trailing edge detector 49, respectively. VC
For the circuit 50 that generates the control voltage of O46, the detection signal of the rising detector 48 becomes the control voltage up command, and the detection signal of the falling detector 49 becomes the control voltage down command,
The coincidence signal of the comparator 45 becomes the control voltage hold command.

In the idle steady state in which the determination signal is L level, the VCO 46 oscillates at 16 MHz.
When the determination signal is inverted to the H level, a rising detection signal is generated, and the control voltage generation circuit 50 gradually increases the output voltage at a prescribed change rate or less. As a result, the clock frequency from the VCO 46 is gradually increased below the specified rate of change. Clock frequency at this time and 50 MHz from oscillator 41
Of the reference signal of the FV converters 44 and 47 and the comparator 45.
The output voltage of the control voltage generation circuit 50 is held at the time when the coincidence signal is output from the comparator 45, and the oscillation frequency of the VCO 46 is stabilized at 50 MHz. The CPU is now operating in high speed mode. When the determination signal becomes L level, a fall detection signal is generated,
The control voltage of the VCO 46 begins to drop gradually, and the clock frequency drops below a prescribed rate of change. This clock frequency is compared with the 16 MHz reference signal from the oscillator 42 as described above, the control voltage is held when the coincidence signal is output from the comparator 45, and the clock frequency is 1
Stabilized to 6 MHz.

Although two configuration examples of the clock generation unit have been described above, the present invention is not limited to these embodiments, and for example, a feedback control type circuit using a PLL (phase locked loop) circuit, etc. The clock frequency gradual increase / decrease means of the invention can be embodied in various circuits. In the case of the open-loop type clock generation unit as shown in FIG. 1, it is possible to ensure stable operation in actual use by using a circuit having a temperature characteristic such that the clock frequency appropriately decreases due to temperature rise. it can.

[0037]

As described in detail above, even in the case where the clock frequency during operation is required to have a high degree of stability of, for example, about 0.1%, and the clock frequency cannot be switched stepwise. As in the drive control device of the present invention, by gradually changing the clock frequency at a prescribed rate of change or less, the mode transition between the high speed mode and the low speed mode can be performed without malfunctioning while maintaining the continuity of the processing of the microprocessor. It can be carried out. Therefore, even in a system using this kind of microprocessor, it is possible to apply the power saving control for reducing unnecessary power consumption according to the program execution state.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a drive control device for a microprocessor according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing the operation of the clock generation unit in the above embodiment.

FIG. 3 is a flowchart showing a processing procedure of a state determination circuit in FIG.

FIG. 4 is a schematic configuration diagram showing another embodiment of a clock generation unit.

[Explanation of symbols]

 2 CPU 3 Clock Generator 7 State Judgment Circuit 8 Address Monitoring Circuit 31 Buffer 32 Integration Circuit 33 Limiter 34 Voltage Controlled Variable Frequency Oscillator

Claims (1)

[Claims] 1. A state monitoring means for monitoring a program execution state by a microprocessor to determine whether or not the microprocessor is in an idle state, and determining that the state monitoring means has changed from a non-idle state to an idle state. In this case, the frequency of the clock signal supplied to the microprocessor is gradually reduced at a rate of change equal to or less than a specified value to change the frequency to a predetermined low frequency, and the state monitoring means changes from an idle state to a non-operating state. And a clock frequency increasing means for gradually increasing the frequency of the clock signal supplied to the microprocessor at a rate of change below a specified value to change the frequency to a predetermined high frequency when the idle state is determined. And a drive control device for the microprocessor.