IL99027A - Supervisory control method for computer system - Google Patents

Description

SUPERVISORY CONTROL METHOD FOR COMPUTER SYSTEM i onn worn ii^y nip:, WA nt iy SUPERVISORY CONTROL METHOD FOR COMPUTER SYSTEM BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a supervisory control method for a computer system and, more particularly, to a method for detecting a status with high probability wherein CPU is waiting for a starting of substantial next task while repeatedly processing a small loop program. Such a status is defined as "substantial rest status" specification. 2. Description of Prior Art As disclosed in, for example, Japanese Patent Laid-Open Publication No. 2-178818, it is well known in the art that based on a status of each section of a computer system, power supply is stopped to some sections which are not executing substantial task of the computer system in order to reduce total power consumption. Such technology has been put into practical use in various applications with modifications. Particularly, in a field of portable computer including lap top type personal computer with battery power supply, research of such power saving technology has been vigorously made so that the computer may work for a longer time with a smaller and lighter battery.

A certain known personal computer is provided with two kinds of stand-by functions called as rest mode and sleep mode, respectively. The rest mode is a function whereby clock frequency is changed to decrease from 16 MHZ to 1 MHZ automatically when CPU does not operate for a predetermined period of time. Further lapse of time under decreased clock frequency causes the computer to automatically enter into the sleep mode wherein power supply is stopped.. Whichever mode the computer is operating in, it returns to a normal mode by pushing any key. A user may arbitrarily set the period of time of which lapse causes the computer to enter into the stand-by mode.

Thus, the fact that CPU does not operate for substantial task for the predetermined period of time is a condition for the computer to enter into the reduced power consumption status, i.e. the stand-by mode in the above example. More specifically, when any external factor by which CPU starts to operate for substantial task, such as input signal from keyboard or a signal from communication controller, is not generated for the predetermined period of time, then the computer assumes the reduced power consumption status. In other words, CPU is determined as being substantially in the rest status when no external factor is generated for the predetermined period of time. In this known art, however, the "predetermined period of time" need be set more than several ten seconds in case of a typical personal computer, so that the power saving is still unsatisfactory.

For example, it is now assumed that a personal computer is using a word processor software for Japanese language. Each input signal at the keyboard constitutes a factor which causes CPU to start. CPU then executes various tasks depending on the input signals, the tasks including an extremely easy task such as displaying a character on a display, a little more complicated task such as transforming Kana character to Kanji character or moving documents, and a further complicated and therefore time consuming task such as file arrangement. When an operator keys while elaborating sentences, processing speed of CPU is generally far faster than keying speed of the operator. Therefore, in most instances there is a substantial rest time between key inputs, the rest time usually being from one to several seconds.

On the other hand, if the above predetermined period of time is set to several seconds, then it happens that CPU enters into the reduced power consumption mode even during CPU is executing a complicated task such as document movement or file arrangement. Thus, the predetermined period of time need be set to a sufficiently long period, i.e. several ten seconds through several minutes, from a viewpoint of safety. This prevents the power saving function from operating during the substantial rest status continuing only for a short period, which occurs frequently, resulting in unsatisfactory power saving.

To solve this problem, it may be possible to so construct the computer that CPU itself sends a signal to an external circuit constituting a power save control circuit, indicating that the power saving is now applicable, each time CPU enters into the substantial rest status. However, such a possibility would require that additional functions should be added to a software which CPU executes, and it is a very troublesome work to add such new functions to existing softwares. The present invention is based on a premise that the existing softwares can be used without any modification.

Also, if a computer system is used to execute a single software only, then the software may be analyzed in order to adequately detect the substantial rest status of CPU in which it repeatedly executes a small loop program with accessing only particular addresses. This solution, however, is not practical when various softwares are to be executed as typically experienced in the art.

The present invention has been made in view of the above technical background, and its object is to provide a method which may detect with high probability a substantial rest status of CPU wherein it is waiting for a substantial task while repeatedly executing a small loop program, by supervising signals in a system bus from outside of CPU. The invention enables such a detection in connection with various existing softwares to be executed without necessity of any modification thereto.

SUMMARY OF THE INVENTION According to the present invention, a supervisory control method for a computer system starts with the steps of storing addresses accessed by the CPU during a predetermined period of time Ta, said addresses being defined as a learned address, and of monitoring whether the CPU accesses to any address other than the learned address during a predetermined period of time Tb. When no address other than the learned address is accessed in the monitoring step, the storing step and monitoring step are repeated with decreasing in each cycle at least the period of time Ta until access to any address other than the learned address is detected in the monitoring step. A value of Ta is determined when the access is detected in the preceding step. The next step is to determine whether the CPU accesses to any address other than the learned address during a period of time Tc which is set larger than the determined value of Ta. When the determination in the preceding step is negative, the CPU is likely to be in the substantial rest status wherein the CPU waits for the substantial task while repeating a process of a small loop program.

When a computer system executes a loop program having a certain cycle, memory addresses in which are stored instructions constituting the loop are fixed for almost all instructions. Accordingly, when CPU executes a loop program repeatedly, it accesses only a limited address group. Assuming such periodic or cyclic time is To, if the above predetermined period of time Ta is longer than To, then access to any address other than the learned address is not detected at the Step 2. Ta is thus gradually decreased, and when it becomes almost egual to To access to address other than the learned address is detected. Tc is then determined based on Ta at that moment. If any address other than the learned address is not accessed during Tc, it is determined, though not definitely, that CPU is in the substantial rest status. An initial value of Ta is so set as to correspond to a maximum value of the cyclic time of loop program which renders CPU in the substantial rest status.

BRIEF DESCRIPTION OF THE DRAWING Fig. 1 is a block diagram of a computer system having a power save control device for embodying a method according to the present invention; and Figs. 2 to 4 are flow charts Part 1 to Part 3, respectively, illustrating procedures of a status judgement and power saving circuit in Fig. 1.

DETAILED DESCRIPTION OF THE INVENTION A preferred embodiment of a supervisory control method according to the present invention will now be described in detail with reference to the drawings.

Referring first to Fig. 1 of the drawings, a status judgement and power saving controller 3 is connected to a system bus 2 of computer system 1 having CPU which is an object of supervisory by the invention. An address memory and comparison circuit 4, which is operated under control of the controller 3, is connected to an address bus and a command bus . The computer system 1 is divided into several functional sections, and operating power is supplied from power supply 5, via a power supply switch circuit 6, to each functional section. The controller 3 controls the switch circuit 6 to turn the switch on or off on the basis of its determination as to whether or not CPU of the computer system 1 is in the substantial rest status in accordance with procedures as described hereinbelow.

Figs. 2 to 4 show control steps of the status judgement and power saving controller 3. After initialization of a period of time Ta at step 100, the address memory and comparison circuit 4 is cleared and then operated with an address memory mode for the time period Ta at step 101, whereby addresses which CPU has accessed during Ta are stored into the address memory and comparison circuit 4. An initial value of Ta will be determined in a manner described below. The address information stored in address memory and comparison circuit 4 is not necessarily divided into each address unit, and it is rather preferable to store the information as address blocks described later. A group of addresses which are stored in step 101 is defined as "learned address" hereinafter.

Next, the controller 3 goes on step 102 and causes the address memory and comparison circuit 4 to operate in an address comparison mode for a period of time Tb which is- set to be the same as Ta in this example. The address memory and comparison circuit 4 then compares addresses accessed by CPU during the time period Tb with the learned address in sequence, and sends a signal to the controller 3 if any address other than the learned address is accessed, such a signal being referred to as "discordance signal" below. If no address other than the learned address is accessed, that is, if discordance signal is not issued at step 102, the controller 3 goes on step 103 where it decreases the time period Ta with a decreasing ratio ct, and returns to step 101. Consequently, until any address other than the learned address is accessed at step 102, steps 101, 102 and 103 are repeated with the gradually decreased time period Ta.

This repeated process of steps 101, 102 and 103 is a "cyclic search and address learning process". That is, when CPU repeatedly executes a small loop program, the time period Ta is gradually decreased until Ta is approximated to a cycle time To of the small loop program and the circuit 4 stores the group of addresses accessed by CPU during each time period Ta. When Ta becomes almost equal to To, addresses other than the learned address is accessed at step 102 so that the controller 3 proceeds with step 200.

This step 200 is a status supervising process to monitor whether CPU accesses any address other than the learned address during a period of time Tc which in this example °is twice of the time period Ta as determined in steps 101 to 103. This is achieved by operating the address memory and comparison circuit 4 in the address comparison mode for the extended period Tc and supervising whether the circuit issues any discordance signal during that period. Unless CPU repeatedly executes the small loop program, an access to any address other than the learned address is detected at step 200. In this case, the controller 3 returns to step 100 to initialize the value of Ta and again executes the cyclic search and address learning process at steps 101, 102 and 103.

If CPU repeatedly executes the small loop program, no address other than the learned address is accessed at step 200 and the controller 3 goes on Step 210. Thus, the repetitive execution of small loop program by CPU can be detected. The situation where CPU repeatedly executes the small loop program is in most cases the substantial rest status where CPU is waiting for next substantial task. However, there are some exceptional cases. In step 210 the controller determines on the basis of various information from the computer system 1 whether any of exceptional conditions is applicable, the exceptional conditions being described later. If it is determined that no exceptional conditions is applicable, CPU is considered to be in the substantial rest status and the controller 3 goes on step 220. On the other hand, if any exceptional condition is applicable, the controller 3 returns to step 100 after a delay time Rl has elapsed. Description of delay time Rl will also be made later.

When CPU is determined to be in the substantial rest status, the controller 3 sends a power down request signal to CPU at step 220 whereby CPU starts preparation for the power down such as saving necessary data. The controller then waits for a response or signal from CPU indicating that the preparation has been completed (step 230) . Upon receiving the response from CPU, the controller proceeds with step 240 where it determines if starting condition of a return timer is applicable and, if applicable, it goes on step 300 after starting the return timer at step 250. In step 300 the controller sends a signal to the switching circuit 6 in order to stop the power supply to CPU.

Thereafter, the controller 3 proceeds with step 400 and stays there until it receives a return signal which gives CPU a substantial task, the return signal including, but not limited to, an input signal from keyboard. When the controller 3 receives the return signal, it causes the switching circuit 6 to supply the power to CPU for re-start (step 500) . Otherwise, the controller determines whether the return timer has been started (step 410) and whether the timer is up (step 411) . If the determination at step 411 is affirmative, the controller also executes step 500. Re-start control at step 500 is accomplished by first controlling the switch circuit 6 to supply the power to CPU and then sending reset signals and a re-start signal to CPU.

A subsequent step after the re-start is to determine whether the re-start was based on the time-up of return timer or on the return signal such as from the keyboard, (step 600) . If the determination is the latter, the controller 3 goes to step 200 after a delaying time R2 (step 610) . Otherwise, it returns to step 100 for executing again the cyclic search and address learning process in steps 101 to 103, after a delaying time R3 has elapsed (step 620) . These delaying times as well as the starting conditions of return timer will be described later. The initial value of Ta is set by the operation of CPU in the computer system 1 via the system bus 2 and is stored in the controller 3. It is necessary that the initial value be larger than a cycle time of small loop program to be objected. However, as the initial value becomes larger, the controller 3 should repeat the search and address learning process in steps 101 to 103 many times, resulting in a lowering of power saving efficiency. Accordingly, the initial value of Ta need be set in order to achieve an optimal power saving.

A maximum accuracy in detecting the small loop program is obtained by storing the information in the memory and comparison circuit 4 address by address. In practice, however, it is rather preferable to store the information as address blocks each of which contains a group of addresses. The addresses are grouped into the block with taking into account a sequence of addresses which may be accessed for small loop program, so that the detecting accuracy can be approximated to the maximum level. When any events that can not occur in a small loop program to be detected happened at step 200, it is determined that the exceptional conditions exist. The delaying time Rl is provided in order to avoid a repeated detection of the same program. The return signal causes CPU to execute instruction corresponding to that signal, and CPU is likely to access to any address other than the learned address. After the execution, it is highly likely that CPU again executes the small loop program which was detected before. Accordingly, the delaying time R2 is so set as to correspond to an estimated period of time necessary for CPU to complete a task based on the return signal. In case that a preceding determination at step 200 is affirmative, the controller 3 starts the return timer at step 250. Also, when a preceding re-start is caused by the return timer, the controller 3 determines that the starting condition is applicable. In case that the re-start is caused by the time-up of the return timer, there is a possibility that an error exists in the detection of small loop program. In order to avoid an occurrence of another error, the delaying time R3 is provided and set so as to correspond to an estimated period of time necessary for such loop to disappear.

As is understood from the foregoing description, the controller 3 stays in the procedures at steps 100 to 200 until it determines negative at step 200. The power down control is executed, after starting the return timer, to stop the power supply to CPU if exceptional conditions are not applicable. Thereafter, in case that the controller 3 receives no return signal, it executes the re-start control based on the time-up signal from the return timer whereby CPU is supplied with the power to resume a task, and the controller 3 returns to step 100. When a determination at step 200 is still negative and no exceptional condition is applicable, and when the controller 3 receives no return signal prior to time-up of the return timer, the re-start is again caused by the time-up signal. These processes are repeated until any change such as return signal occurs, so that CPU cyclically enters into the power down status having a period corresponding to a setting time period of the return timer.

On the other hand, in case that any return signal such as from the keyboard is sent to the controller prior to the time-up, the re-start control is immediately executed to cause CPU to resume a process which it had executed before the power down. The controller 3 goes on steps 500 - 600 - 610 - 200 in this sequence while jumping the search and address learning process at steps 100 to 103, and uses the predetermined time period Tc (= Ta x 2) for the process at step 200. When a determination here is negative and no exceptional condition exists, the controller 3 executes the power down control without starting the timer as the starting conditions are not applicable. Consequently, the re-start can only be caused by return signal.

While in the above embodiment the time period Tb is set to a value equal to Ta and Tc is twice the value of Ta, the present invention is not limited to these examples. Tb may be set larger than Ta, and may be decreased in accordance with decrease of Ta at step 103 or fixed. Tc varies depending on Ta, and may be set in such a manner as to properly detect a small loop program, such as by adding a certain value to Ta, or setting to one and a half (1.5) of Ta with or without adding a certain value thereto.

It is to be noted here that the present method requires no modification to existing softwares which the computer system is to execute and involves no necessity of analyzing the software prior to execution by the present computer system. The invention still can detect with high probability the substantial rest status of CPU during its execution of any software. By controlling the power supply to CPU based on the detection, power down of CPU can be effected even during the substantial rest status of short period, i.e. in the order of one to several seconds. This enables to significantly save the power consumption of the computer as compared with the prior art methods .

Although the present invention has been described with reference to its preferred embodiments, many modifications and alterations may be made within the spirit of the invention. Particularly, the method of the invention may be applied to achieve purposes other than the power saving control.

Claims (12)

WHAT IS CLAIMED IS:

1. A supervisory control method for a computer system including a CPU and a system bus, comprising the steps of: storing addresses accessed by the CPU during a predetermined period of time Ta, said addresses being defined as a learned address ; monitoring whether the CPU accesses to any address other than said learned address during a predetermined period of time Tb; when no address other than said learned address is accessed in the monitoring step, repeating the storing step and monitoring step with decreasing in each cycle at least said period of time Ta until access to any address other than said learned address is detected in the monitoring step; determining a value of Ta when the access is detected in the preceding step; determining whether the CPU accesses to any address other than said learned address during a period of time Tc which is set larger than the determined value of Ta; and when the determination in the preceding step is negative, determining that the CPU is likely to be in a substantial rest status wherein the CPU waits for a substantial task while repeating a process of a small loop program.

2. A supervisory control method for a computer system as claimed in claim 1, wherein said period of time Tb is equal to said period of time Ta.

3. A supervisory control method for a computer system as claimed in claim 1, wherein said period of time Tb is longer than said period of time Ta.

4. A supervisory control method for a computer system as claimed in claim 1, wherein said period of time Tc is twice said determined value of said period of time Ta.

5. A supervisory control method for a computer system as claimed in claim 1, further comprising the step of stopping a power supply to the CPU when the CPU is determined to be in the substantial rest status.

6. A supervisory control method for a computer system as claimed in claim 5, further comprising the step of determining prior to the power down step whether there exists an exceptional condition which prevents the CPU from being considered in said substantial rest status.

7. A supervisory control method for a computer system as claimed in claim 5, further comprising the step of re-starting the power supply to the CPU.

8. A supervisory control method for a computer system as claimed in claim 7, wherein the re-starting step is executed when a return signal occurs.

9. A supervisory control method for a computer system as claimed in claim 7, wherein the computer system further includes a return timer, and the method further comprising the steps of determining whether there exists a starting condition for the return timer and of starting the return timer when exists prior to the power down step.

10. A supervisory control method for a computer system as claimed in claim 9, further comprising the steps of determining whether the return timer is started and of re-starting the power supply when a time-up signal is issued from the return timer.

11. A supervisory control method for a computer system as claimed in claim 10, further comprising the step of determining whether the re-start is based on the return signal or the time-up signal.

12. A supervisory control method for a computer system substantially as hereinbefore described and with reference to the accompanying drawings. FOR THE APPLICANT WOLFF, BREGMAN AND GOLLER