JPH0612258A - Memory for fuzzy set processing - Google Patents

Abstract

PURPOSE:To perform fuzzy set arithmetic at high speed with simple configuration by providing a memory equipped with the function of logical arithmetic concerning a memory constituting a computer system. CONSTITUTION:At the time of write to the memory, logical arithmetic is performed between newly given data and data already stored in the address of the memory, and a register 13, logical arithmetic part 14 and control terminal 25 are added to the conventional memory so as to store the result in the memory. Thus, it is only required for one time of fuzzy logical arithmetic to transfer data twice so as to easily realize high-speed fuzzy logical arithmetic without load for a CPU.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory which is capable of performing a fuzzy operation at a high speed with a simple structure by adding a fuzzy set operation function to a memory used as a main memory of a computer. .

[0002]

2. Description of the Related Art With the progress of application of fuzzy theory, it has become common practice to implement fuzzy reasoning processing by hardware. However, the execution of fuzzy inference is not enough to cover a wide range of applications including learning of inference rules and membership functions, and the processing of numerical operations. A method of combining circuits and a method of adding a maximum value operation (Max) and a minimum value operation (Min) to an instruction set of a general-purpose CPU have been considered (eg, International Fuzzy Engineering Symposium Proceedings, No. 387). Pages 398 (Proc. Of the International
al Fuzzy Engineering Symp
osium91 pp. 387-398).

Maximum value arithmetic and minimum value arithmetic are frequently used in fuzzy theory applications. In fuzzy reasoning in control, the Max-min combining method is often used as a reasoning combining method. In fuzzy inference by the Max-Min method, inference execution results in an operation in which a maximum value operation and a minimum value operation are sequentially repeated between a fuzzy set given as an input and a fuzzy set forming a rule.
In the system, the fuzzy set is as shown in FIG.
As shown in, the grade values can be expressed by arranging them in sequence. The execution of the inference results in sequentially performing the maximum value operation and the minimum value operation between the grade values expressed in this way.

The structure of a conventional memory is as shown in FIG. Address buffer 1 and column decoder 2,
The row decoder 3 decodes the address given to the address terminal 22 and specifies an address in the memory cell array 4. An input data control 11 and an output data control 12 are provided to control the flow of data,
The flow of data between the memory cell array 4 and the data input / output terminal 21 is controlled via the sense switch 5.

In operation, the control signal given to the chip select terminal 23 and the write enable terminal 24 is applied to the control section 15.
Is performed and the input data control 11 and the output data control 12 are controlled. The operation of this control unit is as shown in (Table 1).

[0006]

[Table 1]

That is, L is applied to the chip select terminal 23,
When H is given to the write enable terminal 24, the read mode is set, and the input data control is enabled and the output data control is disabled.
As a result, the content of the specific address of the memory cell array 4 is output to the data input / output terminal 21. When L is applied to the chip select terminal 23 and L is applied to the write enable terminal 24, the write mode is set, and the input data control is disabled and the output data control is enabled. The obtained data is stored in the memory cell array 4. When H is given to the chip select terminal 23, it does not operate effectively.

The flow of calculation by a computer configured using such a conventional memory will be described with reference to FIG. When performing a fuzzy set operation, two elements of the fuzzy set are fetched from the memory (1) (2) and these are C
It is stored in the register of PU, and the CPU performs predetermined calculations such as minimum value calculation and maximum value calculation (3). One operation is completed by storing the result of this operation in another address (4).

By the way, the minimum value calculation and the maximum value calculation are not provided in a general CPU. Therefore, generally, when performing the maximum value operation or the minimum value operation, the comparison instruction and the branch instruction are combined and executed. Considering the loading of data into the CPU register, 3 instructions are required. For the purpose of speeding up fuzzy calculation, C
Maximum value calculation (MA for PU instruction set)
X) and the minimum value operation (MIN) are added, the maximum value operation and the minimum value operation can be executed by one instruction, and the fuzzy logic operation can be speeded up.

[0010]

However, the following problems have been observed in the above-mentioned conventional structure. That is, since it is necessary to send input data to the fuzzy set processing unit and transfer output data to the memory, memory access is required three times for each fuzzy logic operation. Therefore, even if instructions for maximum value calculation and minimum value calculation are added to the CPU, the processing speed of the entire computer system may be limited by the ability of data transfer between the memory and the CPU.

In addition, in the method mentioned above, CP
To change U's instruction set itself, C
It is necessary to change the PU design itself. In addition, since it is necessary to control the hardware specific to fuzzy set processing, the hardware configuration of the entire computer becomes complicated, and the software such as the compiler is burdened by special control, which is a problem. It was

The present invention solves the above-mentioned conventional problems. By adding a fuzzy logic operation function to the memory itself, the overhead due to data transfer is reduced,
It is an object to provide a high-speed fuzzy operation with a simple structure.

[0013]

In order to achieve this object, the fuzzy set processing memory of the present invention is provided with a register and a logical operation unit inside the memory, and the contents of the address of the memory cell and new data input / output are provided. A logical operation is performed with the data given to the terminal, and the result of this logical operation is stored again at the relevant address of the memory cell, and the type of operation performed by this logical operation unit is set by external input. A switching control unit and control terminal are provided.

[0014]

With the operation of the logical operation unit, in the operation of writing to the memory, the result of the logical operation between the data already stored at the specified address and the data newly given as the write data is newly added. It becomes possible to memorize. Since this logical operation unit can be controlled externally, it is possible to switch to a fuzzy set operation such as a sum operation or a product operation.

Therefore, the fuzzy set operation can be performed by substantially the same procedure as the memory transfer, and the high-speed fuzzy set operation can be realized with a simple structure. For example, the binomial fuzzy set operation, which requires three memory accesses and one CPU operation per grade in the conventional method, can be processed by only two memory transfer procedures. As a result, the load on the central processing unit (CPU) can be reduced and the overall calculation speed can be increased.

Further, by substituting one of the address terminals for the control terminal, it is possible to construct a memory having a pin arrangement compatible with the conventional memory.
This makes it possible to use the conventional computer as a computer suitable for fuzzy set processing more easily.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A fuzzy set processing memory according to a first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment in which the present invention is applied to a static RAM. Figure 1
In regard to the basic part, since it has the same configuration as the conventional memory shown in FIG. 4, the same components are designated by the same reference numerals and detailed description thereof will be omitted. Unlike the conventional memory, in this embodiment, there is a logic between the register 13 for temporarily storing the contents read from the memory cell array 4 and the contents of the register and the data given to the data input / output terminal. A logical operation unit 14 for performing an operation is newly provided, and a control terminal 25 is provided to control the operation of the logical operation unit 14. The operation of the control unit 15 is as shown in (Table 2) unlike the conventional memory.

[0019]

[Table 2]

The operation of this embodiment will be described below, focusing on the operation of the control section 15. In this embodiment, the read operation is similar to that of the conventional memory, but the write operation is as follows.

The writing operation is divided into three stages. An address is given to the address terminal 22, and L is given to the chip select terminal 23 and the write enable terminal 24.
Is given, the first stage starts first, and the operation of reading from the memory cell array is performed. Similar to the conventional data read operation of the memory, the input data control 11 is enabled, the output data control 12 is disabled, and data is read from the memory cell array 4 via the sense switch 5. Then, the read data is latched in the register 13. In the second stage, logical operation unit 14 performs a predetermined logical operation between the data applied to data input terminal 21 and the data latched in register 13. Then, in the third stage, the result of this logical operation is written in the memory cell array 4.

As a whole, a new data input / output terminal 2 is provided.
It serves to store again the result of the logical operation between the data given to 1 and the data already stored at the address. Switching of each stage is controlled according to a timer inside the logical operation unit.

There are three prepared operations: maximum value operation, minimum value operation, and no operation. The following calculations are performed respectively.

Maximum value operation MEM <-IN max REG Minimum value operation MEM <-IN min REG No operation MEM <-IN However, data given to IN input terminal REG register value ONE 1 internal expression MEM memory Data given to cell array All of these operations can be realized by a simple circuit and do not require a large chip area. Further, since the operation speed can be performed at high speed, the operation described above can be performed within the range of the write cycle of the conventional memory by using a high speed memory circuit.

When the operation is set to no operation, the data supplied to the data input / output terminal 21 is directly input to the memory cell array 4. In this case, the operation is the same as that of the conventional memory.

The type of logical operation is controlled by using the control terminal 25. The control terminal 25 is always kept at H at the time of writing to or reading from a normal memory, but when L is given to this, the control unit controls the logical operation unit to switch the operation type. To do. That is, when L is applied to the chip select terminal 23 and L is applied to the control terminal 25, the input data control 11 is enabled and the output data control 1
2 is disabled, and the type of operation performed by the logical operation unit 14 is selected according to the data applied to the data input / output terminal 21. For this control terminal, one of the address terminals used in the conventional memory is used by being allocated to it. This effectively uses only half the address space, which reduces storage capacity, but by replacing the existing computer's memory without changing external hardware, the fuzzy set computer Can be configured.

Next, the operation of switching the type of calculation will be described. The most significant bit of the address terminal of the conventional memory is used as the control terminal. If the address space in the conventional memory is 64 kilobytes from 0x0000 to 0xFFFF, the effective address space in this embodiment is 0x80.
It is 32 kilobytes from 00 to 0xFFFF. And 0x00
All access to the space from 00 to 0x7FFF means switching the operation.

For example, data 0x for address 0x0000
When 0000 is written, no calculation is set, and when data 0x0001 is given, maximum value calculation is set. This operation is performed by the control unit 15
When an operation switching signal is given from the logical operation unit 14 from
Logical operation unit 1 according to the signal given to the data input terminal
4 It can be controlled by rewriting the internal registers or flags. Therefore, the operation of switching the type of operation can be realized as an operation of writing data to a specific address space. Therefore, the memory of the present embodiment is used in place of the conventional memory without changing the configuration of the computer, and the software of the present embodiment is used. High-speed processing of fuzzy set operations can be easily realized simply by changing the level.

The flow of processing when a fuzzy operation is performed by a computer constructed using the memory of this embodiment is as follows. When the product set of two fuzzy sets FA and FB is stored in FC, FA (n) represents the address of the nth element of the fuzzy set FA, and the operation type is set to no operation FA (1)-> FC (1) FA (2)-> FC (2) ・ ・ FA (n)-> FC (n) Set the calculation to the minimum value calculation FB (1)-> FC (1) FB ( 2)-> FC (2) ... FB (n)-> FC (n). However, 'X->Y'indicates that the contents of address X are written to address Y. If the number of elements in each fuzzy set is large, the time required to set the type of operation can be ignored and the amount of transfer between memories becomes 2 * n.
This eliminates the transfer between the CPU and memory and transfers the first operand to the destination address, as shown in FIG.
This is because the calculation is performed only by the procedure of (1), which transfers the second operand to the target address, and (2), which is a two-time memory transfer. The transfer between the memories can be executed at high speed without burdening the CPU by using the DMA controller.

Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram of a memory according to the second embodiment of the present invention. Since the basic structure is the same as that of FIG. 1, the description thereof is omitted, and only the different points will be described below. In the present embodiment, the logical operation unit 14 performs a logical operation between the data read from the memory cell array and the data supplied to the data input / output terminal, and the register 13 is used by the logical operation unit 1.
Used to temporarily store the output from 4. The control unit 15 is also provided with the same one, but the operation is as shown in (Table 3).

[0031]

[Table 3]

That is, although the operation at the time of writing is divided into three stages, the address terminal 2
When an address is given to 2 and L is given to the chip select terminal 23 and the write enable terminal 24, first the first
Stage is started, and the reading operation from the memory cell array is performed. The input data control 11 is enabled, the output data control 12 is disabled, and data is read from the memory cell array 4 via the sense switch 5. In the second stage, the data read in the first stage is immediately supplied to the logical operation unit 14, the logical operation is executed, and the result of the logical operation is latched in the register 13. Finally, in the third stage, the contents of 13 are written in the register in the relevant part of the memory cell array 4. As a result of the above operation, the first
Similar to the embodiment described above, it functions to store the result of the logical operation between the data newly applied to the data input / output terminal 21 and the data already stored at the address.

In the above-mentioned embodiments, one of the address terminals of the conventional memory is used instead of the control terminal, but it is also possible to provide a dedicated terminal as the control terminal. When the dedicated terminal is provided, the address space can be effectively utilized by allocating a part of the address space to the control terminal of each memory at the level of a module including a plurality of memories. This configuration is effective when the memory is used in module units.

Similarly, it is possible to assign one of the results of the address decoding to the control terminal and assign one of the address spaces assigned to the memory to the input to the control terminal. With this configuration, most of the memory space allocated to the memory can be allocated to the storage, and therefore the memory space is used efficiently. However, special handling is required for the addresses assigned for control, so care must be taken when creating software.

Further, in the above-mentioned embodiments, there are three types of calculation, maximum value calculation, minimum value calculation, and no calculation.
This combination is suitable for performing the fuzzy inference of Max-Min method, and it is effective to use another combination for different inference methods. For example, Ma
When the inference based on the x-Product method is used, the product operation may be added to the types of operations performed by the logical operation unit.

Further, in the embodiment, the static R of the present invention is used.
The application to AM is shown as an example, but dynamic RAM
Needless to say, the present invention can be applied to a memory having other configurations and has the same effect.

[0037]

As described above, according to the present invention, with respect to a memory used as a main memory of a computer, a register which temporarily holds data read from a memory cell and a register which is saved in the register when writing to the memory are provided. By providing a logic operation unit for performing a fuzzy logic operation between the new data and the data newly given as the write data, the fuzzy operation can be performed by the memory transfer operation. By using this memory, high-speed fuzzy set calculation can be performed with a simple structure.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a memory according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a flow of calculation by a computer using the same embodiment.

FIG. 3 is a block diagram showing a configuration of a memory according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional memory.

FIG. 5 is a diagram showing a flow of calculation by a computer using a conventional memory.

FIG. 6 is a conceptual diagram showing a representation method of a fuzzy set in a computer.

[Explanation of symbols]

 1 Address Buffer 2 Column Decoder 3 Row Decoder 4 Memory Cell Array 5 Sense Switch 11 Input Data Control 12 Output Data Control 13 Register 14 Logical Operation Section 15 Control Section 21 Data Input / Output Terminal 22 Address Terminal 23 Chip Select Terminal 24 Write Enable Terminal 25 Control Terminal

Claims (2)

[Claims] 1. A random access memory device used as a storage device of a computer system, comprising: an address decoder for expanding an address given to an address terminal; a memory cell for storing data; and a data input / output for inputting / outputting data. In addition to the output terminal, a register for temporarily storing the data read from the memory cell and an operation is performed between the data stored in the register and the data given to the data input / output terminal as new write data. A logical operation unit that supplies the result to the memory cell, a control unit that switches the operation of the logical operation unit by an external input, and a control terminal are provided, and correspond to the address given to the address terminal when writing to the memory. The contents of the memory cell are temporarily saved in the register, and the contents of the register and data input / output The results to write to the memory cell performs a logical operation between the data given to the child,
Further, when a signal is applied to the control terminal, the operation of the control unit switches the kind of operation set in the operation unit to an operation determined by the data applied to the data input / output terminal. Memory for fuzzy set processing. 2. A random access memory device used as a storage device of a computer system, comprising an address decoder for expanding an address applied to an address terminal, a memory cell for storing data, and a data input / output for inputting / outputting data. In addition to the output terminal, a logical operation unit that performs an operation between the data read from the memory cell and the data newly given to the data input / output terminal as write data, and supplies the result to a register, and the logical operation unit A register for temporarily storing the output, a control unit for switching the operation of the logic operation unit by an input from the outside and a control terminal are provided, and when writing to the memory, the memory cell corresponding to the address given to the address terminal is A logical operation is performed between the contents and the data given to the data input / output terminal, and the result is When the signal is given to the control terminal after the contents of this register are temporarily stored in the register, or when a signal is given to the control terminal, the operation of the control section causes the operation type set in the operation section to be changed to the data. A fuzzy set processing memory, characterized in that it is configured to switch to an operation determined by data given to an input / output terminal.