JPH06121591A - Microcomputer - Google Patents

Abstract

PURPOSE:To provide a microcomputor for blocking through current at the time of switching a motor while realizing high speed switching. CONSTITUTION:The microcomputor comprises an output latch 6 connected with a buffer register 5, a delay circuit 7 connected between the output latch 6 and output ports P0-P5, a selector 12 selecting register sections 11a, 11b in a compare register 10, and a selector 18 selecting register sections 17a, 17b in a delay designation register 16. A delay time set by a selected delay designation register 16 is stored in a delay storage register 19 and a data, representative of a motor currently controlled, is stored at a motor designation flag 22 through a port output times storing register 20 and an output times counter 21. High speed switching is realized because switching of motor is carried out not through interruption processing based on a command fed from an interruption control section 14 but through utilization of a motor switching request signal being fed upon inversion of the motor designation flag 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer for controlling terminal output in real time.

[0002]

2. Description of the Related Art Conventionally, there is a type of microcomputer (hereinafter referred to as a microcomputer) which has a built-in peripheral circuit called a single-chip microcomputer (or a one-chip microcomputer). This peripheral circuit includes an interrupt controller, a DMA (direct memory access) controller, a timer, a serial interface, etc., and controls various systems. The target microcomputer has a peripheral circuit that controls a terminal (hereinafter referred to as a port) that outputs a plurality of waveforms for controlling a motor to the outside.

FIG. 5 is a block diagram of a microcomputer showing such a conventional example. As shown in FIG. 5, the microcomputer 1a has a C
It includes a PU 2, an interrupt control unit 14a, and a port output control unit 3 that outputs the value of the buffer register to the six ports P0 to P5 at each designated time, and are connected by an internal bus 4. This port output controller 3a
Holds the data output to the ports P0 to P5 and the buffer register 5 including the register unit 23 of the bits a to f for storing the data to be output next to the ports P0 to P5. Of the output latch 6 and a timer for counting the time interval during which the output latch 6 latches the value of the buffer register 5.
Counter 8 and a compare that specifies the time interval
A comparator 13 that compares the value of the timer counter 8 and the value of the compare register 10a with the register 10a and outputs a match signal 101 to the output latch 6 if they match.
And a timer / counter start bit ST9 for starting the counting operation of the timer / counter 8, and the first motor 29.
Also, the port output count storage register 20 that stores the number of times the data is output before the second motor 30 is switched by the motor control unit 28, and the motor switch request signal 10 that counts this output count and receives the coincidence signal 101.
It is composed of an output counter 21a for outputting 3a.

FIG. 6 is a timing chart of the port output in FIG. As shown in FIG. 6, here, the port outputs P0 to P5 and the operation of the first and second motors from the timer start are shown. N1 and N2 are the numbers of port outputs to the first and second motors, respectively. Hereinafter, description will be given with reference to FIGS. 5 and 6.

First, the port P0 is instructed by the instruction of the CPU2.
~ Output latch 6 outputs the first output value ("100011" in Fig. 6) to the first motor 29 connected to P5.
In addition, the second output value (“110001” in FIG. 6) to the first motor 29 is output to the buffer register 5, and the value corresponding to the period in which the first output value is output to the ports P0 to P5 (in FIG. 6, T11) to compare register 10a
In addition, the port output count (N1 in FIG. 6) for the first motor 29 is stored in the output count counter 21a, and the port output count (N2 in FIG. 6) for the second motor 30 is stored in the port output count storage register 20 in advance. Set it. After that, the timer / counter start bit ST9
Is set to "1" to start the counting operation of the timer / counter 8.

The timer counter 8 is set to "0" when the timer counter start bit ST9 is set to "1".
It is cleared and the counting operation of incrementing by "1" is started each time the rising edge of the internal clock CLK input is detected. Further, since the comparator 13 constantly compares the value preset in the compare register 10a with the value of the timer counter 8, the result obtained by the increment of the timer counter 8 is the compare register 10
When it matches the value set in a, the match signal 101 is activated. When the match signal 101 is activated, the value of the buffer register 5 is latched by the output latch 6 and output to the ports P0 to P5. That is, 2 for the first motor 29 stored in the buffer register 5.
The output value of the port for the second time is latched by the output latch 6 and output to the ports P0 to P5. Further, the activation of the coincidence signal 101 initializes the value of the timer / counter 8 to "0", and starts the counting operation for incrementing each time CLK is input again.

On the other hand, the coincidence signal 101 is supplied to the interrupt control section 14a as a timer interrupt request signal, and is also supplied to the output number counter 21a as an output number detection signal. When detecting that the coincidence signal 101 is activated as the timer interrupt request signal, the interrupt control unit 14a outputs the interrupt processing request signal 100 to the CPU 2.

Next, the CPU 2 sends an interrupt processing request signal 1
When it is detected that 00 is activated, the program processing being executed is interrupted and the interrupt program processing is started.
In this interrupt processing routine, the third output value (“111000” in FIG. 6) for the first motor 29 is output to the ports P0 to P5 in the buffer register 5, and the second output value for the first motor 29 is output. Ports P0-P5
The value (T12 in FIG. 6) corresponding to the period to be output to is set in the compare register 10a. Further, when the output number counter 21a detects that the coincidence signal 101 as the output number detection signal is activated, it starts the counting operation of decrementing "1".

By this decrement operation, when the output counter 21a becomes "0", the motor switching request signal 103a is activated. Therefore, when the motor switching request signal 103a is activated, the port output number storage register 20 presets the preset port output number (N2 in FIG. 6) to the second motor 30 in the output number counter 21a.

On the other hand, when the interrupt controller 14a detects that the motor switching request signal 103a has been activated, it outputs the interrupt processing request signal 100 to the CPU 2 again. When the CPU 2 detects that the interrupt processing request signal 100 is activated, the program processing being executed is interrupted and the interrupt program processing is started. In this interrupt processing routine, the first output (“1000 in FIG. 6” to the second motor 30 is output to the ports P0 to P5.
11 ") is set in the output latch 6. Similarly, the second
Second output value to the motor 30 (in FIG. 6, “11
0001 ") to the buffer register 5 and a value (T21 in FIG. 6) corresponding to the period during which the first output value for the second motor 30 is output to the ports P0 to P5.
The port output count (N1 in FIG. 6) for the first motor 29 is set in the register 10a in the port output count storage register 20, respectively. After that, the timer / counter start bit ST9 is set to "1" to start the counting operation of the timer / counter 8.

In this way, the value of the compare register 10a set by the CPU 2 is compared with the value of the timer counter 8 by the comparator 13. Further, when the period (T21 in FIG. 6) of outputting the first output value to the second motor 30 to the ports P0 to P5 has elapsed, the value of the timer counter 8 and the value of the compare register 10a match. As described above, the value of the buffer register 5 is latched in the output latch 6. Since the buffer register 5 stores the output value of the second motor 30 to the port for the second time, after the period for outputting the first output value elapses, the second motor 30 outputs the second value. The output value of the second time is output to the ports P0 to P5.

By repeatedly executing the above-described processing, the coincidence signal generated when the period for outputting the n-th output value to the corresponding motor port is completed causes (n +
1) The output value of the first time is output to the port. In the interrupt processing routine activated by this match signal, the (n + 2) th port output value is output to the buffer register 5, and the (n + 1) th output value is output to the port during the compare register. By setting each to 10a, the port output value can be switched and output to the port every arbitrary period. Moreover,
The motor can be switched by an interrupt processing routine that is started by a switching signal output when the port output corresponding to the number of output times to the corresponding motor is completed.

[0013]

In the microcomputer provided with the conventional port output control section described above, the ports P0 to P
The output waveform of No. 5 is used as a three-phase inverter motor output waveform to control the motor, and the ports P0, P1,
P2 is a three-phase waveform output (U phase, V phase, W phase), P3, P
4 and P5 are used as the opposite phase waveforms (U inversion phase, V inversion phase, W inversion phase).

At this time, the output of each port may not be switched at the same time due to the switching of the port output. For example, at the timing of FIG. 6, when switching from the third output to the fourth output, P0 (U phase) and P3
The output value of (U inversion phase) changes. In this case, the comparator 1
Depending on factors such as the length of the signal line transmitting the coincidence signal 101 from 3 to each latch, the characteristics of each latch, the length of the signal line from each latch to the port, etc., the output of P3 (U inversion phase) is switched The replacement may be delayed from P0 (U phase). Therefore, in such a case, P0 (U phase) and P3 (U phase)
There is a drawback in motor control in that the outputs of the reversed phase) become "0" at the same time for a moment and a through current flows.

Further, conventionally, when a plurality of microcomputers are used to control a plurality of motors, the hardware becomes large and the cost is high. Therefore, one microcomputer controls the time division. However, since the motors are switched by interrupt processing to the CPU, there is also a drawback that the motors cannot be switched at high speed.

It is an object of the present invention to provide a microcomputer capable of preventing such a shoot-through current at the time of switching a motor and realizing high-speed switching.

[0017]

The microcomputer of the present invention is provided with a terminal output value holding means for holding data being output to an output terminal for outputting data to the outside, and a next output to the output terminal. Of the next data storage means for storing data to be stored, at least two storage time storage means for storing the time for storing the value of the next data storage means in the terminal output value holding means, and the next data storage means. The value of the next data storage means is stored in the terminal output value holding means when the time interval for storing the value in the terminal output value holding means is measured and the measured result matches the value of the storage time storage means. Means, and at least two delay time storage means for storing a delay time from the time when the value of the next data storage means is stored in the terminal output value holding means to the time when the value is output to the output terminal, Immediately after the delay time from the time when the value of the next data storage means is stored in the terminal output value holding means to the time of outputting to the output terminal is measured and the value of the next data storage means is stored in the terminal output value holding means The value of the terminal output value storage means is output to the output terminal or the value of the terminal output value storage means is output to the output terminal when the result of measuring the delay time matches the value of the delay time storage means. Means for selecting and outputting either one of the output according to the value stored in the terminal output value storage means, and the number of times data is output to the output terminal is measured, and the measured value becomes a predetermined value. And a means for outputting a switching signal at the time of switching, and a means for switching between the delay time storage means and the storage time storage means according to the switching signal. Configured to output the data to.

[0018]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of a microcomputer showing an embodiment of the present invention. As shown in FIG. 1, a microcomputer 1 of this embodiment includes a CPU 2 and a CP
The interrupt control unit 14 for U2 and the port output control unit 3 for outputting the value of the buffer register 5 to the ports P0 to P5 at every designated time are provided and are connected to each other by the internal bus 4.

Of these, the port output controller 3 stores a buffer register 5 for storing the data to be output next to the ports P0 to P5 and an output latch 6 for holding the data output to the ports P0 to P5. And a timer / counter 8 that counts the time interval at which the output latch 6 latches the value of the buffer register 5, and a compare register that includes two compare register units 11a and 11b that specify the time interval. 10, a selector 12 for selecting the compare register 10, a comparator 13 for comparing the value of the timer counter 8 and the value of the compare register 10, and a timer counter for starting the counting operation of the timer counter 8. The start bit ST9, the delay counter 15 that counts the delay time, and the delay time The delay designating register 16 having two delay designating register sections 17a and 17b for presetting, a selector 18 for selecting the value of the delay designating register 16 and setting in the selected delay designating register section 17a or 17b. When the values of the delay storage register 19 for storing the generated delay time and each latch unit 24 of the output latch 6 are “0”, the ports P0 to P5
A delay circuit 7 for delaying the output timing to the port, a port output count storage register 20 for storing the number of times data is output before the motor control unit 28 switches the first and second motors 29, 30, and It is composed of an output counter 21 for counting the number of outputs and a motor designation flag F22 indicating which motor is currently controlled.

FIG. 2 is a timing chart of the port output in FIG. As shown in FIG. 2, the present embodiment is also a case of outputting to six ports. First, when starting the port output operation, the ports P0 to P
5, the first output value (“000111” in FIG. 2) for the first motor 29 is preset in the output latch 6. Similarly, the second output value for the first motor 29 (“100011” in FIG. 2) is stored in the buffer register 5, and the first output value for the first and second motors 29, 30 is stored in the ports P0 to P5. The values (T11 and T21 in Fig. 2) corresponding to the period output to
In the register units 11a and 11b of the register 10, values corresponding to the delay time when switching the port output to the first and second motors 29 and 30 from "1" to "0" (D1 and D2 in FIG. 2 respectively). ) In the register portions 17a and 17b of the delay designation register 16 for the first motor 2
The value (D1 in FIG. 2) corresponding to the delay time when the port output for 9 is switched from "1" to "0" is stored in the delay storage register 19 and the number of port outputs to the first motor 29 (N1 in FIG. 2). ) Output counter 2
1, the number of port outputs to the second motor 30 (see FIG.
Then, N2) is preset in each of the port output count storage registers 20. Then, the timer / counter start bit ST9 is set to "1" to start the counting operation of the timer / counter 8.

In this timer / counter 8, ST9 is "1".
Set to 0, it is cleared to "0" and the internal clock C
It is incremented by "1" every time the rising edge of the LK input is detected. The comparator 13 constantly compares the value preset in the compare register 10 with the value of the timer counter 8, and as a result of the increment of the timer counter 8, it coincides with the value set in the compare register 10. At this time, the coincidence signal 101 is activated. When this coincidence signal 101 is activated, the value of each bit 23 of the buffer register 5 corresponds to the latch unit 2 of the output latch 6.
4 respectively.

However, since the buffer register 5 previously stores the second output value for the first motor 29 in the ports P0 to P5, the latch section 24 of the output latch 6 stores the second port value. The output value is latched. Further, the activation of the coincidence signal 101 causes the value of the delay storage register 19 to be preset in the delay counter 15, and the delay counter 15 decrements "1" every time it detects the rising edge of the internal clock CLK input. Start operation. When the delay counter 15 becomes "0" by this decrement operation, the coincidence signal 102, which is a one-shot pulse, becomes active and the delay counter 1
5 stops the counting operation.

Here, the output to the port P2 will be described as an example. First, as described above, the second output value to the port P2 is latched in the latch section c of the output latch 6, but when the latched value is "1", it is a set / reset type. Flip flop 2
5 is set, and "1" is output to the port P2.

On the other hand, when the value stored in the latch section c is "0", the output value of the inverter 26 becomes "1" and is input to the AND gate 27, but the input value of the other coincidence signal 102. AND gate 27 until becomes "1"
The output value of is still "0". Thereafter, as described above, when the count of the delay period by the delay counter 15 is completed, the coincidence signal 102 is activated and becomes "1", so that the output value of the AND gate 27 is "1".
become. Therefore, the flip-flop 25 is reset and "0" is output to the port P2.

Similarly, for the other bits, when the value stored in the latch section is "1", "1" is output to the port immediately after being latched, and vice versa. Outputs "0" to the port after the delay time has elapsed.

The match signal 101 is supplied to the interrupt controller 14 and the output counter 21. When detecting that the coincidence signal 101 is activated, the interrupt control unit 14 supplies the interrupt processing request signal 100 to the CPU 2. When the CPU 2 detects that the interrupt processing request signal 100 is activated, the CPU 2 interrupts the program processing being executed and starts the interrupt program processing. In this interrupt processing routine, port P
From 0 to P5, the third output value (“111000” in FIG. 2) to the first motor 29 is stored in the buffer register 5
In addition, the value (T12 in FIG. 2) corresponding to the second output period for the first motor 29 is set to the compare register unit 11
Set to a respectively.

On the other hand, when the output signal counter 21 detects that the coincidence signal 101 is activated, it decrements by "1". When the output number counter 21 becomes "0" by the decrement operation, the borrow from the output number counter 21 inverts the motor designation flag F22 and generates the motor switching request signal 103. By the motor switching request signal 103, the motor control unit 28 switches the controlled motor from the first motor 29 to the second motor 30.

When the motor switching request signal 103 is activated, the selector 18 causes the delay designating register 16 to operate.
Of the delay designation register unit 17a for designating the delay time for the second motor 30.
b, and the delay time (D2 in FIG. 2) for the second motor 30 is set in the delay storage register 19.
At this time, the port output count storage register 20 presets the preset port output count for the second motor 30 in the output count counter 21.

Further, the selector 12 stores the value (T21 in FIG. 2) corresponding to the first output period for the second motor 30 in the register section 11a in the compare register 10 by activating the motor switching request signal 103. It is switched to the register section 11b which is operating.

However, the CPU 2 uses the interrupt request signal 1
When 00 is detected, the program processing being executed is interrupted and the interrupt processing program is started. In this interrupt processing program, the CPU 2 reads the value of the output counter 21, and when the value is "1", the second value is sent to the ports P0 to P5.
Output value to the motor 30 of
111) is set in the buffer register 5. When the value of the output counter 21 is "0", the second motor 3
The second output value for 0 (100011 in FIG. 2) is stored in the buffer register 5, the port output count (N1 in FIG. 2) for the first motor 29 is stored in the port output count storage register 20, and the first motor 29 is stored. A value (T11 in FIG. 2) corresponding to the first output period is set in the register section 11a of the compare register 10. After that, the timer / counter start bit ST9 is set to "1" to start the counting operation of the timer / counter 8.

As described above, the value of the register section 11b of the compare register 10 set by the CPU 2 is
It passes through the selector 12 and is compared with the value of the timer counter 8 by the comparator 13. Therefore, one for the second motor 30
When the period for outputting the output value for the second time (T21 in FIG. 2) has elapsed, the comparator 13 detects a match between the value of the timer counter 8 and the value of the register section 11b of the compare register 10, and The same operation as the first match detection for the motor 29 is performed. Also, when switching from the second motor 30 to the first motor 29, the same operation as when switching from the first motor 29 to the second motor 30 is performed.

By repeating the above processing, when the output value to the port is "0", the value output to the port can be switched at high speed while delaying the output timing to the port. It is possible to prevent a through current at the time of switching. Further, by inverting the motor designation flag by the signal output when the port output to the corresponding motor has finished the predetermined number of times, the motor can be switched at high speed using the switching signal output to the port. .

FIG. 3 is a delay circuit diagram in a microcomputer for explaining another embodiment of the present invention, and FIG. 4 is a circuit diagram of FIG.
3 is a timing diagram of port output in FIG. As shown in FIGS. 3 and 4, this embodiment has substantially the same configuration as that of the above-described embodiment of FIG. 1 except for the delay circuit 7. The delay circuit 7 will be described below, but FIG. 1 is used for the other circuits.

First, the delay circuit 7 is a logic circuit for delaying the timing of outputting to the port when the value of each of the latch parts a to f of the output latch 6 is "1", and the flip-flop 25 and the inverter 26 are provided. And AND gate 2
7 and 7. Also, in this embodiment, similarly to the above-described embodiment, the output to the port P2 is taken as an example.

Next, the output latch section c24 causes the value of the bit section c23 of the buffer register 5 to be changed by the match signal 101 which is activated when the value of the compare register 10 and the value of the timer counter 8 match. Is latched. When the value latched by the output latch unit c is "0", the output value of the inverter 26 becomes "1", and
The reset flip-flop 25 is reset and "0" is output to the port P2.

On the other hand, when the value latched by the output latch 6 is "1", "1" is input to the AND gate 27, but the coincidence signal 102 which is the output of the other delay counter 15 is input. The output value of the AND gate 27 remains "0" until the value becomes "1". That is, the delay counter 15 counts the delay time as in the above-described embodiment. This delay counter 15
When the counting of the delay time due to
02 is activated and becomes "1", so the AND gate 27
Has an output value of "1", the flip-flop 25 is set, and "0" is output to the port P2. The output to the other ports P0, P1, P3 to P5 is also performed by the same operation as the port P2.

By repeating this processing, when the output value to the port is "1", the value to be output to the port can be switched at any time while delaying the timing to output to the port. The first and second motors 29 and 30 can be switched via the motor control unit 28 by the same operation as that of the first embodiment.

[0039]

As described above, the microcomputer of the present invention outputs the next output value to the port immediately after the designated time of the output value has elapsed when the output values output to the plurality of ports are simultaneously switched. It is possible to control multiple motors by selecting whether to output to the port after a certain delay or output to the port according to the value to be output to the port and switching the delay time at certain intervals. Even when the output waveform is used as the output waveform of the three-phase inverter motor, the phases (P0 output and P3 output, P1 output and P4 output, P2 output and P5 output) that are opposite to each other do not momentarily become "0" at the same time, and penetrate. There is an effect that the current can be prevented from flowing.

Further, according to the present invention, when controlling a plurality of motors, a value corresponding to the delay time when switching the port output is set in accordance with the characteristics of each motor, and for each port output period of each motor. By switching the set delay time, the motor switching can be performed not by interrupt processing but by using the switching signal output by the inversion of the motor designation flag, so that the motor switching can be performed at high speed. is there.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a microcomputer showing an embodiment of the present invention.

FIG. 2 is a timing diagram of port output in FIG.

FIG. 3 is a delay circuit diagram in a microcomputer for explaining another embodiment of the present invention.

FIG. 4 is a timing diagram of port output in FIG.

FIG. 5 is a configuration diagram of a microcomputer showing a conventional example.

FIG. 6 is a timing diagram of port output in FIG.

[Explanation of symbols]

 1 Microcomputer (microcomputer) 2 CPU 3 Port output controller 5 Buffer register 6 Output latch 7 Delay circuit 8 Timer counter 9 Start bit (ST) 10 Compare register 12, 18 Selector 13 Comparator 14 Interrupt controller 15 Delay・ Counter 16 Delay designation register 19 Delay storage register 20 Port output count storage register 21 Output count counter 22 Motor designation flag (F) 23 Register bit part 24 Latch part 25 Flip flop 26 Inverter 27 AND gate P0 to P5 port output

Claims (1)

[Claims] 1. A terminal output value holding means for holding data output to an output terminal for outputting data to the outside, and next data for storing data to be output next to the output terminal. Storage means, at least two storage time storage means for storing the time for storing the value of the next data storage means in the terminal output value holding means, and storing the value of the next data storage means in the terminal output value holding means And a means for storing the value of the next data storage means in the terminal output value holding means when the measured result coincides with the value of the storage time storage means; At least two delay time storage means for storing a delay time from the time when the value is stored in the terminal output value holding means to the time when the value is output to the output terminal, and the value of the next data storage means is output to the terminal. The value of the terminal output value holding means is measured immediately after the delay time from the time of storage in the value holding means to the output to the output terminal is measured and immediately after the value of the next data storage means is stored in the terminal output value holding means. Either output to the output terminal or output the value of the terminal output value storage means to the output terminal when the result of measuring the delay time matches the value of the delay time storage means. Means for selecting and outputting the value stored in the output value storage means, means for measuring the number of times data is output to the output terminal, and means for outputting a switching signal when the measured value reaches a predetermined value, The delay time storage means and the storage time storage means according to the switching signal, and outputs data to the plurality of output terminals in real time. Lee Black computer.