JPH0612135A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0612135A JPH0612135A JP4169777A JP16977792A JPH0612135A JP H0612135 A JPH0612135 A JP H0612135A JP 4169777 A JP4169777 A JP 4169777A JP 16977792 A JP16977792 A JP 16977792A JP H0612135 A JPH0612135 A JP H0612135A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- internal
- supply voltage
- external
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
- Dram (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体集積回路装置に関
し、特に内部降圧電源回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to an internal step-down power supply circuit.
【0002】[0002]
【従来の技術】従来の内部降圧電源回路は、図2に示す
様に、基準電圧VREFと内部電源電圧VINTとを比
較し、外部電源をソースとし、内部電源をドレインと
し、前記比較した結果に応じて変化する電位をゲートと
するPch(チャネル)MOSトランジスタTR1と、
PchMOSトランジスタ21,22と、NchMOS
トランジスタ20,23,24とを備えており、常に内
部電源電圧VINTをフィードバックして基準電圧VR
EFと比較するタイプの回路である。2. Description of the Related Art As shown in FIG. 2, a conventional internal step-down power supply circuit compares a reference voltage VREF with an internal power supply voltage VINT, and uses an external power supply as a source and an internal power supply as a drain. A Pch (channel) MOS transistor TR1 whose gate is a potential that changes in accordance with
PchMOS transistors 21, 22 and NchMOS
It is provided with transistors 20, 23 and 24, and always feeds back the internal power supply voltage VINT to obtain the reference voltage VR.
This is a type of circuit compared to EF.
【0003】図2の下段は外部電源電圧VCCが低下す
ることで起こる内部電源電圧VINTの低下を検知する
回路であり、検知レベルを基準電圧VREFと接地電位
GNDとの間の抵抗R6,R7によって作っている。本
回路は、PchMOSトランジスタTR2,33,34
と、NchMOSトランジスタ30,31,32と、イ
ンバータ35,36と、抵抗R6,R7とを有する。The lower part of FIG. 2 is a circuit for detecting a decrease in the internal power supply voltage VINT caused by a decrease in the external power supply voltage VCC. The detection level is determined by resistors R6 and R7 between the reference voltage VREF and the ground potential GND. Making. This circuit is composed of PchMOS transistors TR2, 33, 34.
, NchMOS transistors 30, 31, 32, inverters 35, 36, and resistors R6, R7.
【0004】節点N4のレベルは、図3の小点線に示す
様なレベルである。図3の節点N4のレベルと実線の内
部電源電圧VINTとを比較し、内部電源電圧VINT
が節点N4のレベルより下がると、内部電源電圧VIN
Tを節点N4のレベルまで回復させる様に、Pチャネル
トランジスタTR2を駆動させる回路である。The level of the node N4 is as shown by the dotted line in FIG. The level of the node N4 in FIG. 3 is compared with the solid line internal power supply voltage VINT, and the internal power supply voltage VINT is compared.
Falls below the level of node N4, internal power supply voltage VIN
This is a circuit for driving the P-channel transistor TR2 so as to restore T to the level of the node N4.
【0005】[0005]
【発明が解決しようとする課題】このような従来の内部
電源降圧回路では、外部電源電圧VCCが内部電源電圧
VINT付近まで低下すると、外部電源線と内部電源線
との間に挿入したトランジスタTR1のVDSが小さく
なって、電流能力が低下してしまうので、この状態で動
作させると内部電源電圧VINTの低下が顕著となる。
その為に、外部電源電圧対策用の回路があるが、内部電
源電圧VINTの低下の検知レベルが一定である為(図
3における内部電源電圧VINTが外部電源電圧VCC
によらず一定の範囲)、その検知レベルを基準電圧VR
EFの近くに設定すると、外部電源電圧VCCが高いと
きに、内部電源が発振するおそれがあり、検知レベルを
基準電圧VREFより大きく下に設定すると、外部電源
電圧VCCが低いときに、内部電源電圧VINTの沈み
の回復が遅れる。前述したような理由で、検知レベルの
設定が難かしく、設定がずれると性能が悪化するという
問題点がある。In such a conventional internal power supply step-down circuit, when the external power supply voltage VCC drops to around the internal power supply voltage VINT, the transistor TR1 inserted between the external power supply line and the internal power supply line is connected. Since VDS becomes small and the current capability is lowered, the internal power supply voltage VINT is significantly lowered when operated in this state.
Therefore, there is a circuit for countermeasures against the external power supply voltage, but the detection level of the decrease of the internal power supply voltage VINT is constant (the internal power supply voltage VINT in FIG. 3 is the external power supply voltage VCC.
(Regardless of the fixed range), the detection level is set to the reference voltage VR.
When it is set near EF, the internal power supply may oscillate when the external power supply voltage VCC is high. When the detection level is set much lower than the reference voltage VREF, when the external power supply voltage VCC is low, the internal power supply voltage is low. VINT subsidence recovery is delayed. For the reasons described above, it is difficult to set the detection level, and if the setting is deviated, there is a problem that the performance deteriorates.
【0006】本発明の目的は、前記問題点を解決し、検
知レベルの設定が容易で、性能が低下しないようにした
半導体集積回路を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit which solves the above-mentioned problems, makes it easy to set the detection level, and prevents the performance from deteriorating.
【0007】[0007]
【課題を解決するための手段】本発明の構成は、内部降
圧電源回路を有する半導体集積回路装置において、外部
より半導体集積回路素子に印加される外部電源電圧が低
下したことによって起こる動作時の内部降圧電源電圧の
低下を検知するレベルを前記外部電源電圧に応じて変化
させる手段を有し、前記変化した検知レベルにて活性化
される内部電源回路を設けたことを特徴とする。According to the structure of the present invention, in a semiconductor integrated circuit device having an internal step-down power supply circuit, an internal power supply voltage applied to a semiconductor integrated circuit element from the outside is reduced during operation. It is characterized in that it has means for changing a level for detecting a drop in the step-down power supply voltage according to the external power supply voltage, and an internal power supply circuit activated at the changed detection level is provided.
【0008】[0008]
【実施例】図1は本発明の一実施例の半導体集積回路装
置を示す回路図である。図1において、本発明の一実施
例は、上段の回路が動作時用の内部電源回路、下段の回
路が外部電源低下時用の内部電源回路を示している。1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention. In FIG. 1, an embodiment of the present invention shows an upper power supply circuit for operating and an lower power supply circuit for lowering external power supply.
【0009】動作時の内部電源回路は、図2の上段の回
路と同様である。外部電源低下時用の内部電源回路は、
図2の下段の回路とは異なる。The internal power supply circuit during operation is the same as the upper circuit in FIG. The internal power supply circuit for external power supply drop,
It is different from the lower circuit in FIG.
【0010】即ち、内部電源電圧VINTは、抵抗R
4,R5の直列体で分圧され、その共通接続点N2をト
ランジスタ31のゲートに接続している。また、外部電
源電圧VCCを抵抗R1,R2の直列体で分圧し、その
共通接続点NOをゲートとするNchMOSトランジス
タTR3を設け、基準電圧VREFは抵抗R3を介して
トランジスタTR3のドレイン・ソースに接続されてい
る。抵抗R3との接続点N1を、トランジスタ32のゲ
ート入力としている。その他の回路部分は、図2と同様
である。That is, the internal power supply voltage VINT is equal to the resistance R
The voltage is divided by the series body of R4 and R5, and the common connection point N2 is connected to the gate of the transistor 31. Further, the external power supply voltage VCC is divided by the series body of the resistors R1 and R2, and the NchMOS transistor TR3 having the common connection point NO as a gate is provided, and the reference voltage VREF is connected to the drain / source of the transistor TR3 via the resistor R3. Has been done. The connection point N1 with the resistor R3 is used as the gate input of the transistor 32. The other circuit parts are the same as those in FIG.
【0011】図3において、接続点N1の電圧が内部電
源電圧VINTの低下検知のしきい値、接続点N2の電
圧が内部電源電圧VINTと接地電圧の間に抵抗R4,
R5によって得られる電圧であり、接続点N1,N2の
電圧とも外部電源電圧VCC依存性を示している。In FIG. 3, the voltage at the connection point N1 is a threshold value for detecting a decrease in the internal power supply voltage VINT, and the voltage at the connection point N2 is a resistor R4 between the internal power supply voltage VINT and the ground voltage.
The voltage is obtained by R5, and the voltages at the connection points N1 and N2 also show the dependency on the external power supply voltage VCC.
【0012】外部電源電圧低下時内部電源は、外部電源
電圧VCCが内部電源電圧VINTと等しくなったと
き、抵抗R1,R2によって発生する接続点N0のレベ
ルによって、NchMOSトランジスタTR3がONす
るように設定し、この時のNchMOSトランジスタT
R3の電流能力と抵抗R3によって発生する接続点N1
のレベルが、内部電源電圧VINTと接地電圧GNDと
の間にある抵抗R4,R5によって発生する接続点N2
のレベルと等しくなるように、抵抗R4,R5の値を設
定する。When the external power supply voltage drops, the internal power supply is set such that when the external power supply voltage VCC becomes equal to the internal power supply voltage VINT, the NchMOS transistor TR3 is turned on by the level of the connection point N0 generated by the resistors R1 and R2. Then, the NchMOS transistor T at this time
Connection point N1 generated by current capability of R3 and resistor R3
Of the connection point N2 generated by the resistors R4 and R5 between the internal power supply voltage VINT and the ground voltage GND.
The values of the resistors R4 and R5 are set so as to be equal to the level of.
【0013】この様に設定すると、外部電源電圧VCC
が高くなると、接続点N0のレベルも一次的に高くな
り、NchMOSトランジスタTR3のゲートレベルが
高くなり、電流能力が大きくなって、接続点N1のレベ
ルは低くなっていく。従って、図3に示すような外部電
源電圧VCC依存性を示す。With this setting, the external power supply voltage VCC
Becomes higher, the level of the connection point N0 also temporarily increases, the gate level of the NchMOS transistor TR3 increases, the current capability increases, and the level of the connection point N1 decreases. Therefore, the external power supply voltage VCC dependency as shown in FIG. 3 is exhibited.
【0014】内部電源電圧VINTが低下すると、一次
的に接続点N2のレベルが低下し、接続点N1のレベル
より低下すると、差動アンプによりロウレベルが出力さ
れ、インバータ35,36によって増幅されて、Pch
MOSトランジスタTR2のゲートレベルの接続点N3
のレベルは接地電圧GNDまで落されると、PchMO
SトランジスタTR2がONし、内部電源電圧VINT
を回復させようとする。When the internal power supply voltage VINT drops, the level of the connection point N2 temporarily drops, and when it drops below the level of the connection point N1, a low level is output by the differential amplifier and amplified by the inverters 35 and 36, Pch
Gate-level connection point N3 of the MOS transistor TR2
When the level of PchMO drops to the ground voltage GND,
The S transistor TR2 is turned on, and the internal power supply voltage VINT
Try to recover.
【0015】通常、内部電源電圧VINTの低下が小さ
ければ、差動アンプの出力はハイレベルであり、インバ
ータによって接続点N3のレベルは外部電源電圧VCC
となっているために、PchMOSトランジスタTR2
はOFFしており、外部電源電圧低下時用内部電源回路
は動いていない。Normally, if the decrease of the internal power supply voltage VINT is small, the output of the differential amplifier is high level, and the level of the connection point N3 is set to the external power supply voltage VCC by the inverter.
PchMOS transistor TR2
Is OFF, and the internal power supply circuit for external power supply voltage drop is not operating.
【0016】外部電源電圧低下時用内部電源回路は、外
部電源電圧VCC=内部電源電圧VINTのとき、内部
電源電圧VINTが少しでも低下すれば作動し、外部電
源電圧VCCが高くなるに従って、内部電源電圧VIN
Tが大きく低下しないと作動しないようになっている。
このことで、外部電源電圧VCCが低下したときのPc
hMOSトランジスタTR1の電流能力不足を、Pch
MOSトランジスタTR2によって補い、外部電源電圧
VCCの高いところでの内部電源電圧VINTの発振を
防いでいる。When the external power supply voltage VCC is equal to the internal power supply voltage VINT, the internal power supply circuit for lowering the external power supply voltage is activated if the internal power supply voltage VINT is lowered even a little, and the internal power supply is increased as the external power supply voltage VCC increases. Voltage VIN
If T does not drop significantly, it will not work.
As a result, Pc when the external power supply voltage VCC drops
If the current capability of the hMOS transistor TR1 is insufficient, Pch
This is compensated by the MOS transistor TR2 to prevent the internal power supply voltage VINT from oscillating when the external power supply voltage VCC is high.
【0017】[0017]
【発明の効果】以上説明したように、本発明は、半導体
集積回路装置の内部電源回路部に、外部電圧低下時に、
外部電源電圧の変化を伴なう内部電源電圧が低下したこ
とを検知するレベルをもち、その検知レベルより内部電
源電圧が低下したときのみ、内部電圧電源を供給する回
路を設置することで、外部電源電圧が低下したときでも
半導体集積回路素子の動作性能低下を防ぐという効果が
ある。As described above, according to the present invention, the internal power supply circuit portion of the semiconductor integrated circuit device is provided with:
By installing a circuit that supplies internal voltage power only when the internal power supply voltage has dropped to a level that detects a drop in the internal power supply voltage and the internal power supply voltage drops below that detection level. Even when the power supply voltage is lowered, there is an effect of preventing deterioration of the operating performance of the semiconductor integrated circuit device.
【図1】本発明の一実施例の半導体集積回路装置を示す
回路図である。FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention.
【図2】従来の内部電源降圧回路を示す回路図である。FIG. 2 is a circuit diagram showing a conventional internal power supply voltage down circuit.
【図3】内部電源及び検知レベルの電圧特性を示す特性
図である。FIG. 3 is a characteristic diagram showing voltage characteristics of an internal power supply and a detection level.
VREF 基準電圧 VCC 外部電源電圧 VINT 内部電源電圧 TR1,TR2 内部電源供給用PchMOSトラン
ジスタ TR3 内部電源電圧低下検知レベル用NchMOS
トランジスタ R1〜R7 抵抗 N0〜N3 接続点VREF Reference voltage VCC External power supply voltage VINT Internal power supply voltage TR1, TR2 PchMOS transistor for internal power supply TR3 NchMOS for internal power supply voltage drop detection level
Transistors R1 to R7 Resistors N0 to N3 Connection points
Claims (2)
路装置において、外部より半導体集積回路素子に印加さ
れる外部電源電圧が低下したことによって起こる動作時
の内部降圧電源電圧の低下を検知するレベルを前記外部
電源電圧に応じて変化させる手段を有し、前記変化した
検知レベルにて活性化される内部電源回路を設けたこと
を特徴とする半導体集積回路装置。1. In a semiconductor integrated circuit device having an internal step-down power supply circuit, a level for detecting a drop in the internal step-down power supply voltage during operation caused by a decrease in the external power supply voltage externally applied to the semiconductor integrated circuit element is set. A semiconductor integrated circuit device comprising: an internal power supply circuit having means for changing the external power supply voltage and activated at the changed detection level.
の差の増減に従って、前記内部電源電圧の低下を検知す
るしきい値を変化させる回路を有する請求項1に記載の
半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, further comprising a circuit that changes a threshold value for detecting a decrease in the internal power supply voltage according to an increase / decrease in a difference between the external power supply voltage and the internal power supply voltage.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4169777A JP2901419B2 (en) | 1992-06-29 | 1992-06-29 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4169777A JP2901419B2 (en) | 1992-06-29 | 1992-06-29 | Semiconductor integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0612135A true JPH0612135A (en) | 1994-01-21 |
JP2901419B2 JP2901419B2 (en) | 1999-06-07 |
Family
ID=15892673
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4169777A Expired - Lifetime JP2901419B2 (en) | 1992-06-29 | 1992-06-29 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2901419B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100494122B1 (en) * | 1998-07-16 | 2005-08-01 | 주식회사 하이닉스반도체 | Internal voltage control circuit |
-
1992
- 1992-06-29 JP JP4169777A patent/JP2901419B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100494122B1 (en) * | 1998-07-16 | 2005-08-01 | 주식회사 하이닉스반도체 | Internal voltage control circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2901419B2 (en) | 1999-06-07 |
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