JPH0612135A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a semiconductor integrated circuit element from deteriorating in operation performance even if the voltage of an external power source drops by supplying the electric power from an internal voltage power source only when the internal source voltage of an internal power source drops below the level where the drop of the internal source voltage is detected. CONSTITUTION:If the external source voltage VCC drops to become equal to an internal voltage VINT, a transistor(TR) 3 turns ON. At this time, the values of resistors R4 and R5 are so set that the level at a connection point N1 equals to the level at a connection point N2. Therefore, an internal power circuit for external source voltage dropping time operates if the internal source voltage VINT drops even slightly on condition that the external source voltage VCC equals the internal source voltage VINT, but does not operates unless the internal voltage VINT drops greatly as the external voltage rises. Consequently, a deficiency of the current capacity of a TR 1 when the external voltage VCC drops is compensated by a TR 2 to prevent the internal source voltage VINT from oscillating where the external source voltage VCC is high.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to an internal step-down power supply circuit.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional internal step-down power supply circuit compares a reference voltage VREF with an internal power supply voltage VINT, and uses an external power supply as a source and an internal power supply as a drain. A Pch (channel) MOS transistor TR1 whose gate is a potential that changes in accordance with
PchMOS transistors 21, 22 and NchMOS
It is provided with transistors 20, 23 and 24, and always feeds back the internal power supply voltage VINT to obtain the reference voltage VR.
This is a type of circuit compared to EF.

The lower part of FIG. 2 is a circuit for detecting a decrease in the internal power supply voltage VINT caused by a decrease in the external power supply voltage VCC. The detection level is determined by resistors R6 and R7 between the reference voltage VREF and the ground potential GND. Making. This circuit is composed of PchMOS transistors TR2, 33, 34.
, NchMOS transistors 30, 31, 32, inverters 35, 36, and resistors R6, R7.

The level of the node N4 is as shown by the dotted line in FIG. The level of the node N4 in FIG. 3 is compared with the solid line internal power supply voltage VINT, and the internal power supply voltage VINT is compared.
Falls below the level of node N4, internal power supply voltage VIN
This is a circuit for driving the P-channel transistor TR2 so as to restore T to the level of the node N4.

[0005]

In such a conventional internal power supply step-down circuit, when the external power supply voltage VCC drops to around the internal power supply voltage VINT, the transistor TR1 inserted between the external power supply line and the internal power supply line is connected. Since VDS becomes small and the current capability is lowered, the internal power supply voltage VINT is significantly lowered when operated in this state.
Therefore, there is a circuit for countermeasures against the external power supply voltage, but the detection level of the decrease of the internal power supply voltage VINT is constant (the internal power supply voltage VINT in FIG. 3 is the external power supply voltage VCC.
(Regardless of the fixed range), the detection level is set to the reference voltage VR.
When it is set near EF, the internal power supply may oscillate when the external power supply voltage VCC is high. When the detection level is set much lower than the reference voltage VREF, when the external power supply voltage VCC is low, the internal power supply voltage is low. VINT subsidence recovery is delayed. For the reasons described above, it is difficult to set the detection level, and if the setting is deviated, there is a problem that the performance deteriorates.

An object of the present invention is to provide a semiconductor integrated circuit which solves the above-mentioned problems, makes it easy to set the detection level, and prevents the performance from deteriorating.

[0007]

According to the structure of the present invention, in a semiconductor integrated circuit device having an internal step-down power supply circuit, an internal power supply voltage applied to a semiconductor integrated circuit element from the outside is reduced during operation. It is characterized in that it has means for changing a level for detecting a drop in the step-down power supply voltage according to the external power supply voltage, and an internal power supply circuit activated at the changed detection level is provided.

[0008]

1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention. In FIG. 1, an embodiment of the present invention shows an upper power supply circuit for operating and an lower power supply circuit for lowering external power supply.

The internal power supply circuit during operation is the same as the upper circuit in FIG. The internal power supply circuit for external power supply drop,
It is different from the lower circuit in FIG.

That is, the internal power supply voltage VINT is equal to the resistance R
The voltage is divided by the series body of R4 and R5, and the common connection point N2 is connected to the gate of the transistor 31. Further, the external power supply voltage VCC is divided by the series body of the resistors R1 and R2, and the NchMOS transistor TR3 having the common connection point NO as a gate is provided, and the reference voltage VREF is connected to the drain / source of the transistor TR3 via the resistor R3. Has been done. The connection point N1 with the resistor R3 is used as the gate input of the transistor 32. The other circuit parts are the same as those in FIG.

In FIG. 3, the voltage at the connection point N1 is a threshold value for detecting a decrease in the internal power supply voltage VINT, and the voltage at the connection point N2 is a resistor R4 between the internal power supply voltage VINT and the ground voltage.
The voltage is obtained by R5, and the voltages at the connection points N1 and N2 also show the dependency on the external power supply voltage VCC.

When the external power supply voltage drops, the internal power supply is set such that when the external power supply voltage VCC becomes equal to the internal power supply voltage VINT, the NchMOS transistor TR3 is turned on by the level of the connection point N0 generated by the resistors R1 and R2. Then, the NchMOS transistor T at this time
Connection point N1 generated by current capability of R3 and resistor R3
Of the connection point N2 generated by the resistors R4 and R5 between the internal power supply voltage VINT and the ground voltage GND.
The values of the resistors R4 and R5 are set so as to be equal to the level of.

With this setting, the external power supply voltage VCC
Becomes higher, the level of the connection point N0 also temporarily increases, the gate level of the NchMOS transistor TR3 increases, the current capability increases, and the level of the connection point N1 decreases. Therefore, the external power supply voltage VCC dependency as shown in FIG. 3 is exhibited.

When the internal power supply voltage VINT drops, the level of the connection point N2 temporarily drops, and when it drops below the level of the connection point N1, a low level is output by the differential amplifier and amplified by the inverters 35 and 36, Pch
Gate-level connection point N3 of the MOS transistor TR2
When the level of PchMO drops to the ground voltage GND,
The S transistor TR2 is turned on, and the internal power supply voltage VINT
Try to recover.

Normally, if the decrease of the internal power supply voltage VINT is small, the output of the differential amplifier is high level, and the level of the connection point N3 is set to the external power supply voltage VCC by the inverter.
PchMOS transistor TR2
Is OFF, and the internal power supply circuit for external power supply voltage drop is not operating.

When the external power supply voltage VCC is equal to the internal power supply voltage VINT, the internal power supply circuit for lowering the external power supply voltage is activated if the internal power supply voltage VINT is lowered even a little, and the internal power supply is increased as the external power supply voltage VCC increases. Voltage VIN
If T does not drop significantly, it will not work.
As a result, Pc when the external power supply voltage VCC drops
If the current capability of the hMOS transistor TR1 is insufficient, Pch
This is compensated by the MOS transistor TR2 to prevent the internal power supply voltage VINT from oscillating when the external power supply voltage VCC is high.

[0017]

As described above, according to the present invention, the internal power supply circuit portion of the semiconductor integrated circuit device is provided with:
By installing a circuit that supplies internal voltage power only when the internal power supply voltage has dropped to a level that detects a drop in the internal power supply voltage and the internal power supply voltage drops below that detection level. Even when the power supply voltage is lowered, there is an effect of preventing deterioration of the operating performance of the semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional internal power supply voltage down circuit.

FIG. 3 is a characteristic diagram showing voltage characteristics of an internal power supply and a detection level.

[Explanation of symbols]

VREF Reference voltage VCC External power supply voltage VINT Internal power supply voltage TR1, TR2 PchMOS transistor for internal power supply TR3 NchMOS for internal power supply voltage drop detection level
Transistors R1 to R7 Resistors N0 to N3 Connection points

Claims (2)

[Claims] 1. In a semiconductor integrated circuit device having an internal step-down power supply circuit, a level for detecting a drop in the internal step-down power supply voltage during operation caused by a decrease in the external power supply voltage externally applied to the semiconductor integrated circuit element is set. A semiconductor integrated circuit device comprising: an internal power supply circuit having means for changing the external power supply voltage and activated at the changed detection level. 2. The semiconductor integrated circuit device according to claim 1, further comprising a circuit that changes a threshold value for detecting a decrease in the internal power supply voltage according to an increase / decrease in a difference between the external power supply voltage and the internal power supply voltage.