JPH06120927A - Stuff multiplex converter - Google Patents

Abstract

PURPOSE:To provide the stuff multiplex converter not needing the adjustment with high reliability in which a warning signal given to a low-order group equipment is generated on the occurrence of a fault of a high-order group. CONSTITUTION:A write clock generated by a transmission use low-order group clock generating circuit 21 to be given to a transmission buffer memory 20 is given directly or via a reception use low-order group clock generating circuit 5A to a warning signal generating circuit 8. When a fault of a high-order group is detected by a monitor circuit 7, the warning signal generating circuit 8 generates a warning signal satisfying the frequency standard of the low-order group signal based on the given block. Thus, the clock signal used for generating the warning signal is obtained without the use of a variable resistor and a mechanical switch to eliminate the need for the adjustment and to enhance the reliability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stuff multiplex converter for converting between a low-order group signal and a high-order group signal, and more particularly to a configuration for generating a warning signal to be output to the low-order group device side when an abnormality occurs in a higher order group. It is a thing.

[0002]

2. Description of the Related Art As a multiplex converter for converting between a low-order group signal (for example, 6.312 Mb / s) and a high-order group signal (for example, 32.064 Mb / s), there is a stuff multiplex converter that employs a stuff synchronization method. .

FIG. 2 shows a conventional reception configuration of a stuff multiplex conversion device. In FIG. 2, the high-order group signal is demultiplexed by the demultiplexing circuit 1 to be converted into a low-order group signal containing a stuff pulse, and then supplied to the reception buffer memory 2. Further, the higher-order group signal is supplied to the reception timing circuit 3 to extract a clock signal, and the extracted clock signal is passed through the destuffing control circuit 4 to remove the clock component at the timing when the stuff pulse is applied to the buffer memory 2. It is supplied to the buffer memory 2 as a write clock. By such write control, the low-order group signal from which the stuff pulse has been removed is written in the buffer memory 2. The low-order group signal written in the buffer memory 2 is read by the low-order group clock (read clock) having the low-order group frequency generated by the receiving low-order group clock generation circuit 5 and is read via the switch 6. Is output.

Here, the read clock (low-order group clock) requires that its average frequency is equal to the average frequency of the write clock so that the read does not overtake the write. However, since the stuff pulse is removed from the buffer memory 2 and written to it, and it is continuously read, the write clock and the read clock (low-order group clock) for the buffer memory 2 have different instantaneous frequencies. Has become.

Therefore, the low-order group clock generation circuit 5 is
As shown in FIG. 3, it is realized by a PLL circuit configuration that receives a write clock as an input and forms a low-order group clock (read clock) so as to follow it.

In FIG. 3, the write clock output from the destuffing control circuit 4 is frequency-divided via the frequency dividing circuit 10 and applied to the phase comparator 11. In the phase comparator 11, the frequency division ratio of the low-order group clock at that time is also divided.
It is given via the frequency dividing circuit 12 equal to 0. Thus, the phase comparator 11 obtains the phase difference information between the write clock and the low-order group clock, which is converted into a direct current through the low-pass filter 13 and further supplied to the voltage controlled oscillator 15 through the switch 14. The center oscillation frequency of the voltage controlled oscillator 15 is selected to be the predetermined frequency of the low-order group clock, and the oscillation frequency is changed in the vicinity of this predetermined frequency according to the DC voltage at that time, and the oscillation signal is changed to the low-order group clock. Is output to the buffer memory 2 described above. The low-order group clock is frequency-divided via the frequency dividing circuit 12 and fed back to the phase comparator 11 as described above.

The write clock and the low-order group clock are not directly phase-compared with each other, but the frequency is divided and the phase comparison is performed. The phase comparison using a low-speed signal is more accurate in detecting the phase difference. This is because.

In the stuff multiplex converter, the high-order group signal is converted into the low-order group signal by the above-described receiving structure and output to the low-order group device (not shown). However, when a failure occurs in the upper group device (including not only the immediately preceding higher order group but also higher order groups) and its transmission path, the higher order group signal cannot be naturally converted to the lower order group signal, At this time, for example, all 1s satisfying the frequency standard of the low-order group signal
The warning signal (hereinafter referred to as the AIS signal) is converted into the low order group signal and is output to the low order group device.

The structure and operation will be described below. In FIG. 2, the high-order group abnormality monitoring circuit 7 monitors the high-order group signal, and the high-order group signal is disconnected or out of synchronization or AI is detected.
When the S signal is received, a significant abnormality occurrence signal is given to the switch 6, the AIS signal generation circuit 8 and the switch 14 (FIG. 3) in the low-order group clock generation circuit 5. At this time, in the low-order group clock generation circuit 5 (see FIG. 3),
The DC voltage set in the volume 16 is applied to the voltage-controlled oscillator 15 by switching the switch 14,
A low-order group clock corresponding to this DC voltage is output to the AIS signal generation circuit 8. The AIS signal generation circuit 8 generates an AIS signal satisfying the frequency standard of the low-order group signal by the clock from the low-order group clock generation circuit 5, and this AIS signal is generated.
The signal is a buffer memory 2 due to a significant abnormality occurrence signal.
Is output to the low-order group device via the switch 6 that is switched to the AIS signal generation circuit 8 side.

[0010]

However, in the conventional stuff multiplex converter, the volume 16 is set in the low order group clock generation circuit 5 in order to generate the AIS signal which satisfies the frequency standard of the low order group signal. The direct current voltage is applied to the voltage controlled oscillator 15. Here, if the setting voltage of the volume 16 is not appropriate, it is not possible to generate an AIS signal that satisfies the frequency standard of the low-order group signal. Therefore, this is called volume adjustment when shipping or assembling the stuff multiplex converter. It required complicated work.

Further, the switch 14 in the preceding stage of the voltage controlled oscillator 15 is constituted by a mechanical switch such as a relay so that the voltage controlled oscillator 15 is not adversely affected by the bias voltage of the switch 14 or the like, The reliability was low.

The present invention has been made in consideration of the above points, and is highly reliable in the configuration of generating a warning signal.
It is intended to provide a staff multiplex converter that does not require adjustment work.

[0013]

In order to solve such a problem, the present invention provides a warning signal generating circuit (called an AIS signal generating circuit in the embodiment) when an abnormality occurs in a higher level group. Formed based on the clock
In a stuff multiplex conversion device for outputting a warning signal satisfying the frequency standard of a low-order group signal to a low-order group device, based on a clock formed by a transmission low-order group clock generation circuit for giving to a transmission buffer memory, A warning signal generating circuit generates a warning signal.

[0014]

According to the present invention, the write clock formed by the transmitting low-order group clock generating circuit for giving to the transmitting buffer memory is directly applied to the warning signal generating circuit, or the receiving low-order group clock generating circuit is generated. By giving the clock through the circuit, the clock used for generating the warning signal can be obtained without using the volume or mechanical switch, the adjustment work is unnecessary, and the reliability is improved.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the stuff multiplex converter according to the present invention will be described in detail below with reference to the drawings. FIG. 1 shows the configuration of the main part of the stuff multiplex conversion device of this embodiment, and the same or corresponding parts as in FIG. 2 are designated by the same reference numerals.

In FIG. 1, the stuff multiplex conversion device is
The transmission configuration also includes the buffer memory 20, and after writing the low-order group signal to be transmitted given from the low-order group device to the buffer memory 20, by controlling the read operation, the low-order signal in which the stuff pulse is inserted is inserted. It is designed to obtain a group signal. The write clock (transmission low-order group clock) for the transmission buffer memory 20 is formed by the transmission low-order group clock generation circuit 21 based on the transmission low-order group signal. It should be noted that further description of the transmission configuration will be omitted.

In the case of this embodiment, the low order group clock for transmission formed by the low order group clock generation circuit 21 for transmission is also applied to the low order group clock generation circuit 5A for reception.

FIG. 4 shows a detailed configuration of the receiving low-order group clock generating circuit 5A of this embodiment, and FIG. 3 showing the configuration of the conventional receiving low-order group clock generating circuit 5. The same or corresponding parts are designated by the same reference numerals.

In FIG. 4, the receiving low-order group clock generating circuit 5A of this embodiment is different from the conventional receiving low-order group clock generating circuit 5 in that the switch 14 and the volume 1 are different from each other.
6 is omitted, the output from the low-pass filter 13 is always input to the voltage controlled oscillator 15, and the two-input selector circuit 17 is provided in the preceding stage of the frequency dividing circuit 10. There is.

The selector circuit 17 receives the write clock for reception from the destuffing control circuit 4 and the above-mentioned low-order group clock for transmission generated by the low-order group clock generator for transmission 21. An abnormality occurrence signal is input from the upper group abnormality monitoring circuit 7 as a selection control signal. The selector circuit 17 selects the low-order group clock for transmission when the abnormality occurrence signal is significant, and selects the PLL circuit portion (10
13 to 15), the write clock for reception is selected and output to the PLL circuit portion when the abnormality occurrence signal is insignificant.

The receiving low-order group clock generated by the receiving low-order group clock generating circuit 5A described above is also applied to the receiving buffer memory 2 and the AIS signal generating circuit 8 as in the conventional case.

Except for the points described above, the configuration of each part in the stuff multiplex converter of this embodiment is the same as that of the conventional stuff multiplex converter.

In the above configuration, if an abnormality occurs in the upper group device or the transmission path of the upper group signal during the reception processing of the higher order group signal, the upper group abnormality monitoring circuit 7 detects the abnormality and detects the abnormality occurrence signal. To the selector circuit 17 of the receiving low-order group clock generation circuit 5A and the switch 6.

As a result, in the receiving low-order group clock generation circuit 5A, the selector circuit 17 selects the transmitting low-order group clock generated by the transmitting low-order group clock generating circuit 21, and the transmitting low-order group clock is generated. A clock that is phase-synchronized with the clock is supplied to the AIS signal generation circuit 8.
Thus, the AIS signal generation circuit 8 generates an AIS signal (for example, all 1) that satisfies the frequency standard of the low order group signal by this clock from the low order group clock generation circuit 5A. This AIS signal is transmitted to the low-order group device (not shown) via the switch 6 which is switched from the buffer memory 2 to the AIS signal generation circuit 8 side by a significant abnormality occurrence signal.
Is output to.

Therefore, according to the above embodiment, since there is no volume in the clock generation structure for generating the AIS signal satisfying the frequency standard of the low order group signal, the clock frequency is set at the time of shipping or assembling the stuff multiplex converter. It is possible to eliminate the work of adjusting.

Further, according to the above-described embodiment, it is possible to realize a clock generating structure for generating an AIS signal satisfying the frequency standard of the low-order group signal without using a mechanical switch, and it is possible to improve reliability. .

Further, according to the above-described embodiment, the clock which is phase-synchronized by the PLL circuit configuration with respect to the transmitting low-order group clock is supplied to the AIS signal generating circuit 8, so that the output to the low-order group device is outputted. Even if the received low-order group signal is switched to the AIS signal, the phase change can be made small. Incidentally, in the conventional case, when the switch 14 is switched to the volume 16 side, the DC voltage applied to the voltage-controlled oscillator 15 may change abruptly, and as a result, the phase of the AIS signal is lower than the previous low-order group signal. There is also a possibility that the low-order group device may be delayed in receiving the AIS signal due to a sudden shift from the phase of the above.

In the above embodiment, the selector circuit 17 is set to P in the receiving low-order group clock generation circuit 5A.
Although the one provided at the input stage of the LL circuit configuration is shown, this selector circuit 17 is provided at the output stage of the PLL circuit configuration, that is,
It may be provided in the next stage of the voltage controlled oscillator 15 and in front of the branch point of the feedback loop, and the same effect as the above embodiment can be obtained. Further, the transmission low-order group clock from the transmission low-order group clock generation circuit 21 may be directly applied to the AIS signal generation circuit 8 without passing through the reception low-order group clock generation circuit 5A.

Furthermore, the present invention can be applied to the stuff multiplex conversion device of any multiplexing stage.

[0030]

As described above, according to the present invention, when an abnormality occurs in the higher order group, the warning signal generating circuit satisfies the frequency standard of the low order group signal formed based on the given clock. In a stuff multiplex converter that outputs a warning signal to a low-order group device, a warning signal generation circuit generates a warning signal based on a clock formed by a transmission low-order group clock generation circuit for giving to a transmission buffer memory. Since this is done, it is possible to realize a highly reliable stuff multiplex conversion device that does not require adjustment work at the time of shipment.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of an embodiment.

FIG. 2 is a block diagram showing a conventional reception configuration.

FIG. 3 is a block diagram showing a configuration of a conventional low-order group clock generation circuit for reception.

FIG. 4 is a block diagram showing a configuration of a receiving low-order group clock generation circuit of the embodiment.

[Explanation of symbols]

5A ... Low-order group clock generation circuit for reception, 6 ... Changeover switch between reception low-order group signal and AIS signal (warning signal),
7 ... Upper group abnormality monitoring circuit, 8 ... AIS signal generating circuit, 1
7 ... Selector circuit, 20 ... Transmission buffer memory, 21
... Low-order group clock generation circuit for transmission.

Claims (1)

[Claims] 1. A warning signal generating circuit is formed based on a given clock when an abnormality occurs in the upper group,
In a stuff multiplex conversion device that outputs a warning signal that satisfies the frequency standard of the low-order group signal to the low-order group device, based on the write clock formed by the transmission low-order group clock generation circuit to give to the transmission buffer memory, A stuff multiplex converter in which the warning signal generating circuit generates a warning signal.