JPH06120409A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH06120409A
JPH06120409A JP4931992A JP4931992A JPH06120409A JP H06120409 A JPH06120409 A JP H06120409A JP 4931992 A JP4931992 A JP 4931992A JP 4931992 A JP4931992 A JP 4931992A JP H06120409 A JPH06120409 A JP H06120409A
Authority
JP
Japan
Prior art keywords
lead
adhesive sheet
sheet
adhesive
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4931992A
Other languages
Japanese (ja)
Inventor
Yoshimi Matsunaga
義見 松永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Semiconductor Package and Test Solutions Co Ltd
Original Assignee
Hitachi Hokkai Semiconductor Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Hokkai Semiconductor Ltd, Hitachi Ltd filed Critical Hitachi Hokkai Semiconductor Ltd
Priority to JP4931992A priority Critical patent/JPH06120409A/en
Publication of JPH06120409A publication Critical patent/JPH06120409A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent a fault of lead plating and to reduce a fault of connection to an external device by a method wherein plated surfaces of a plurality of outer leads are protected by an adhesive sheet. CONSTITUTION:After wire bonding is completed, a lead frame 1 is conveyed to a molding process and a chip 4, bonding wires 5, inner leads 6, etc., are sealed in a package 9 formed of thermosetting resin. Subsequently the lead frame 1 is conveyed to an adhesive sheet sticking process. Herein surfaces of outer leads 8 of the lead frame 1 are plated with solder beforehand. Then, the outer leads in a plurality projecting from one side of the package 9 are connected as one unit by sticking thereon an adhesive sheet 10 coated with an adhesive which is set to lose adhesion by application of ultraviolet rays. In this way, the plated surfaces of the leads are protected.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関するもので、特にアウタ−リ−ドに半田メッキ等傷
つき易いメッキを施した半導体装置(以下、ICとい
う)やアウタ−リ−ドが屈曲しやすいICに適用して有
効な技術に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a semiconductor device (hereinafter referred to as an IC) or an outer lead in which an outer lead is plated with a fragile material such as solder plating. The present invention relates to a technique effective when applied to an IC that is easily bent.

【0002】[0002]

【従来の技術】ICは基板に実装され家電品や各種の外
部装置に組み込まれて使用されるが、ICのアウタ−リ
−ドをメッキ処理していないと、アウタ−リ−ドの表
面が酸化して、外部装置にICを実装する際に使用する
接続用の半田をアウタ−リ−ド材表面の酸化膜が弾き、
ICを基板にうまく取り付けられないアウタ−リ−ド
が腐食しやすくなる等の問題が発生する。
2. Description of the Related Art An IC is mounted on a board and incorporated in home electric appliances and various external devices for use. However, if the outer lead of the IC is not plated, the surface of the outer lead will be The oxide film on the surface of the outer lead material oxidizes and repels solder for connection used when mounting the IC on an external device,
There is a problem that the outer lead, which cannot properly mount the IC on the substrate, is easily corroded.

【0003】そのため、アウタ−リ−ドの表面に予めメ
ッキを形成する事が行なわれるが、その方法として、リ
−ドフレ−ムを成型したさいにメッキする方法と、完成
したICにメッキする方法がある。しかしながら、最近
リ−ド形状が複雑なICやリ−ド間隔が狭いICに対応
するため、リ−ドフレ−ム状態にてメッキの厚さを容易
に制御できる電気メッキにより、アウタ−リ−ドの表面
にメッキを形成する方法が増加してきている。
For this reason, the outer lead surface is preliminarily plated, and as a method therefor, a method of plating when forming a lead frame and a method of plating a completed IC. There is. However, in order to deal with ICs with complicated lead shapes and ICs with a narrow lead interval recently, the outer lead is provided by electroplating in which the plating thickness can be easily controlled in the lead frame state. There is an increasing number of methods of forming plating on the surface of.

【0004】なお、リ−ドフレ−ムの製造工程について
は、「電子材料取引の手引」ゲマテック社編 1987
年4月18日発行 p.199に記載されている。
Regarding the manufacturing process of the lead frame, "Guide for Electronic Materials Trading", edited by Gematech Co., 1987.
Published April 18, 2012 p. 199.

【0005】[0005]

【発明が解決しようとする課題】ところが、上記メッキ
を施したアウタ−リ−ドがICの製造途中において、外
的要因により汚れや傷が生じると、外部基板にICを半
田付けする際、アウタ−リ−ドの表面に良好に半田がの
らずに接続不良が発生したり、またアウタ−リ−ドのメ
ッキが剥がれた部分から腐食してしまうという問題が発
生することになりかねない。
However, when the plated outer lead is contaminated or scratched by an external factor during the manufacture of the IC, the outer lead is soldered to the external substrate when the IC is soldered. There is a possibility that solder may not be properly deposited on the surface of the lead and a connection failure may occur, or that the plating of the outer lead may be corroded from the peeled portion.

【0006】また、ICを搬送中、アウタ−リ−ドが屈
曲すると、アウタ−リ−ドの修正が必要となる、自
動的にテステイングができない、外部装置に確実に接
続できないなどの不具合が生じる問題がある。
If the outer lead is bent during the transportation of the IC, the outer lead needs to be corrected, the automatic testing cannot be performed, and the external device cannot be surely connected. There's a problem.

【0007】従って、本発明の目的は、リ−ドメッキ不
良を防止し、外部装置への接続不良を低減する半導体装
置の製造方法を提供するものである。
Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device which prevents lead plating defects and reduces connection defects to external devices.

【0008】本発明の他の目的は、半導体装置の製造過
程において、搬送中におけるリ−ド曲がりを防止する技
術を提供するものである。
Another object of the present invention is to provide a technique for preventing lead bending during transportation in the manufacturing process of a semiconductor device.

【0009】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0010】[0010]

【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を簡単に説明すれば、下
記のとおりである。
The outline of the representative ones of the inventions disclosed in the present application will be briefly described as follows.

【0011】すなわち、メッキが施され、少なくとも外
部装置と接続するに必要とする部分のメッキを接着シ−
トで保護し、かつ複数のアウタ−リ−ド間を連結して貼
付るものである。
That is, the plating is applied, and at least a portion of the plating necessary for connecting to an external device is bonded to the adhesive sheet.
The outer cover and the outer lead are connected to each other and attached.

【0012】[0012]

【作用】上記の手段により、外的衝撃によりアウタ−リ
−ドへストレスが生じてもアウタ−リ−ド間が接着テ−
プで補強されているので、屈曲するのを防止できるもの
である。
By the above means, even if stress is applied to the outer lead due to external impact, the adhesive tape is attached between the outer lead and the outer lead.
Since it is reinforced with a push-pull, it can be prevented from bending.

【0013】また、シ−トでアウタ−リ−ド表面を覆う
ことにより、アウタ−リ−ドの表面が外部と接触してメ
ッキ剥がれが生じるのを防止しでき、さらにはメッキ剥
がれ等によるメッキ不良で外部装置への半田付け不良が
発生するのを防止するものである。
By covering the surface of the outer lead with a sheet, it is possible to prevent the surface of the outer lead from coming into contact with the outside and peeling off the plating. Furthermore, the plating due to the peeling off of the plating can be prevented. It is intended to prevent defective soldering to an external device from occurring.

【0014】[0014]

【実施例】図1は本発明の一実施例であるICの製造方
法の概略プロセスフロ−、図2は図1の製造方法により
製造されたリ−ドフレ−ムの製造説明図である。図示す
るように、リ−ドフレ−ム1の略中央部に位置しタブリ
−ド2にて支持された複数のタブ3上にチップ4を搭載
する工程、いわゆるチップボンディング工程のち、チッ
プ4を搭載したリ−ドフレ−ムを、一枚ずつ順次ワイヤ
ボンディング工程Aに移動させる。ここで、ボンディン
グワイヤ5により上記チップ4の上面に形成された電極
からインナ−リ−ド6の先端とが結線され電気的に結合
されることになる。これより先は、リ−ドを便宜上タイ
バ−7の内側と外側でそれぞれインナ−リ−ド6とアウ
タ−リ−ド8に区別して説明する。ワイヤボンディング
完了後、モ−ルディング工程Bにリ−ドフレ−ム1を搬
送し、チップ4、ボンディングワイヤ5及びインナ−リ
−ド6等を熱硬化性の樹脂にて形成されたパッケ−ジ9
内に封止する。続いてリ−ドフレ−ム1を接着シ−ト貼
付工程Cに搬送する。以下、接着シ−ト貼付工程Cから
切断・折曲工程Dについて図により詳細に説明する。本
図において、リ−ドフレ−ム1は、既にそのアウタ−リ
−ド8の表面に半田メッキが施された状態であるとす
る。10は紫外線の照射により硬化して粘性が低下する
接着剤10aが塗布された接着シ−トであり、パッケ−
ジ9の一側面から突出する複数本のアウタ−リ−ドを一
単位として連結して貼付られている。このとき、本実施
例では、接着シ−ト10を外部と接触して傷が生じやす
い全部分、すなわち図5で示すように、アウタ−リ−ド
8を屈曲させたときに外側となる面の全体に貼り付けら
れている(尚、リ−ド表面及び裏面の両面に接着シ−ト
を貼付ても良い。また、外部装置に接続するために必要
な最小限のメッキ部分、例えばアウタ−リ−ドの先端部
分のみに接着シ−トを貼付ても、後述する効果が得られ
る)。このように、接着シ−トを貼ることにより、アウ
タ−リ−ド表面のメッキ部分を外部から保護できると共
に、アウタ−リ−ド間を連結して補強強化しているの
で、リ−ド曲がりも防止することを可能にしている。次
に、切断・折曲工程Dへとリ−ドフレ−ム1を搬送し、
上記リ−ドフレ−ム1を構成しているリ−ドフレ−ム横
枠11,11からタブリ−ド2を、またタイバ−7及び
リ−ドフレ−ム縦枠12,12からアウタ−リ−ド8,8
を切断して分離することにより、複数個のIC13得る
ことができる。尚、この接着シ−トを貼った状態で出
荷、あるいは搬送すると、アウタ−リ−ド8の屈曲を確
実に防止することができる。次ぎに、ここに分離された
IC13を必要によりテスト工程Eを経たのち、UV照
射工程FにIC13を搬送する。ここで、接着シ−ト1
0にUV(紫外線)を照射することにより、接着剤10
aを硬化させる。これにより、接着剤10aは粘性を失
うことになり、次工程の接着シ−ト除去工程GにてIC
13から、簡単に接着シ−ト10を剥がすことが可能と
なる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic process flow of a method of manufacturing an IC which is an embodiment of the present invention, and FIG. 2 is a manufacturing explanatory view of a lead frame manufactured by the manufacturing method of FIG. As shown in the figure, the chip 4 is mounted after a process of mounting the chips 4 on a plurality of tabs 3 which are located at the substantially central portion of the lead frame 1 and supported by the tab lead 2, that is, a so-called chip bonding process. The prepared lead frames are sequentially moved to the wire bonding step A one by one. Here, the bonding wire 5 connects the electrode formed on the upper surface of the chip 4 and the tip of the inner lead 6 to be electrically connected. For the sake of convenience, the leads will be described by distinguishing them between the inner lead 6 and the outer lead 8 inside and outside the tie bar 7 for convenience. After the wire bonding is completed, the lead frame 1 is conveyed to the molding step B, and the chip 4, the bonding wire 5, the inner lead 6 and the like are packaged 9 made of a thermosetting resin.
Seal inside. Subsequently, the lead frame 1 is conveyed to the adhesive sheet attaching step C. Hereinafter, the adhesive sheet attaching step C to the cutting / bending step D will be described in detail with reference to the drawings. In this figure, it is assumed that the lead frame 1 is in a state in which the surface of the outer lead 8 is already solder-plated. Reference numeral 10 is an adhesive sheet coated with an adhesive 10a which is hardened by irradiation of ultraviolet rays and whose viscosity is reduced.
A plurality of outer leads projecting from one side surface of the die 9 are connected and attached as one unit. At this time, in this embodiment, the entire portion where the adhesive sheet 10 is likely to come into contact with the outside to be scratched, that is, the outer surface when the outer lead 8 is bent as shown in FIG. The adhesive sheet may be attached to both the front surface and the back surface of the lead. In addition, the minimum plated portion necessary for connecting to an external device, for example, the outer layer. Even if the adhesive sheet is attached only to the tip portion of the lead, the effects described later can be obtained). In this way, by sticking the adhesive sheet, the plated portion on the surface of the outer lead can be protected from the outside, and the outer lead is connected to strengthen and strengthen the lead. It is also possible to prevent. Next, the lead frame 1 is conveyed to the cutting / bending process D,
The lead frame lateral frames 11 and 11 forming the lead frame 1 are connected to the tab lead 2 and the tie bar 7 and the lead frame vertical frames 12 and 12 are formed to the outer lead. 8,8
A plurality of ICs 13 can be obtained by cutting and separating. If the outer sheet 8 is shipped or transported with the adhesive sheet attached, the outer lead 8 can be surely prevented from bending. Next, the separated IC 13 is subjected to a test process E if necessary, and then the IC 13 is transported to a UV irradiation process F. Here, the adhesive sheet 1
0 by irradiating UV (ultraviolet ray), the adhesive 10
Cure a. As a result, the adhesive 10a loses its viscosity, and the IC is removed in the next adhesive sheet removing step G.
It is possible to easily peel off the adhesive sheet 10 from 13.

【0015】ところで、図7に示すように、例えば異な
るIC14、15の対接するアウタ−リ−ド16、17
に共通して接着シ−ト18を貼付ても良い。
By the way, as shown in FIG. 7, for example, outer leads 16 and 17 in which different ICs 14 and 15 are in contact with each other.
The adhesive sheet 18 may be attached in common to the above.

【0016】次ぎに、本実施例で得られる作用・効果に
ついて説明する。
Next, the operation and effect obtained in this embodiment will be described.

【0017】(1)メッキしたリ−ド表面を、接着シ−
トで保護することにより、外部からの衝撃が直接リ−ド
表面のメッキに加わるのを防止することができる。その
ため、メッキ表面の剥がれ、キズが生じるのを防止でき
るという効果が得られる。
(1) The plated lead surface is attached with an adhesive seal.
It is possible to prevent external impacts from being directly applied to the plating on the lead surface by protecting the lead surface. Therefore, the effect of preventing peeling of the plating surface and generation of scratches can be obtained.

【0018】(2)上記のように、メッキ剥がれを防止
することができるので、外部装置への半田付けが確実に
行なうことができるという効果が得られる。
(2) As described above, it is possible to prevent the plating from peeling off, so that it is possible to obtain an effect that soldering to an external device can be reliably performed.

【0019】(3)複数のリ−ド間表面を接着シ−トで
連結することにより、接着シ−トでリ−ドが補強される
ので、リ−ド曲がりを防止できるという効果が得られ
る。
(3) By connecting the surfaces of a plurality of leads with an adhesive sheet, the leads are reinforced by the adhesive sheet, so that an effect of preventing the lead bending can be obtained. .

【0020】(4)メッキされ、かつ外部装置と接続す
るために必要な部分、すなわちアウタ−リ−ドの先端部
のみに接着シ−トを形成することにより、接着シ−トの
材料コストをアウタ−リ−ド全体に貼る場合に比べて低
減できるという効果が得られる。
(4) The material cost of the adhesive sheet is reduced by forming the adhesive sheet only on the portion which is plated and is necessary for connecting to an external device, that is, only the tip of the outer lead. The effect that it can be reduced compared to the case where it is attached to the entire outer lead is obtained.

【0021】(5)隣接したICの対向したアウタ−リ
−ドに共通して接着シ−トを貼ることにより、上記テ−
プの貼る作業工数を低減できるという効果が得られる。
(5) By attaching an adhesive sheet in common to the opposing outer leads of the adjacent ICs, the above-mentioned tape is attached.
It is possible to obtain the effect of reducing the man-hours for sticking the tape.

【0022】(6)接着シ−トをタイバ−と外枠の中間
に貼ることにより、アウタ−リ−ドをタイバ−や外枠か
ら切り離す切断工程においても影響されずに処理できる
という効果が得られる。
(6) By sticking the adhesive sheet between the tie bar and the outer frame, it is possible to obtain an effect that the outer lead can be processed without being affected even in the cutting step of separating the outer lead from the tie bar and the outer frame. To be

【0023】以上本発明者によってなされた発明を実施
例に基づき具体的説明したが、本発明は上記実施例に限
定されるものではなく、その要旨を逸脱しない範囲で種
種変更可能であることはいうまでもない。例えば、本実
施例では、接着テ−プは紫外線を照射することにより粘
性力を失うものであるが、その他に加熱等により粘性力
が失う材料を用いても良い。さらには、熱可塑性のプラ
スチックでメッキされたアウタ−リ−ドを表裏両側から
はさんで製造工程中搬送し、除去する際に熱を加えるよ
うにしても良い。また、本実施例では、リ−ドフレ−ム
の製造時に形成したメッキの保護等について適用する場
合について、主に述べているが、ICが完成したのちに
形成したメッキの保護等においても、メッキ後に接着テ
−プを貼ることで同様の効果が得られる。
Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various kinds of modifications can be made without departing from the scope of the invention. Needless to say. For example, in this embodiment, the adhesive tape loses its viscous force by being irradiated with ultraviolet rays, but a material whose viscous force is lost by heating or the like may be used. Further, the outer lead plated with a thermoplastic may be sandwiched between the front and back sides to be conveyed during the manufacturing process, and heat may be applied when removing the outer lead. In addition, in the present embodiment, the case where the protection of the plating formed at the time of manufacturing the lead frame is applied is mainly described, but the protection of the plating formed after the completion of the IC is also applied to the plating. Similar effects can be obtained by applying an adhesive tape later.

【0024】[0024]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記の通りである。
The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

【0025】すなわち、メッキされたリ−ド表面を保護
できるので、キズ、剥がれ、汚れ等メッキ不良起因によ
る不良発生を防止する効果がある。
That is, since the surface of the plated lead can be protected, there is an effect of preventing the occurrence of defects such as scratches, peeling, and stains due to defective plating.

【0026】また、アウタ−リ−ド間を連結して補強で
きるので、リ−ド曲がりを防止できるという効果が得ら
れる。
Further, since the outer lead and the lead can be connected and reinforced, the lead bending can be prevented.

【0027】[0027]

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例である半導体装置の製造方法
の概略プロセスフロ−、
FIG. 1 is a schematic process flow of a method for manufacturing a semiconductor device according to an embodiment of the present invention,

【図2】図1の製造方法で製造されるリ−ドフレ−ムの
製造説明図、
FIG. 2 is a manufacturing explanatory view of a lead frame manufactured by the manufacturing method of FIG.

【図3】接着シ−トの貼付を完了したリ−ドフレ−ム平
面図、
FIG. 3 is a plan view of a lead frame in which application of an adhesive sheet is completed,

【図4】接着シ−トを貼付けた状態で切断を行なったと
きのリ−ドフレ−ム平面図、
FIG. 4 is a plan view of a lead frame when cutting is performed with an adhesive sheet attached.

【図5】アウタ−リ−ドの折り曲げが完了したICの斜
視図、
FIG. 5 is a perspective view of the IC in which the outer lead is completely bent,

【図6】接着シ−トを貼付けたアウタ−リ−ドの断面図FIG. 6 is a sectional view of an outer lead having an adhesive sheet attached.

【図7】本発明の一実施例の応用例を説明するリ−ドフ
レ−ムの平面図である。
FIG. 7 is a plan view of a lead frame for explaining an application example of an embodiment of the present invention.

【符号の説明】 1…リ−ドフレ−ム、2…タブリ−ド、3…タブ、4…
チップ、5…ボンディングワイヤ、6…インナ−リ−
ド、7…タイバ−、8、16、17…アウタ−リ−ド、
9…パッケ−ジ、10、18…接着シ−ト、11…リ−
ドフレ−ム横枠、12…リ−ドフレ−ム縦枠、13、1
4、15…IC
[Explanation of Codes] 1 ... Lead frame, 2 ... Tab lead, 3 ... Tab, 4 ...
Chip, 5 ... Bonding wire, 6 ... Inner reel
De, 7 ... tie bar, 8, 16, 17 ... outer lead,
9 ... Package, 10, 18 ... Adhesive sheet, 11 ... Release
Horizontal horizontal frame, 12 ... Vertical vertical frame, 13, 1
4, 15 ... IC

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】外部からの電気的信号を半導体チップ上の
複数の電極に入出力するために形成された複数のアウタ
−リ−ドのメッキされた表面を、接着シ−トで保護する
ことを特徴とする半導体装置の製造方法。
1. An adhesive sheet protects the plated surfaces of a plurality of outer leads formed for inputting and outputting an external electrical signal to and from a plurality of electrodes on a semiconductor chip. A method for manufacturing a semiconductor device, comprising:
【請求項2】複数のチップを搭載したリ−ドフレ−ムを
モ−ルドする工程と、外部からの電気的信号を半導体チ
ップ上の複数の電極に入出力するために形成された複数
のメッキが施されたアウタ−リ−ドを一体的に連結する
接着シ−トを貼付るシ−ト貼付工程と、シ−トを貼付け
た状態でリ−ドフレ−ムのフレ−ム枠からアウタ−リ−
ドを分離する切断工程と、アウタ−リ−ドを介して電気
的な試験を行なうテスト工程と、アウタ−リ−ドから接
着シ−トを除去するシ−ト除去工程を有する半導体装置
の製造方法。
2. A step of molding a lead frame having a plurality of chips mounted thereon, and a plurality of platings formed for inputting / outputting an external electrical signal to / from a plurality of electrodes on a semiconductor chip. A sheet attaching step of attaching an adhesive sheet for integrally connecting the outer leads provided with the sheet, and an outer sheet from the frame frame of the lead frame with the sheet attached. Lee
Manufacture of a semiconductor device having a cutting step for separating the cord, a test step for conducting an electrical test through the outer lead, and a sheet removing step for removing the adhesive sheet from the outer lead Method.
【請求項3】接着シ−トは、紫外線を照射することによ
り粘着力が低下する接着剤が使用されており、シ−ト除
去前に紫外線を照射することによりアウタ−リ−ドから
接着シ−トを簡単に除去することを特徴とする請求項5
記載の半導体装置の製造方法。
3. The adhesive sheet is made of an adhesive whose adhesive strength is reduced by irradiating ultraviolet rays, and by irradiating ultraviolet rays before removing the sheet, the adhesive sheet is adhered to the adhesive sheet. -Easy removal of
A method for manufacturing a semiconductor device as described above.
JP4931992A 1992-03-06 1992-03-06 Manufacture of semiconductor device Pending JPH06120409A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4931992A JPH06120409A (en) 1992-03-06 1992-03-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4931992A JPH06120409A (en) 1992-03-06 1992-03-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH06120409A true JPH06120409A (en) 1994-04-28

Family

ID=12827654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4931992A Pending JPH06120409A (en) 1992-03-06 1992-03-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH06120409A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100287414B1 (en) * 1997-04-22 2001-06-01 도시바주식회사 Semiconductor device and manufacturing method of the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100287414B1 (en) * 1997-04-22 2001-06-01 도시바주식회사 Semiconductor device and manufacturing method of the same

Similar Documents

Publication Publication Date Title
USRE43443E1 (en) Leadframe semiconductor integrated circuit device using the same, and method of and process for fabricating the two
CN203300631U (en) Semiconductor device
JPH0355859A (en) Semiconductor die bonding method, strip carrier and integrated circuit bonding tape
JPH0621326A (en) Multiple package module on pc board and its formation method
KR101544844B1 (en) Wired rubber contact and method of manufacturing the same
KR19980068001A (en) Manufacturing method of semiconductor package
JP2004349728A (en) Method for manufacturing encapsulated electronic component, particularly integrated circuit
KR100266138B1 (en) Method for manufacturing chip scale package
KR100206026B1 (en) Semiconductor integrated circuit device
JPH0745641A (en) Semiconductor device mounting method
JPH06120409A (en) Manufacture of semiconductor device
JPH088293A (en) Structure for connecting electronic parts and connection method therefor
JP2009252778A (en) Manufacturing method of semiconductor package
JP2001148447A (en) Resin-sealed semiconductor device and method of manufacturing the same
JPH06236956A (en) Semiconductor device and its manufacture
JP3706082B2 (en) Lead frame, method of manufacturing the same, and method of manufacturing semiconductor device using the lead frame
US20150187688A1 (en) Method For Treating A Leadframe Surface And Device Having A Treated Leadframe Surface
JP2542675B2 (en) Semiconductor device
JPH04162734A (en) Semiconductor device and formation therefor
JPH0442547A (en) Method of mounting components on printed board
GB2295722A (en) Packaging integrated circuits
JPH11204577A (en) Manufacture of semiconductor device
JPH01278032A (en) Wire bonding process
JP2005277415A (en) Lead chip directly adhered semiconductor package, and manufacturing method and device of same
JP2005045041A (en) Semiconductor package and its manufacturing method