JPH06120167A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide low contact resistance through a simple process in regard to micro-contact on a submicron level by forming a silicide layer in an region of impurities formed in a preset region of a semiconductor substrate. CONSTITUTION:After a N-well 102 and a P-well 103 are first formed in a semiconductor substrate 101, a P+ diffused layer and a N+ diffused layer 105 are formed to form an interlayer insulating film 106. Next, a contact hole 107 is opened in the interlayer insulating film 106, a Ti layer of approximately 200Angstrom to 1000Angstrom is formed. Further, a barrier layer 109 of TiN, TiW and the like of 500Angstrom to 1500Angstrom is formed. Next, furnace annealing is performed at a temperature of 450 deg.C to 600 deg.C in an atmosphere of inert gas or hydrogen gas. In this case, a reaction occurs between a contact metal such as Ti and a silicon substrate base, forming a silicide layer 110. The final step comprises etching back after tungsten is formed over the entire surface, forming a contact plug 111, and forming a metal wiring 112 with Al-Cu and the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a device structure and a manufacturing method for realizing a semiconductor device having fine contact with excellent contact characteristics by a simple process. .

[0002]

2. Description of the Related Art In a submicron fine contact, an increase in contact resistance with a diffusion layer (particularly a P + diffusion layer) has been a problem. As a countermeasure for this, after opening the contact hole, B (boron) is additionally injected only in the P + diffusion region to increase the surface concentration of boron to reduce the contact resistance.

FIG. 2 shows a manufacturing process diagram of a conventional semiconductor device. In FIG. 2, in FIG. 2A, after the N-well 202 and the P-well 203 are formed in the semiconductor substrate 201, P +
The diffusion layer 204 and the N + diffusion layer 205 are formed, and the interlayer insulating film 206 is formed.
Is a step of forming. FIG. 2B shows the interlayer insulating film 20.
This is a step of forming a contact hole 207 in 6 and selecting only a P + diffusion region by a mask 208 and ion-implanting boron. FIG. 2C shows a lamp anneal (10) for activating the ion-implanted boron after removing the mask.
This is a step of forming a metal layer 210 of Al-Si or the like after performing a sputtering process to form a barrier layer 209 of Ti / TiN or the like.

[0004]

However, the conventional technique requires a photo step of selecting the P + diffusion region after the contact opening, an ion implantation step, and a step of activating the implanted dopant, which is complicated. there were.
Furthermore, since high-temperature heat treatment is required for activation, redistribution of impurities, damage due to thermal stress, etc. occur, which is a serious problem in devices of submicron or even half micron or less.

Therefore, the present invention solves such a problem, and provides a contact structure and a manufacturing method thereof for realizing a low contact resistance by a simpler process.

[0006]

A semiconductor device according to the present invention comprises: (1) a semiconductor substrate, an impurity region containing a high concentration of impurities formed in a predetermined region of the semiconductor substrate, and an opening above the impurity region. It has at least an interlayer insulating film having a hole and a silicide layer formed in the impurity region corresponding to the opening, and the impurity concentration contained in the silicide layer is 5 as an average value in the film thickness direction of the silicide layer. It is characterized in that it is not more than × 10 ¹⁹ cm ^-3 .

(2) The impurity region is P-type.

(3) The silicide layer is made of titanium silicide.

(4) The thickness of the silicide layer is 100
It is characterized by being Å to 900Å.

(5) A semiconductor substrate, an impurity region containing a high concentration of impurities formed in a predetermined region of the semiconductor substrate, an interlayer insulating film having an opening above the impurity region, and the opening. At least a silicide layer formed in the impurity region corresponding to the above and a barrier metal layer formed on the silicide layer, and at least a part of the barrier metal layer contains 1 atomic% or more of oxygen. Is characterized by.

(6) The concentration of impurities contained in the silicide layer is 5 × 10 ^{19 as} an average value in the thickness direction of the silicide layer.
It is characterized in that it is not more than cm ^-3 .

(7) The barrier metal is TiN or TiW.

Further, the method of manufacturing a semiconductor device according to the present invention includes (8) a step of forming a diffusion layer containing a high concentration of impurities on a semiconductor substrate, a step of forming an interlayer insulating film covering the diffusion layer, There is at least a step of forming a contact hole in the interlayer insulating film on the diffusion layer, a step of depositing a metal layer, and a step of reacting the metal layer with the semiconductor substrate by heat treatment to form a silicide layer, and the heat treatment temperature is It is characterized in that the temperature is 550 ° C. or lower.

(9) The heat treatment time is 2 hours or more.

(10) The impurity region is P-type.

(11) The silicide layer is made of titanium silicide.

(12) A step of forming a diffusion layer containing a high concentration of impurities on a semiconductor substrate, a step of forming an interlayer insulating film covering the diffusion layer, and a contact hole formed in the interlayer insulating film on the diffusion layer. A step of depositing a metal layer, a step of laminating a barrier metal on the metal layer, and a heat treatment in a state where at least the barrier metal is laminated on the metal layer to react the metal layer with the semiconductor substrate. The method is characterized by including at least a step of forming a silicide layer.

(13) The barrier metal is TiN or TiW.

(14) At least a part of the barrier metal contains 1 atomic% or more of oxygen.

[0020]

FIG. 1 is an example of a manufacturing process diagram of a semiconductor device in an embodiment of the present invention.

In FIG. 1, FIG. 1A shows a semiconductor substrate.
In this step, after forming the N-well 102 and the P-well 103 in the 101, the P + diffusion layer 104 and the N + diffusion layer 105 are formed, and the interlayer insulating film 106 is formed. As a method for forming the P + diffusion layer, BF ₂ + is ₂ to 4 × at about 30 to 50 keV.
There is a method such as ion implantation of about 10 ¹⁵ (cm ⁻² ). As a method for forming the N + diffusion layer, As is 30
There is a method such as ion implantation of about 4 to 6 × 10 ¹⁵ (cm ⁻³ ) at about 50 keV. In FIG. 1B, a contact hole 107 is opened in the interlayer insulating film 106, and a Ti layer 108 is formed.
Is formed on the order of 200Å to 1000Å.
This is a step of forming a barrier layer 109 such as W having a thickness of about 500Å to 1500Å. As a method for forming the Ti layer and the barrier layer,
There are a sputtering method, a CVD method, an ECR-CVD method and the like. FIG. 1C shows a step of performing furnace annealing in an inert gas or hydrogen gas atmosphere at about 450 ° C. to 600 ° C.
In this case, the contact metal such as Ti reacts with the underlying silicon substrate, and the reaction proceeds while forming the silicide layer 110. FIG. 1D shows a blanket CVD method.
After forming W (tungsten) on the entire surface, it is etched back to form a contact plug 111, and then Al-Cu.
Etc. is a step of forming the metal wiring 112. In this embodiment, the case where W or the like is formed on the entire surface by the blanket CVD method is taken as an example, but the present invention is not limited to this.

The electrical characteristics of the semiconductor device according to the present invention will be described below. According to the present invention, for example, in a contact hole having an interlayer insulating film thickness of 1.5 μm and a contact diameter of 0.5 μm and an aspect ratio of 3, the contact resistance is about 35Ω to 90Ω (P + diffusion layer), about 30Ω to 40Ω.
(N + diffusion layer) was realized. Also, after the Al wiring is formed, 5
Even if annealing was performed for 30 minutes at 25 ° C., a contact structure that was thermally stable could be realized without causing characteristic deterioration such as junction leakage.

Next, the mechanism by which the contact resistance is greatly reduced by the present invention will be described. By forming a Ti film and performing heat treatment, Ti reacts with Si to form a Ti silicide. At this time, the interface between Si and Ti silicide is moved into the Si substrate, and the B concentration at the Si / Ti silicide interface after the heat treatment is significantly higher than the B concentration at the Si / Ti interface before the heat treatment. I understood. As a result, the contact resistance with the P + diffusion layer before heat treatment (0.5
While the μm diameter and the aspect ratio 3) were as high as about 350Ω, they were dramatically reduced to about 40Ω after the heat treatment at 500 ° C. for 10 hours. It was also found that there is a large difference in the amount of B redistributed in the Ti silicide depending on the heat treatment temperature. In low temperature long time annealing at 500 ° C. for 10 hours, Ti
While the amount of B redistributed in the silicide is small and the B concentration at the Si / Ti silicide interface is kept high,
It was found that as the annealing temperature was increased, the amount of B redistributed in the Ti silicide was large, and the B concentration at the Si / Ti silicide interface was low. Although a clear causal relationship is not clear so far, it seems to correspond to that the solid solution limit of B in Ti silicide increases with increasing annealing temperature. As a result, in the heat treatment at 700 ° C. for 10 minutes, the contact resistance with the P + diffusion layer (0.5 μm
Diameter and aspect ratio 3) are as high as 230Ω, while 5
In the heat treatment at 00 ° C. for 10 hours, as described above, it was significantly reduced to about 40Ω. An example of the annealing conditions and the contact resistance value (0.5 μm diameter, aspect ratio 3) between the P + diffusion layer is about 35Ω, 50 after annealing at 450 ° C. for 20 hours.
About 40Ω at 0 ° C for 10 hours, about 55Ω at 550 ° C for 5 hours,
Approx. 80Ω at 580 ° C for 2 hours, approx. 10 at 600 ° C for 30 minutes
It was 0Ω, about 150Ω at 650 ° C for 20 minutes, and about 230Ω at 700 ° C for 10 minutes. From now on, the annealing temperature is 600
It can be seen that the temperature is preferably not higher than 0 ° C and is particularly excellent at not higher than about 550 ° C. The optimum annealing time varies depending on the annealing temperature, but the optimum value exists for about 30 minutes to about 20 hours.

Further, the average value of the boron concentration in the film thickness direction in the Ti silicide formed by forming Ti about 100∂ on the bottom of the contact and annealing at 500 ° C. for 10 hours is 2 × 10.
^{About 19} (cm ^-3 ), 3 × by annealing at 550 ° C. for 5 hours
It is about 10 ¹⁹ (cm ^-3 ) and about 5 × 10 ¹⁹ (cm ^-3 ) in annealing at 600 ° C. for 30 minutes. On the other hand, 650 ℃ 20
About 6 × 10 ¹⁹ (cm ⁻³ ) at 700 ° C.
Annealing for 10 minutes results in about 7 × 10 ¹⁹ (cm ⁻³ ) or more. Therefore, the average value of the boron concentration in the Ti silicide in the film thickness direction is preferably about 5 × 10 ¹⁹ (cm ⁻³ ) or less, and particularly preferably about 3 × 10 ¹⁹ (cm ⁻³ ) or less. .

Further, the amount of boron redistributed in the Ti silicide also depends on the Ti silicide film thickness which changes depending on the Ti film thickness deposited on the bottom of the contact. For example,
In high-temperature annealing at 650 ° C. for 20 minutes, the contact resistance tends to increase when the Ti silicide film thickness reaches about 250Å. On the other hand, in the case of annealing at a low temperature of about 550 ° C. to 600 ° C. or less, the contact resistance is not increased due to the redistribution of boron at the Ti silicide film thickness of about 250 Å, but rather the contact resistance is reduced by increasing the film thickness. Shows a tendency to However, when the thickness of the Ti silicide formed on the bottom of the contact is 900 Å or more, the amount of boron redistributed in the silicide cannot be ignored even by low temperature annealing, and the contact resistance tends to increase. On the other hand, when the thickness of the Ti silicide film formed on the bottom of the contact is 100 Å or less, the movement of the interface due to silicidation does not occur sufficiently, and the effect of reducing the contact resistance is significantly reduced. From the above results, the thickness of the Ti silicide film formed on the bottom of the contact is 100Å to 900Å
Is desirable.

During the annealing, TiN on Ti,
A manufacturing method of annealing in a state where TiW and the like are laminated is
It was also found to be effective in reducing the contact resistance with the P + diffusion layer. If you do not stack TiN, TiW, etc.,
It was found that during annealing, boron in the diffusion layer diffuses out of Ti and escapes into the vapor phase, and the boron concentration in the Si substrate decreases. On the other hand, if TiN, TiW, etc. are annealed in a stacked state, TiN, TiW, etc. serve as a barrier layer for preventing the diffusion of boron, and the outward diffusion can be prevented, so that the concentration of boron in the Si substrate can be prevented from lowering. understood. In particular, in the barrier layer such as TiN, TiW,
It was also found that when 1 atomic% or more of oxygen is added to at least part of the film thickness direction, diffusion of impurities such as boron during heat treatment is further suppressed. Examples of the method of adding oxygen include a method of adding oxygen in a sputtering atmosphere when forming a barrier layer by a sputtering method, and a method of annealing in a oxygen atmosphere after forming the barrier layer. As described above, the effect of promoting the complete silicidation while suppressing the redistribution of boron in the Ti silicide by the low temperature long-time annealing is
By adding the outward diffusion preventing effect of boron by N and TiW, the boron concentration at the Si / Ti silicide interface can be increased and the contact resistance can be greatly reduced. Especially Ti
The effect of N and TiW to prevent outward diffusion of boron becomes more effective and indispensable as the annealing time becomes longer.

In this embodiment, Ti is formed on the silicon substrate.
However, the present invention is not limited to this. For example,
In addition to the silicon substrate, it can be applied to a Si epi layer, a poly-Si layer, and the like. In addition to Ti, a method of forming Pt (platinum), Ta (tantalum), or the like, and performing silicidation by annealing is also effective. Further, the present invention is particularly effective in reducing the contact resistance with the P + diffusion layer, but is also effective in reducing the contact resistance with the N + diffusion layer doped with As or the like.

As described above, according to the semiconductor device and the manufacturing method thereof according to the present invention, a semiconductor device having excellent contact characteristics for both the P + diffusion layer and the N + diffusion layer can be formed by a simple process. .

The present invention is not limited to the embodiment shown in FIG. 1 and can be widely applied to the contact structure of semiconductor devices in general.

[0030]

As described above, according to the present invention, both the P + diffusion layer and the N + diffusion layer have low resistance and excellent ohmic properties for a contact hole having a contact diameter of submicron or less and a high aspect ratio. A contact structure can be formed. Further, according to the present invention, it is possible to realize an excellent contact characteristic by a simpler process, which does not require a conventional ion implantation process or a high temperature annealing process for activating impurities after the contact hole is opened. Became.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to an embodiment of the invention.

FIG. 2 is a manufacturing process diagram of a conventional semiconductor device.

[Explanation of Codes] 102 ・ ・ ・ N-well 103 ・ ・ ・ P-well 104 ・ ・ ・ P + diffusion layer 105 ・ ・ ・ N + diffusion layer 106 ・ ・ ・ Inter-layer insulation film 107 ・ ・ ・ Contact hole 108 ・ ・ ・Ti layer 109 ・ ・ ・ Barrier layer 110 ・ ・ ・ Silicide layer 111 ・ ・ ・ Contact plug 112 ・ ・ ・ Metal wiring

Claims (14)

[Claims] 1. A semiconductor substrate, an impurity region containing a high concentration of impurities formed in a predetermined region of the semiconductor substrate, an interlayer insulating film having an opening above the impurity region, and an opening in the opening. There is at least a silicide layer formed in the corresponding impurity region, and the concentration of impurities contained in the silicide layer is 5 × 10 ¹⁹ cm ^{−3 as} an average value in the thickness direction of the silicide layer.
A semiconductor device characterized by the following. 2. The semiconductor device according to claim 1, wherein the impurity region is P-type. 3. The semiconductor device according to claim 1, wherein the silicide layer is titanium silicide. 4. The thickness of the silicide layer is 100Å-9
It is 00Å, Claim 1 or Claim 2 characterized by the above-mentioned.
Alternatively, the semiconductor device according to claim 3. 5. A semiconductor substrate, an impurity region containing a high concentration of impurities formed in a predetermined region of the semiconductor substrate, an interlayer insulating film having an opening above the impurity region, and an opening in the opening. There is at least a silicide layer formed in the corresponding impurity region and a barrier metal layer formed on the silicide layer, and at least a part of the barrier metal layer is 1
A semiconductor device characterized by containing at least atomic% of oxygen. 6. The concentration of impurities contained in the silicide layer is 5 × 10 ¹⁹ cm ^{−3 as} an average value in the thickness direction of the silicide layer.
The semiconductor device according to claim 5, wherein: 7. The barrier metal is TiN or Ti
7. The semiconductor device according to claim 5, wherein the semiconductor device is W. 8. A step of forming a diffusion layer containing a high concentration of impurities on a semiconductor substrate, a step of forming an interlayer insulating film covering the diffusion layer, and a step of forming a contact hole in the interlayer insulating film on the diffusion layer. And a step of depositing a metal layer, and a step of reacting the metal layer with a semiconductor substrate by heat treatment to form a silicide layer, wherein the heat treatment temperature is 550 ° C. or lower. Production method. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the heat treatment time is 2 hours or more. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the impurity region is P-type. 11. The method of manufacturing a semiconductor device according to claim 8, wherein the silicide layer is titanium silicide. 12. A step of forming a diffusion layer containing a high concentration of impurities on a semiconductor substrate, a step of forming an interlayer insulating film covering the diffusion layer, and a step of forming a contact hole in the interlayer insulating film on the diffusion layer. A step of depositing a metal layer, a step of laminating a barrier metal on the metal layer, and a heat treatment in a state where at least the barrier metal is laminated on the metal layer to react the metal layer with the semiconductor substrate to form a silicide. A method of manufacturing a semiconductor device, comprising at least a step of forming a layer. 13. The barrier metal is TiN or T
13. The method for manufacturing a semiconductor device according to claim 12, wherein the method is iW. 14. The method of manufacturing a semiconductor device according to claim 12, wherein at least a part of the barrier metal contains 1 atomic% or more of oxygen.