JPH06119792A - Semiconductor storage circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption at the time of operating at a low speed by making a pull-up element nonconductive at the time of selecting the output of a sense amplifier, and making the sense amplifier inactive at the time of selecting a digit line and also, making the pull-up element conductive. CONSTITUTION:MOSFET 104 being the pull-up element is turned OFF when a control signal 105 is a logical value '1', and the sense amplifier 102 is activated by an EN input, and a signal on a digit line 101 is amplified and outputted at high speed. Then, the amplifier 102 becomes a standby state when the signal is the logical value '0', and though the FET 104 is turned ON, current drive ability is sufficiently low, a level capable of deciding the logical value '0' is outputted to the digit line 101 when a selection bit line is turned ON. Then, the logical level of the digit line 101 is inversed and outputted as the output 106 as it is with low power consumption at a low speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit,
Especially ASIC (Application Specif)
ROM used in the ied IC field (memory that can only read stored data: Read Onl
y Memory) macro library.

[0002]

2. Description of the Related Art A conventional example will be described below with reference to the drawings. FIG. 3 is a block diagram showing a general configuration of the ROM. In FIG. 3, the input address is distributed to the X decoder 306 and the Y decoder 307 via the address buffer 305. In the X decoder 306,
The input address is decoded and the memory cell array 3
01 physical word line is selected. On the other hand, Y decoder 3
07, Y selector 302 selects the digit line of the memory cell array according to the distributed address.

Further, in the sense amplifier / output circuit 303, a minute signal on the selected digit line is amplified and data is output to the outside via an output buffer. The control circuit 304 controls whether the sense amplifier is active / inactive (hereinafter, active / standby) and the output buffer O
Control N / OFF.

FIG. 4 is a circuit diagram showing a current mirror type sense amplifier as an example of the sense amplifier portion of the sense amplifier / output circuit 303 in FIG.

In FIG. 4, P-channel MOS type field effect transistors (FETs) 407, 408 and 410,
N-channel MOSFETs 406, 409, 411 and N
OR gate 41, digit line 401, terminal of STBY signal 402, terminal of STBY signal 403, VR
A terminal for the EF signal 404, a terminal for the data output 405,
It is provided with a ground (GND) terminal and a constant voltage VDD terminal.

In FIG. 4, STBY signals 402, ST
The BY signal 403 is a complementary signal and controls active / standby of the sense amplifier. The power supply voltage VDD level is referred to as a logical value 1 and the GND level is referred to as a logical value 0. When the STBY signal 402 has a logical value 1, the standby state is set, all DC current paths are cut off, and unnecessary power consumption is suppressed. It is possible.

A logical value 0 is output to the data output 405 at this time. When the STBY signal 402 has a logical value of 0, the sense amplifier is activated and the selected bit cell in the memory cell array 301 is turned on / off.
It operates according to the state (usually the transistor there is valid / invalid, or there is a transistor there / is not supported). When the selected bit cell is OFF, no current flows on the digit line, and the P-channel MOSFET 407 is OF
It becomes the F state. The P-channel MOSFET 408 whose gate input is common to the MOSFET 407 is also turned off.

On the other hand, the reference voltage VREF404 is applied to the gate.
The N-channel MOSFET 409 to which is input is constantly turned on, and a logical value 0 is output to the data output 405. When the selected bit cell is ON, P channel type M
A steady current flows through the paths of the OSFETs 407 and 406, the Y selector, and the bit cell transistor. In response to this,
A steady current also flows from the P-channel MOSFET 407 and the P-channel MOSFET 408 having the same gate input to the N-channel MOSFET 404, and the data output 405 includes the MOSFET 408 and the MOSFET 4.
A signal which can be regarded as a logical value 1 is output although it is not a complete VDD level divided by 09.

[0009]

As described above, when the sense amplifier is used to read the data of the memory cell, the data can be read at high speed, but a steady current flows in the sense amplifier to increase power consumption. In particular, a ROM incorporated in an ASIC product has various uses, and the specifications and performance required for each use differ. The most typical specification is the ROM storage capacity size, and the output bit width and the number of words.

In terms of performance, the performances that are usually noticed are read speed and power consumption, and rather read speed is often given higher priority as required performance. Therefore, in order to support more applications, it is necessary to prepare a ROM macro library in which the read speed is increased as much as possible by using the sense amplifier as described above.

However, in this case, even in an application where a high read speed is not required, there is a problem that excessive power is similarly consumed by the steady current in the sense amplifier. It is possible to separately prepare a ROM macro library suitable for constant power consumption, but as mentioned above, it takes time and money to develop a macro library that supports a wide variety of specifications. In addition, there is a problem in that it is not possible to meet the demand for operating at high speed at one time and at low time at another time, which requires low power consumption.

An object of the present invention is to provide a semiconductor memory circuit which solves the above-mentioned problems and can meet a variety of needs.

[0013]

A semiconductor memory circuit according to the present invention has a structure in which a pull-up element connected to a digit line selected by a Y selector and a signal on the digit line are input to activate / deactivate by a control signal. A sense amplifier whose activeness is controlled, a selector which inputs the output of the sense amplifier and the signal of the digit line, selects one of them according to the control signal, and outputs the selected signal, and the selector selects the output of the sense amplifier Control means for activating the sense amplifier and non-conducting the pull-up element when selecting the digit line, and deactivating the sense amplifier and conducting the pull-up element for selecting the digit line. It is characterized by

[0014]

The present invention will be described below with reference to the drawings. FIG. 1 shows an R of the semiconductor memory circuit of the first embodiment of the present invention.
It is a circuit diagram which shows the read-out circuit of OM.

In this embodiment, the sense amplifier 102 in FIG. 1 may be the same as that shown in FIG. 4, and the EN input corresponds to the STBY signal 403 in FIG.

Referring to FIG. 1, in this embodiment, a sense amplifier 102 having IN, EN inputs and OUT, and a selector 1 are provided.
03, P-channel MOSFET 104, digit line 101, control signal MOD 105 input terminal, data output 106 terminal, inverter 4, constant voltage VDD.
And an input terminal of. Here, the selector 103
Has an inverter 3 and MOSFETs 1 and 2.

First, the operation when the control signal MOD105 has a logical value of 1 will be described. At this time, the P-channel MOSFET 104, which is a pull-up element, receives the logic value 1 of the control signal MOD105 as a gate input and is turned off.
The digit line 101 is not affected at all. On the other hand, since the sense amplifier 102 inputs the logical value 1 to the EN input, it is in the active state and amplifies and outputs the signal on the digit line 101. In the selector 103, the output of the sense amplifier 102 is selected, and the output of the sense amplifier 102 is inverted and output as the data output 106.

Next, the operation when the control signal MOD105 has a logical value of 0 will be described. At this time, sense amplifier 1
02 receives the logical value 0 of the control signal MOD105 at the EN input and is in a standby state. On the other hand, the P-channel MOSFET 104 is turned on because the logic value 0 is input as the gate input, but the current driving capability is sufficiently lower than that of the N-channel MOSFET that constitutes the bit cell. Therefore, when the selected bit cell is ON, the digit line 101 outputs a level that can be determined to be a logical value 0. The digit line 101 when the selected bit cell is OFF becomes a logical value 1 by the P-channel MOSFET 104. In the selector 103, the digit line 101 is selected, and the logic level of the digit line 101 is inverted and output as it is as the data output 106.

FIG. 2 is a circuit diagram showing a ROM read circuit of a semiconductor memory circuit according to a second embodiment of the present invention.

2 is different from the embodiment of FIG. 1 in that the configuration of the selector 203 and the control signal CS are different.
That is, the terminal 209 is added.

Further, the inverter 21 and the OR gate 20
8, AND gate 207 is added. Selector 20
3 has inverters 22, 23, 24.

The sense amplifier 202 may be the same as that shown in FIG. 4, with the EN input corresponding to the STBY control signal 403 in FIG. First, the operation when the control signal MOD 205 has the logical value 1 will be described. At this time, the OR gate 208 outputs a logical value 1 regardless of the state of the control signal CS209. Therefore, P-channel MOSFET
204 receives the output of the OR gate 208 and is in an OFF state, and does not affect the digit line 201 at all.

On the other hand, the sense amplifier 202 has an A input to the EN input.
It receives the output of ND gate 207, but now MOD20
Since the logic value 5 is fixed to 1, the control signal CS209 is practically used.
Will be controlled by. When the control signal CS209 has a logical value of 1, the sense amplifier 202 is in an active state and amplifies and outputs the signal on the digit line 201. If the control signal CS209 has a logical value of 0, the sense amplifier 202 is in a standby state and outputs invalid data. In the selector 203, the output of the sense amplifier 202 is selected, and the output of the sense amplifier 202 is output as the data output 206.

Next, the operation when the control signal MOD 205 has a logical value of 0 will be described. At this time, AND gate 2
07 outputs a logical value 0 regardless of the state of the control signal CS209. The sense amplifier 202 receives the logical value 0 which is the output of the AND gate 207 at the EN input and is in the standby state.

On the other hand, the P-channel MOSFET 204
Receives the output of the OR gate 208 through the gate input, but since the MOD 205 has a fixed logic value of 0 now, it is effectively controlled by the control signal CS209.
If the control signal CS209 is a logical value 1, the P channel type M
The OSFET 204 is turned on because it inputs a logical value of 0, but its current drivability is sufficiently lower than that of the N-channel MOSFET that constitutes the bit cell. Therefore,
When the selected bit cell is ON, the digit line 201 outputs a level that can be determined to be a logical value 0. The digit line 201 when the selected bit cell is OFF becomes a logical value 1 by the P-channel MOSFET 204.
If the control signal CS209 has a logical value of 0, the P-channel MOSFET 204 inputs a logical value of 1 and is turned off.
It becomes a state and becomes invalid data on the digit line. The selector 203 selects the digit line, and the logic level of the digit line is directly output as the data output 206.

[0026]

As described above, according to the present invention, it is possible to select whether or not to use the sense amplifier when reading data by the control signal. When the sense amplifier is used, the sense amplifier is used. Power consumption increases due to the steady current of, but the high-speed reading is possible, and the reading speed becomes slower when the sense amplifier is not used, but the steady current is due to the pull-up element with a low current drive capability that pulls up the digit line. Since it is only one, there is an effect that power consumption can be reduced.

ASICs used in various fields
By applying the ROM according to the present invention as a memory macro library for products, it is possible for the library provider to avoid the waste of preparing a high speed ROM and a low power consumption ROM macro library in duplicate. Has the effect that a single ROM macro library can be used at high speed and low power consumption as desired by the user.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor memory circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram showing a general configuration of a ROM.

FIG. 4 is a circuit diagram showing a conventional circuit of a sense amplifier section shown in FIG.

[Explanation of symbols]

 101, 201 Digit line 102, 202 Sense amplifier 103, 203 Selector 104, 204 Pull-up element 105, 205 Control signal MOD 106, 206 Data output 207, 208 Gate 209 Control signal MCS 301 Memory cell array 302 Y selector 303 Sense amplifier / output Circuit 304 Control circuit 305 Address buffer 306 X decoder 307 Y decoder 401 Digit line 402,403 Standby control signal 404 Reference voltage 405 Data output 406,409 N-channel MOSFET 407,408 P-channel MOSFET

Claims (2)

[Claims] 1. A pull-up element connected to a digit line selected by a Y selector, a sense amplifier to which a signal of the digit line is input and whose active / inactive state is controlled by a control signal, and an output of the sense amplifier. And a signal of the digit line, select one of them according to the control signal and output the selector, and activate the sense amplifier and select the pull-up when selecting the output of the sense amplifier in the selector. A semiconductor memory circuit comprising: a control means for turning off the element and turning off the sense amplifier when the digit line is selected and turning on the pull-up element. 2. The semiconductor memory circuit according to claim 1, wherein the selector comprises three inverters.