JPH06119776A - Dynamic semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a dynamic semiconductor memory preventing destruction due to an internal boosting node at a burn-in time and setting a burn-in time to a proper value. CONSTITUTION:A P type MOS transistor 13 is turned ON by a control signal B. I. Enable' at a burn-in time, and an internal boosting signal is cramped to an internal source voltage + the threshold value Vth of an N type MOS transistor 14 level. The path of the transistors 13, 14 is interrupted always at a regular time excepting that, and the internal boosting signal is an internal source voltage + the threshold value Vth of an n type MOS transistor 11 + the threshold value Vth of the n type MOS transistor 12 level. Then, when the threshold values Vth.n of the n type MOS transistors 11, 12, 14 for cramping are equal, the internal boosting signal becomes the internal source voltage + 2XVth.n at a regular time and the internal source voltage + Vth.n at a burn-in time, and the internal boosting signal is lowered by the Vth.n in a cramp level at a burn-in time than a regular time, and the node conducted to the signal is protected by that.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory having an internal power supply voltage down circuit, and more particularly to power supply voltage control during burn-in.

[0002]

2. Description of the Related Art Conventionally, in a dynamic semiconductor memory, a power supply voltage from the outside has been applied to the inside as it is (that is, if 5 V is applied from the outside, the inside is also 5 V), but the semiconductor device is miniaturized year by year. However, when the gate length of the transistor enters the submicron world, the reliability problem due to the electric field has come to occur.

Therefore, recently, in a highly integrated memory such as 16M DRAM, an internal power supply voltage dropping circuit for ensuring the reliability of the device by internally lowering the voltage to about 3V to 4V while the applied voltage of the external power supply voltage is 5V. Some are equipped with.

By the way, generally, in a semiconductor memory, in order to remove an initial defect caused by a minute defect generated in a manufacturing process in a test process before shipping, a continuous operation at higher temperature and higher voltage than in normal use is performed. There is a so-called burn-in continuous operation test that is performed for several hours to several tens of hours. Here, the reason why the temperature is set to high temperature and high voltage is to accelerate the stress applied to the device so as to correspond to several years to several decades under normal operating conditions.

Therefore, even in the semiconductor memory having the internal power supply voltage down circuit, if the external power supply voltage is increased, the internal power supply voltage also rises at a constant rate or becomes equal to the external power supply voltage, or special timing setting, etc. In general, an external power source and an internal power source are connected to each other so that acceleration can be performed by a voltage inside the device.

[0006]

However, in the voltage acceleration during burn-in by the above-described conventional internal power supply voltage down circuit, when the power supply voltage is simply increased, the internal voltage is increased like the word line of the memory cell of the dynamic semiconductor memory. The boosted signal was so stressed that it destroyed the chip unnecessarily.

On the other hand, if the voltage is lowered to such an extent that it is not destroyed, on the other hand, the burn-in time in the manufacturing process becomes hundreds to thousands of hours, resulting in a significant loss of productivity. There is.

The present invention has been made in order to solve the above-mentioned problems, and the signal level of the internal boosting signal is increased so that the power supply voltage during burn-in can be increased to a value at which an appropriate voltage acceleration can be obtained. It is an object of the present invention to obtain a dynamic semiconductor memory capable of controlling the semiconductor device during burn-in and detecting an initial defect in a burn-in time that does not impair productivity.

[0009]

A dynamic semiconductor memory according to claim 1 of the present invention is a dynamic semiconductor memory having an internal power supply voltage step-down circuit for lowering a voltage level of an internal power supply as compared with an external power supply. It is provided with a clamp circuit that sets the clamp level of the internal power supply to a lower level than that during normal use at the time of burn-in for performing a continuous operation test for removing.

The dynamic semiconductor memory according to a second aspect of the invention is a dynamic semiconductor memory having an internal power supply voltage step-down circuit that lowers the voltage level of the internal power supply as compared with the external power supply. In the burn-in for the continuous operation test for removing the above, the memory cell section and the peripheral circuit section are separately provided with a power supply setting circuit.

[0011]

According to the first aspect of the present invention, the dynamic semiconductor memory prevents the chip from being destroyed during burn-in by changing the clamp level of the internally boosted signal during burn-in and during normal use.

According to another aspect of the dynamic semiconductor memory of the present invention, the internal voltage system in which the internally boosted signal is used and the internal voltage system used in the memory cell are independently controlled at the time of burn-in to prevent damage during chip burn-in. prevent.

[0013]

【Example】

Example 1. An embodiment of the present invention will be described below. Figure 1
3 is a circuit diagram showing a clamp circuit of an internal booster circuit according to Embodiment 1. FIG. This internal booster circuit is an example provided with a means for preventing an unnecessarily rising level of the internal boosted signal that is boosted internally and causes chip destruction at the time of burn-in by changing the clamped level.

In FIG. 1, 11, 12, and 14 are N-type MOS transistors, 13 is a P-type MOS transistor, and the gate of the P-type MOS transistor 13 is activated to "L" level during burn-in. Control signal bar B. I. Enable is input. The control signal during burn-in is, for example, 5 V when the external power supply voltage is increased.
Is activated when the voltage exceeds 7V or more, or is applied based on the recognition of burn-in by an address key or the like in which a high voltage is applied to a specific pin at a specific timing. The internal power supply shown in the figure is a power supply that has been dropped by the internal power supply voltage down circuit at a constant ratio to the external power supply.

Next, the operation according to the configuration of FIG. 1 will be described.
Now that the burn-in is recognized, the control signal bar B. I. When Enable is activated to "L" level, the P-type MOS transistor 13 is turned on, whereby the internal boosted signal is clamped to the internal power supply voltage + threshold _Vth level of the N-type MOS transistor 14. Like

At other times, that is, in normal times, the paths of the transistors 13 and 14 are always cut off, so that the internal boosted signal is clamped by the n-type MOS transistors 11 and 12, that is, the internal power supply voltage + n-type MOS.
The threshold value V _{th of the} transistor 11 + the threshold value V _th level of the n-type MOS transistor 12 is set.

Therefore, assuming that the clamping n-type MOS transistors 11, 12, and 14 have the same threshold value V _th · _n , the normal power supply voltage is + 2 × V _th · _n .
At the time of burn-in, the internal power supply voltage becomes + V _th · _n, and V
_{During the} burn-in, the clamp level of the internal boosted signal by _th · _n becomes lower than in the normal state, and the node communicating with this signal is protected accordingly.

When performing a burn-in with a high power supply voltage, as shown in FIG. 2, the internal power supply voltage level may be directly set during the burn-in without using the n-type MOS transistor 14 of FIG.

Therefore, according to the first embodiment, by controlling the level of the internal signal boosted internally during burn-in, it is possible to perform appropriate voltage acceleration and prevent chip destruction.

Next, a second embodiment of the present invention will be described. FIG. 3 is a configuration diagram according to the second embodiment. As shown in FIG. 3, the internal voltage down converter used for the memory cell and the internal voltage down converter used for the peripheral circuit including the voltage boost level are independently controlled without paying attention to only the voltage boost level, and the power supply voltage itself at the time of burn-in It is also possible to change the value of.

At this time, the burn-in control signal bar B. I. The Enable is activated, and the external power supply comes to be output to the memory cell power supply as it is, and the peripheral circuit power supply has a level lower than the external power supply by the threshold value V _th of the n-type MOS transistor 22. It is designed to work. The reason for the higher cost for the memory cell is that the main purpose at the time of burn-in is to screen a defective cell by applying a high electric field to a large number of memory cells having a large area.

[0022]

As described above, according to the first aspect of the present invention, defective products are eliminated in the dynamic semiconductor memory having the internal power supply voltage down circuit for lowering the voltage level of the internal power supply as compared with the external power supply. A clamp circuit that sets the clamp level of the internal power supply to a lower level than that during normal use during burn-in for performing continuous operation tests prevents the internal boost level from becoming excessively high during burn-in. There is an effect that a dynamic semiconductor memory in which the power supply voltage can be set to a high potential in which burn-in can be performed in a time that does not impair productivity is obtained.

According to a second aspect of the present invention, in a dynamic semiconductor memory having an internal power supply voltage step-down circuit that lowers the voltage level of the internal power supply than that of the external power supply, the voltage level of the internal power supply is continuously changed to eliminate defective products. At the time of burn-in for the operation test, the memory cell section and the peripheral circuit section are equipped with a power supply setting circuit that is set separately, so the internal voltage system used for the internally boosted signal and the internal voltage system used for the memory cell are There is an effect that the chip can be prevented from being destroyed during burn-in by controlling independently at the time of burn-in.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a clamp circuit of an internal booster circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of FIG.

FIG. 3 is a circuit diagram showing a clamp circuit of an internal booster circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 11 n-type MOS transistor 12 n-type MOS transistor 13 p-type MOS transistor 14 n-type MOS transistor 21 p-type MOS transistor 22 n-type MOS transistor 23 p-type MOS transistor

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[Procedure amendment]

[Submission date] April 12, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

[0003] Therefore, recently, for example in a highly integrated memory such as 16M DRAM, yet applied voltage of the external power supply voltage is 5V, and an internal descending internal power supply to ensure the reliability of the device by lowering the voltage to approximately 3V~4V pressure Some have a circuit.

Claims (2)

[Claims] 1. A dynamic semiconductor memory having an internal power supply voltage-down circuit for lowering the voltage level of an internal power supply as compared with an external power supply, wherein the clamp level of the internal power supply is set at the time of burn-in for conducting a continuous operation test for removing defective products. A dynamic semiconductor memory having a clamp circuit which is set lower than that during normal use. 2. A dynamic semiconductor memory having an internal power supply voltage step-down circuit for lowering the voltage level of an internal power supply than an external power supply, at the time of burn-in for a continuous operation test for removing defective products. A dynamic semiconductor memory having a power setting circuit for separately setting a memory cell section and a peripheral circuit section.