JPH06112995A - Test method for communication use ic - Google Patents

Abstract

PURPOSE:To provide a method for conducting test of high reliability with simple hardware configuration in the test method for the communication use IC inputting an asynchronous character signal and a clock signal from a MODEM and outputting a synchronizing character signal. CONSTITUTION:This method is provided with a process in which the operation of a communication use IC is simulated to generate asynchronizing character signal A1, a clock signal B1 and a synchronizing character signal C1, a process in which each signal is sampled at a prescribed period to generate sampling signals A2, B2, C2, a process in which an asynchronizing character signal A3 and a clock signal B3 are generated based on each sampling signal, a process in which the signals A3, B3 are inputted to the communication use IC and a synchronizing character signal C3 is outputted thererfrom, a process the signal C3 is sampled at a prescribed period to generate a sampling signal C4 and a process in which the sampling signals C2, C4 are compared.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for a communication IC having an asynchronous / synchronous conversion function.

[0002]

2. Description of the Related Art I for communication having an asynchronous / synchronous conversion function
When testing the operation of C, it is necessary to carry out the test in consideration of the fluctuation of the communication speed of the asynchronous character signal with respect to the communication speed of the clock signal.

[0003]

Therefore, it has been difficult to carry out a test with a simple hardware configuration and a test with high reliability.

An object of the present invention is to perform a highly reliable test with a simple hardware configuration in a test method of a communication IC for inputting an asynchronous character signal and a clock signal from a modem and outputting a synchronous character signal. It is to provide a test method capable of

[0005]

I for communication according to the present invention
The test method of C is the process of simulating the operation of the communication IC to form the first asynchronous character signal, the first clock signal and the first synchronous character signal, and sampling each of the above signals at a predetermined cycle. Forming a first asynchronous character signal sampling signal, a first clock signal sampling signal and a first synchronous character signal sampling signal, and forming a second asynchronous character signal and a second clock signal based on the respective sampling signals , The second asynchronous character signal and the second
Inputting a clock signal to the communication IC to output the second sync character signal from the communication IC, and forming the second sync character signal sampling signal by sampling the second sync character signal at a predetermined cycle. When,
Comparing the first sync character signal sampling signal with the second sync character signal sampling signal.

[0006]

1 is a time chart showing a method of testing a communication IC having an asynchronous / synchronous conversion function. FIG. 2 is a diagram showing a configuration for testing the operation of a communication IC using the method of FIG. The communication IC 11 inputs the asynchronous character signal and the clock signal from the modem and outputs the synchronous character signal, and the synchronous tester 12 tests the operation of the communication IC 11.

The test method will be described below with reference to FIGS. 1 and 2.

In the first process, the operation of the communication IC 11 is logically simulated to generate an asynchronous character signal A1 (first
An asynchronous character signal), a clock signal B1 (first clock signal) and a synchronous character signal C1 (first synchronous character signal) are formed. STA is a start bit, STP is a stop bit, and 1 to N are data bits. Normally, the period Tx for one bit of the asynchronous character signal A1 and the period T for one clock of the clock signal B1
some difference between s and s (eg, Tx = 0.975 × T
s, Tx = 1.01 to 1.023 * Ts.

In the second process, the asynchronous character signal A1, the clock signal B1 and the synchronous character signal C1.
Sampling signal A2 (first asynchronous character signal sampling signal), sampling signal B2 (first clock signal sampling signal) and sampling signal C2 (first synchronizing character) by each sample value series obtained when sampling is performed at a predetermined cycle. Signal sampling signal) is formed. The sampling cycle is the above cycle T
Sufficiently short compared to s and Tx.

In the third step, the sampling signal A2
And each bit of each sample value series of the sampling signal B2 are sequentially connected at the same cycle as the sampling cycle, thereby making the asynchronous character signal A3 substantially the same as the asynchronous character signal A1 and the clock signal B1.
(Second asynchronous character signal) and clock signal B3
(Second clock signal) is formed. That is, the asynchronous character signal A3 and the clock signal B3 are re-synthesized by once sampling the asynchronous character signal A1 and the clock signal B1 and then using a bit pattern having the same cycle as the sampling cycle. .

In the fourth step, the asynchronous character signal A3
And the clock signal B3 is sent from the synchronous tester 12 to the communication IC 11. If the communication IC 11 is normal,
From the communication IC 11, a sync character signal C3 (second sync character signal) that is substantially the same as the sync character signal C1 is output.

In the fifth step, the synchronous tester 12 samples the synchronous character signal C3, and the sampling signal C4 is obtained from each sample value sequence obtained at that time.
(Second synchronization character signal sampling signal) is formed. The sampling cycle at this time is equal to the sampling cycle in the second process.

In the sixth step, the sampling signal C2
And the sampling signal C4 are compared by a comparator in the synchronous tester 12. That is, the sampling signal C
The difference between the sample value series of 2 and the sample value series of the sampling signal C4 is compared. If the two are equal, the communication IC 11 is determined to be a good product, and if they are not equal, it is determined to be a defective product.

As described above, according to the above-mentioned test method, each of the simulation signals has a sampling period sufficiently shorter than the period Tx of one bit of the asynchronous character signal A1 and the period Ts of one clock of the clock signal B1. Are sampled, and the communication IC 11 is tested using each sample value series obtained at that time. Therefore, in the case where the communication IC 11 is tested by variously changing the difference between the period Tx of 1 bit of the asynchronous character signal A1 and the period Ts of 1 clock of the clock signal B1, it is easy to obtain a highly accurate signal. Can be formed.

[0015]

According to the present invention, a test signal for a communication IC having an asynchronous / synchronous conversion function can be formed easily with high accuracy, so that a highly reliable test can be performed with a simple hardware configuration. It becomes possible to do.

[Brief description of drawings]

FIG. 1 is a time chart showing a test method of a communication IC having an asynchronous / synchronous conversion function.

FIG. 2 is a block diagram showing a configuration for testing the operation of a communication IC using the method of FIG.

[Explanation of symbols]

 A1 ... first asynchronous character signal B1 ... first clock signal C1 ... first synchronous character signal A2 ... first asynchronous character signal sampling signal B2 ... first clock signal sampling signal C2 ... first synchronous character signal Sampling signal A3 ... second asynchronous character signal B3 ... second clock signal C3 ... second synchronous character signal C4 ... second synchronous character signal sampling signal

Claims (1)

[Claims] 1. A method of testing a communication IC for inputting an asynchronous character signal and a clock signal from a modem and outputting a synchronous character signal, wherein the operation of the communication IC is simulated to obtain the asynchronous character signal. The corresponding first asynchronous character signal,
A step of forming a first clock signal corresponding to the clock signal and a first sync character signal corresponding to the sync character signal, and a predetermined process of setting the first asynchronous character signal, the first clock signal and the first sync character signal. Forming a first asynchronous character signal sampling signal, a first clock signal sampling signal and a first synchronous character signal sampling signal by sampling at a period of, and the first asynchronous character signal sampling signal and the first clock signal sampling. Forming a second asynchronous character signal substantially the same as the first asynchronous character signal and a second clock signal substantially the same as the first clock signal based on the signal; and the second asynchronous character signal and the second Clock signal for above communication The process of inputting to the C and outputting the second synchronization character signal which is substantially the same as the first synchronization character signal from the communication IC, and the second synchronization character signal is sampled at a predetermined cycle to perform the second synchronization. A method for testing a communication IC, comprising: a step of forming a character signal sampling signal; and a step of comparing the first synchronization character signal sampling signal with the second synchronization character signal sampling signal.