JPH06112585A - Manufacture of submount - Google Patents

Manufacture of submount

Info

Publication number
JPH06112585A
JPH06112585A JP28091392A JP28091392A JPH06112585A JP H06112585 A JPH06112585 A JP H06112585A JP 28091392 A JP28091392 A JP 28091392A JP 28091392 A JP28091392 A JP 28091392A JP H06112585 A JPH06112585 A JP H06112585A
Authority
JP
Japan
Prior art keywords
submount
wafer
coating
manufacturing
coated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28091392A
Other languages
Japanese (ja)
Inventor
Yuji Yoshinaga
祐治 吉永
Chiharu Ishikura
千春 石倉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Kikinzoku Kogyo KK
Original Assignee
Tanaka Kikinzoku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Kikinzoku Kogyo KK filed Critical Tanaka Kikinzoku Kogyo KK
Priority to JP28091392A priority Critical patent/JPH06112585A/en
Publication of JPH06112585A publication Critical patent/JPH06112585A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To obtain a submount excellent in conductive characteristics in which resistance from one side to the other side is lowered while exhibiting sufficient heat dissipation effect by applying a coating on one side of a wafer and then cutting the wafer into band members thereafter applying a coating on the other side. CONSTITUTION:A wafer 1 is sequentially coated 1a, on one side thereof, with Ti, Pt, and Au through sputtering and further coated with Pb-Sn through wet plating. The water 1 is then cut into band members 2 which are subjected to ultrasonic cleaning and subsequently coated, on the other side thereof, with Ti, Pt, and Au through sputtering. Thereafter, the band member 2 is cut into a submount 3. Since the wafer 1 is applied with coating on one side thereof and cut off and then applied with coating on the other side thereof, coating 1c on the other side spreads onto the cutting face, i.e., the side face. Consequently, electrical conduction from one side to the other side is achieved through connection of side faces thus realizing a submount excellent in conductive characteristics and exhibiting sufficient heat dissipation effect.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子部品、特にレーザ
ーダイオードに用いられるサブマウントの製造方法に係
り、詳しくは導電特性に優れたサブマウントの製造方法
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a submount used for an electronic component, especially a laser diode, and more particularly to a method of manufacturing a submount excellent in conductive characteristics.

【0002】[0002]

【従来の技術】従来、サブマウントを製造するには、ウ
ェハーの片面にコーティングした後他面にコーティング
し、次に切断してチップとなしている。
2. Description of the Related Art Conventionally, in order to manufacture a submount, one side of a wafer is coated, then the other side is coated, and then the wafer is cut into chips.

【0003】ところで、かかる従来のサブマウントの製
造方法では、放熱効果に優れ、切断時ばりが出にくく、
温度が上がりにくいウェハーを用いているが、コーティ
ング後切断している為、片面から他面への導電性が悪
く、十分な放熱効果が得られなかった。従って、このサ
ブマウントをレーザーダイオードに用いると、レーザー
特性が劣化した。
By the way, according to the conventional method for manufacturing the submount, the heat dissipation effect is excellent, and burrs are less likely to occur during cutting.
Although a wafer whose temperature does not rise easily is used, since it is cut after coating, the conductivity from one surface to the other is poor, and a sufficient heat dissipation effect was not obtained. Therefore, when this submount was used for a laser diode, the laser characteristics deteriorated.

【0004】この為、片面から他面への結線(ワイヤー
ボンディング)により導電性をカバーしていたが、サブ
マウント製造の工数が増え、生産性が低下していた。
For this reason, although the conductivity is covered by the connection (wire bonding) from one surface to the other surface, the man-hour for manufacturing the submount is increased and the productivity is lowered.

【0005】[0005]

【発明が解決しようとする課題】そこで本発明は、導電
特性に優れたサブマウントの製造方法を提供しようとす
るものである。
Therefore, the present invention is intended to provide a method of manufacturing a submount having excellent conductive characteristics.

【0006】[0006]

【課題を解決するための手段】上記課題を解決するため
の本発明のサブマウントの製造方法は、ウェハーの片面
にコーティングした後切断し、然る後他面にコーティン
グすることを特徴とするものである。
A method of manufacturing a submount according to the present invention for solving the above problems is characterized in that one side of a wafer is coated, then cut, and then the other side is coated. Is.

【0007】[0007]

【作用】上記のように本発明のサブマウントの製造方法
では、ウェハーの片面にコーティングした後切断し、然
る後他面にコーティングするので、この他面のコーティ
ングが回り込んで切断面である側面もコーティングされ
る。その結果、側面の接続により片面から他面への電気
的導通が得られ、導電特性の優れたものとなり、十分な
放熱効果が得られる。
As described above, in the submount manufacturing method of the present invention, one side of the wafer is coated and then cut, and then the other side is coated, so that the coating on the other side wraps around to form a cut surface. The sides are also coated. As a result, electrical connection from one side to the other side can be obtained by the connection of the side surfaces, the conductive characteristics become excellent, and a sufficient heat dissipation effect can be obtained.

【0008】[0008]

【実施例】本発明のサブマウントの製造方法の実施例と
従来例を説明する。先ず第1実施例について説明する
と、図1に示す外径 100mm、厚さ 0.6mmのAlNよりな
るウェハー1の片面にスパッタリング法によりTi1000
Å、Pt2000Å、Au 500Åをコーティング1aし、さ
らにPb−Sn40%を湿式メッキ法により3μmコーテ
ィング1bした。次にこのウェハー1を図2に示すよう
に幅2mmに順次切断して帯材2となした。次いでこの帯
材2をイソプロピルアルコールにより超音波洗浄し、他
面に図3に示すようにスパッタリング法によりTi1000
Å、Pt2000Å、Au 500Åをコーティング1cした。
その後この帯材2を長さ2mmに切断して図4に示すよう
にチップ状のサブマウント3となした後、イソプロピル
アルコールにより超音波洗浄した。
EXAMPLE An example of a method of manufacturing a submount according to the present invention and a conventional example will be described. First, the first embodiment will be described. One surface of a wafer 1 made of AlN having an outer diameter of 100 mm and a thickness of 0.6 mm shown in FIG.
Å, Pt2000Å and Au500Å were coated 1a, and Pb-Sn 40% was further coated to a thickness of 3 μm by a wet plating method. Next, as shown in FIG. 2, this wafer 1 was sequentially cut into a strip 2 having a width of 2 mm. Next, this strip 2 is ultrasonically cleaned with isopropyl alcohol, and Ti1000 is sputtered on the other surface as shown in FIG.
Å, Pt2000Å and Au500Å were coated 1c.
Thereafter, the strip 2 was cut into a length of 2 mm to form a chip-shaped submount 3 as shown in FIG. 4, and then ultrasonic cleaning was performed with isopropyl alcohol.

【0009】次に第2実施例について説明すると、図5
に示す外径 100mm、厚さ 0.6mmのAlNよりなるウェハ
ー1の片面にスパッタリング法によりTi1000Å、Pt
2000Å、Au 500Åをコーティング1aし、さらにPb
−Sn40%を湿式メッキ法により3μmコーティング1
bした。次にこのウェハー1を図6に示すように縦、横
2mmの方形に切断して多数のチップ4を得た。次いでこ
の多数のチップ4をイソプロピルアルコールにて超音波
洗浄し、他面にスパッタリング法によりTi1000Å、P
t2000Å、Au 500Åをコーティングして図7に示すサ
ブマウント5を得た。
Next, the second embodiment will be described with reference to FIG.
On one side of a wafer 1 made of AlN having an outer diameter of 100 mm and a thickness of 0.6 mm shown in FIG.
2000 Å, Au 500 Å coated 1a, then Pb
-Sn 40% coating 3μm by wet plating 1
b. Next, as shown in FIG. 6, this wafer 1 was cut into a rectangular shape having a length and a width of 2 mm to obtain a large number of chips 4. Next, the large number of chips 4 are ultrasonically cleaned with isopropyl alcohol, and the other surface is sputtered with Ti1000Å, P
The submount 5 shown in FIG. 7 was obtained by coating t2000Å and Au500Å.

【0010】最後に従来例について説明すると、図8に
示す外径 100mm、厚さ 0.6mmのSiよりなるウェハー
1′の片面に蒸着法によりTi1000Å、Pt2000Å、A
u 500Åをコーティング1aした。次にウェハー1′の
他面に蒸着法により図9に示すようにTi1000Å、Pt
2000Å、Au 500Åをコーティング1cし、さらにPb
−Sn40%を湿式メッキ法により3μmコーティング1
bした。次いでこのウェハー1′を図10に示すように
縦、横2mmの方形に切断してチップ状のサブマウント6
を得た後、イソプロピルアルコールにより超音波洗浄し
た。
Finally, a conventional example will be described. On one surface of a wafer 1'made of Si having an outer diameter of 100 mm and a thickness of 0.6 mm shown in FIG. 8, Ti1000Å, Pt2000Å, A by a vapor deposition method.
u 500Å was coated 1a. Next, as shown in FIG. 9, Ti1000Å and Pt were deposited on the other surface of the wafer 1'by vapor deposition.
2000 Å, Au 500 Å coated 1c, and Pb
-Sn 40% coating 3μm by wet plating 1
b. Next, as shown in FIG. 10, this wafer 1'is cut into a square with a length and width of 2 mm to form a chip-like submount 6
After being obtained, ultrasonic cleaning was performed with isopropyl alcohol.

【0011】こうして得た第1実施例、第2実施例、従
来例のサブマウントのV(電圧)−I(電流)特性を調
べた処、図11、12、13に示すような結果を得た。
When the V (voltage) -I (current) characteristics of the first, second and conventional submounts thus obtained were examined, the results shown in FIGS. 11, 12 and 13 were obtained. It was

【0012】図11、12、13を比較して明らかなように第
1実施例、第2実施例のサブマウントは、従来例のサブ
マウントよりも著しく抵抗が低く、導電特性に優れてい
ることが判る。とりわけ第2実施例のサブマウントは、
チップに切断した後他面にコーティングしたので、周囲
の四側面にコーティングが回り込み、片面から他面への
電気的導通が極めて良好となった為、第1実施例の二側
面にコーティングが回り込んだサブマウントよりもさら
に抵抗が低く、導電特性が優れたものとなった。
As can be seen by comparing FIGS. 11, 12, and 13, the submounts of the first and second embodiments have significantly lower resistance and superior conductive characteristics than the submounts of the conventional example. I understand. In particular, the submount of the second embodiment is
Since the other side was coated after cutting into chips, the coating wraps around the surrounding four side surfaces, and the electric conduction from one side to the other side becomes extremely good. Therefore, the coating wraps around the two side surfaces of the first embodiment. However, it has lower resistance and better conductivity than the submount.

【0013】尚、上記実施例ではTi、Pt、Auのコ
ーティングに密着力の強いスパッタリング法を用いた
が、蒸着法、湿式メッキ法、乾式メッキ法でも良いもの
である。
In the above embodiment, the Ti, Pt, and Au coatings are formed by the sputtering method having a strong adhesive force, but the vapor deposition method, the wet plating method, and the dry plating method may be used.

【0014】[0014]

【発明の効果】以上の通り本発明のサブマウントの製造
方法によれば、片面から他面への抵抗が低く、導電特性
に優れ、十分な放熱効果が得られるサブマウントを容易
に得ることができる。
As described above, according to the method of manufacturing a submount of the present invention, it is possible to easily obtain a submount having a low resistance from one surface to the other surface, excellent conductive properties, and sufficient heat dissipation effect. it can.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のサブマウントの製造方法の第1実施例
の工程を示す図である。
FIG. 1 is a diagram showing a process of a first embodiment of a method of manufacturing a submount according to the present invention.

【図2】本発明のサブマウントの製造方法の第1実施例
の工程を示す図である。
FIG. 2 is a diagram showing a process of a first embodiment of a method of manufacturing a submount according to the present invention.

【図3】本発明のサブマウントの製造方法の第1実施例
の工程を示す図である。
FIG. 3 is a diagram showing a process of the first embodiment of the method of manufacturing a submount according to the present invention.

【図4】本発明のサブマウントの製造方法の第1実施例
の工程を示す図である。
FIG. 4 is a diagram showing a process of the first embodiment of the method of manufacturing a submount according to the present invention.

【図5】本発明のサブマウントの製造方法の第2実施例
の工程を示す図である。
FIG. 5 is a diagram showing steps of a second embodiment of the method of manufacturing a submount according to the present invention.

【図6】本発明のサブマウントの製造方法の第2実施例
の工程を示す図である。
FIG. 6 is a diagram showing a process of a second embodiment of the method of manufacturing a submount according to the present invention.

【図7】本発明のサブマウントの製造方法の第2実施例
の工程を示す図である。
FIG. 7 is a diagram showing a process of a second embodiment of the method of manufacturing a submount according to the present invention.

【図8】従来のサブマウントの製造方法の工程を示す図
である。
FIG. 8 is a diagram showing steps of a conventional submount manufacturing method.

【図9】従来のサブマウントの製造方法の工程を示す図
である。
FIG. 9 is a diagram showing steps of a conventional submount manufacturing method.

【図10】従来のサブマウントの製造方法の工程を示す図
である。
FIG. 10 is a diagram showing steps of a conventional submount manufacturing method.

【図11】本発明のサブマウントの製造方法の第1実施例
によって得たサブマウントのV−I特性を示すグラフで
ある。
FIG. 11 is a graph showing VI characteristics of a submount obtained by the first example of the method for manufacturing a submount according to the present invention.

【図12】本発明のサブマウントの製造方法の第2実施例
によって得たサブマウントのV−I特性を示すグラフで
ある。
FIG. 12 is a graph showing VI characteristics of a submount obtained according to a second example of the method for manufacturing a submount of the present invention.

【図13】従来のサブマウントの製造方法によって得たサ
ブマウントのV−I特性を示すグラフである。
FIG. 13 is a graph showing VI characteristics of a submount obtained by a conventional submount manufacturing method.

【符号の説明】[Explanation of symbols]

1 ウェハー 2 帯材 3、5 サブマウント 4 チップ 1 Wafer 2 Band material 3, 5 Submount 4 Chip

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 ウェハーの片面にコーティングした後切
断し、然る後他面にコーティングすることを特徴とする
サブマウントの製造方法。
1. A method of manufacturing a submount, which comprises coating one surface of a wafer, cutting the wafer, and then coating the other surface.
JP28091392A 1992-09-25 1992-09-25 Manufacture of submount Pending JPH06112585A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28091392A JPH06112585A (en) 1992-09-25 1992-09-25 Manufacture of submount

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28091392A JPH06112585A (en) 1992-09-25 1992-09-25 Manufacture of submount

Publications (1)

Publication Number Publication Date
JPH06112585A true JPH06112585A (en) 1994-04-22

Family

ID=17631686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28091392A Pending JPH06112585A (en) 1992-09-25 1992-09-25 Manufacture of submount

Country Status (1)

Country Link
JP (1) JPH06112585A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0755074A2 (en) * 1995-07-18 1997-01-22 Tokuyama Corporation Submount

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0755074A2 (en) * 1995-07-18 1997-01-22 Tokuyama Corporation Submount
EP0755074A3 (en) * 1995-07-18 1998-04-01 Tokuyama Corporation Submount

Similar Documents

Publication Publication Date Title
US4394679A (en) Light emitting device with a continuous layer of copper covering the entire header
US5332695A (en) Method of manufacturing semi conductor device mounted on a heat sink
JPH03209896A (en) Semiconductor laser element submount
CN100364189C (en) Semiconductor laser and its producing method
JPH06112585A (en) Manufacture of submount
US3483610A (en) Thermocompression bonding of foil leads
JPH0548213A (en) Sub-mount for semiconductor laser
US4290080A (en) Method of making a strain buffer for a semiconductor device
JPH08125270A (en) Laminated semiconductor laser
JPS6188535A (en) Manufacture of semiconductor device
JPH11204828A (en) Manufacture of light emitting diode
JPH1131601A (en) Chip part and manufacture thereof
KR100277938B1 (en) Compound Semiconductor Laser Diode and Manufacturing Method Thereof
KR100282177B1 (en) Bonding structure of laser diode
JPS63107012A (en) Electronic component
JPH07111897B2 (en) Method of connecting electrode formed on conductive film and lead wire
KR0149129B1 (en) Method of packaging laser diode transmission module
JPS5998566A (en) Heat sink
JPH02156606A (en) Connection structure of lead wire
JPH09116090A (en) Power semiconductor module
JPH05343578A (en) Semiconductor device and manufacture thereof
JPS6394640A (en) Manufacture of semiconductor element
JPS5966182A (en) Manufacture of semiconductor device
JP2559524Y2 (en) Positive characteristic thermistor device
JPS6118190A (en) Semiconductor laser device