JPH06112447A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive an increase in the integration of fundamental cells, which are arranged on a substrate in the form of matrix, and an increase in the reliability of the fundampental cells in a gate array formed using a CMOS semiconductor. CONSTITUTION:P-type source regions 2 and N-type drain regions 5 are formed on a substrate, P-channel and N-channel MOS transistors are respectively formed at parts, which cross the regions 2 and 5, of a polysilicon wiring 3 and fundamental cell rows are constituted. A plurality of wiring layers 3, 7, 7a, 7b and 9 are provided over the fundamental cell rows and the lowest wiring layer of the wiring layers is used as the wiring 3 which is connected to the regions 2 and 5 and a gate electrode via contact holes 6.

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a CMOS (complementary MO
S) The present invention relates to a structure of basic cells arranged in a matrix on a substrate in a gate array using a semiconductor. 2. Description of the Related Art Conventionally, as shown in FIG. 8, a device of this type has a structure in which 2 P-type source / drain regions and 5 N-type source / drain regions are crossed by 3 polysilicon regions. The basic cells are arranged in a matrix on the semiconductor substrate. In this case, 10 is an N-type channel stopper region, 11 is a P-type channel stopper region, 16
Is a P-well. Reference numerals 7, 7a, 7b are first-layer metal wirings, and 6 is metal wirings, polysilicon and P.
And N-type source / drain regions are connected to each other. In the metal wiring of FIG. 8, 7a is a plus side power source line and 7b is a minus side power source line. The central P-type transistors are connected in series and the N-type transistors are connected in parallel by metal wiring. FIG. 4 is a transistor circuit diagram equivalent to FIG. As can be seen from this figure, FIG.
Wiring is performed so as to form an R gate. In FIG. 8, polysilicon 3 running laterally on the upper and lower sides of the basic cell is a signal line for passing a signal across the inside of the cell. This signal line is used, for example, when the terminal 501 from the cell A and the terminal 502 from the cell B shown in FIG. The conventional technique has the following problems because the above-described basic cell structure is general. When an electric signal passes in the lateral direction of FIG. 8, the resistance of polysilicon and the resistance of polysilicon and P
Type or N-type source / drain capacitance has the drawback of increasing the propagation delay time of an electric signal. Therefore, even when the basic cells are arranged in a matrix, the circuit scale is restricted if the semiconductor device requires a high operation speed. For example, as described in JP-A-54-93375, the second or more wiring layers of a plurality of wiring layers are used for the wirings connected to the source / drain regions and the gate electrodes through the contact holes. If so, the step between the wirings becomes large, and there is a risk of disconnection. SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and a MOS forming a basic cell is formed.
In a transistor (FET), by using the lowermost wiring layer of a plurality of wiring layers for the wiring connected to the source / drain region and the gate electrode through a contact hole, By interposing the first wiring layer, it is attempted to reduce the step difference between the wirings, increase the degree of freedom of the wirings of the second and higher layers, and achieve higher integration, high reliability, and high speed. It is a thing. The present invention provides a semiconductor device having a plurality of basic cell rows formed in a row in a first direction on a semiconductor substrate of a first conductivity type, Each of the basic cells in the basic cell row includes a second conductive type source / drain region formed in a first conductive type region in the semiconductor substrate, a first transistor having a gate electrode, and the semiconductor substrate. A source / drain region of the first conductivity type formed in a region of the second conductivity type therein, and a second electrode having a gate electrode
Transistors are arranged adjacent to each other in a second direction substantially orthogonal to the first direction, a plurality of wiring layers are provided above the basic cell row, and the bottom wiring layers of the plurality of wiring layers are in contact with each other. It is characterized by being used for a wiring connected to the source / drain region and the gate electrode through a hole. The second-layer wiring of the plurality of wiring layers is the second wiring.
And can be connected to the wiring of the lowermost wiring layer. According to the present invention, a plurality of wiring layers are provided above the basic cell row, and the lowermost wiring layer of the plurality of wiring layers is connected to the source / drain region or the above through the contact hole. By using it for the wiring connected to the gate electrode, the step difference between the wirings can be reduced, and the degree of freedom of the wirings of the second or higher layer can be increased. FIG. 7 is a plan view of a basic cell of the present invention,
2 is a P-type source / drain region, 5 is an N-type source / drain region
The drain region 3 is polysilicon. The intersections of the source / drain regions 2 and 5 and the polysilicon 3 are P-channel and N-channel MOS, respectively.
Forming a transistor. Reference numeral 1 denotes an N-type high impurity concentration region, 4 denotes a P-type high impurity concentration region, which are P-type source / drain regions 2 and N of the basic cell, respectively.
The source / drain region 5 of the mold is surrounded from three directions. Reference numeral 10 is an N type, 11 is a P type channel stopper region, and 16 is a P well. FIG. 1 shows an embodiment in which wiring is provided on top of FIG. 7, and the equivalent circuit is a 2-input NOR circuit as shown in FIG.
Wiring is performed so as to form a gate.
Reference numerals 7, 7a and 7b are first-layer metal wirings, and 9 is a second-layer metal wiring. 6 is a metal wiring of the first layer, P-type and N-type source / drain regions, a high impurity concentration region, and
Reference numeral 8 is a contact for connecting the gate electrode, and reference numeral 8 is a through hole for connecting the first-layer metal wiring and the second-layer metal wiring. The source / drain region and the gate electrode are connected to the metal wiring of the first layer through the contact hole, and the source / drain region and the gate electrode are directly connected to the wiring of the second layer or more. There is no concern about disconnection that may occur when there are large steps. In this embodiment, two layers of metal wiring are used to form two
An input NOR gate is configured, the input terminal A1 is a positive power supply line VDD, and the input terminal A2 is a negative power supply line V.
Although connected to SS, it is connected to the power supply line through the high-impurity concentration region 1 or 4 surrounding the first-layer metal wiring 7 and the basic cell. Therefore, since the high impurity concentration regions 1 and 4 are connected to the power supply potential, it is possible to stabilize the potential fluctuation of each substrate and the well, prevent malfunction of the transistor, and stabilize the operation. The portions of the high-impurity regions 1 and 4 shown in the vertical direction are arranged in parallel with the power supply line and are connected to the power supply line, thereby shunting the power supply current. Basically, the input cells of A1 and A2 can be arbitrarily selected from two power supply lines VDD and VSS because the basic cell is symmetrical. FIG. 2 is a sectional view of the P-channel transistor of FIG. 1 seen in the direction of the power supply line VDD, and FIG. 3 is a sectional view of FIG.
FIG. 5 is a cross-sectional view of the N-channel transistor of FIG. 6 when viewed in the power supply line VSS direction. Reference numerals 1 to 11 and 16 in the figure
Means the same as in FIG. Reference numeral 12 is an oxide film, 13 is a gate oxide film, and 14 and 15 are insulating films for insulating metal wiring. Of the second-layer metal wirings 9 in FIG. 1, the metal wirings running in the horizontal direction above and below the basic cell correspond to the polysilicon wirings running in the horizontal direction described in the basic cell of FIG. is there. Further, in the embodiment of FIG. 1, all the electric signals running in the lateral direction use the second layer metal wiring. The conventional basic cell shown in FIG. 8 is used by dropping the input terminal to the power supply line (this is generally done by dropping one terminal of, for example, a 10-input NAND gate circuit to a positive power supply and a 9-input NAND cell). This is the case where it is used as a gate. By doing this, it is possible to reduce the number of types of logic function blocks created by wiring on the basic cell, and to facilitate library management of function blocks). If the logic function block (2-input NOR gate) wired on the basic cell is handled as a black box, the handling as shown in FIG. 6 becomes difficult, and the processing of the input terminal cannot be performed outside the black box. In other words, the wiring on the basic cell could not be made into a black box. When an electric signal passes in the horizontal direction of FIG. 8, the resistance of polysilicon and the capacitance between the polysilicon and the P-type or N-type source / drain increase the propagation delay time of the electric signal. It had drawbacks. On the other hand, in the embodiment, since the structure is as described above, even if an electric signal is passed in the lateral direction like the conventional basic cell shown in FIG. It is possible to reduce the delay of a signal, which is disadvantageous in terms of circuit characteristics due to resistance and capacitance when passing through the N-type and N-type source / drain regions. Regarding the power supply line, in the embodiment shown in FIG.
Since the plus side has the N-type high impurity concentration region 1 and the minus side has the P-type high impurity concentration region 4 in parallel with the first-layer metal wiring, the power supply current may be bypassed using this region. it can. Since it did in this way, the metal wiring of the 1st layer for power supplies may be the same as a general signal line like before, and does not need to be larger than a signal line. Therefore, the degree of integration can be further improved. Furthermore, since the power supply line of the first layer can be connected to the high-concentration impurity regions 1 and 4 below the metal wiring of the second layer which extends above and below the basic cell in the lateral direction, in other words, By doing so, since it is possible to connect the power supply line to the substrate in units of basic cells, it is possible to stabilize the substrate potential of the MOS transistors in each basic cell and to take measures against latch-up peculiar to CMOS, which makes the IC more reliable. Can be converted. Next, the processing of the input terminal will be described.
The basic cell of FIG. 1 has a structure in which a logic circuit formed on the basic cell can be made into a black box as shown in FIG. When the actual pattern shown in FIG. 1 is symbolized, it can be seen that the processing of the input terminal is performed outside the black box. By considering the outer region as a wiring region, the wiring work of the entire IC can be replaced with the wiring work between the black boxes. As is apparent from the above description, according to the present invention, in a semiconductor device having a basic cell row formed in a row in one direction on a semiconductor substrate, a basic cell row is formed above the basic cell row. By providing a plurality of wiring layers and using the lowermost wiring layer for the wiring connected to the source / drain regions and the gate electrodes of the transistors in the basic cell through the contact holes, the level difference of the wiring is reduced and the disconnection A worry-free semiconductor device with high integration and high reliability can be provided. Further, since the wiring connecting the source / drain regions can be formed on the lowermost wiring layer, the signal wiring can be freely arranged on the lowermost wiring on the basic cell. For example, the signal wiring that crosses the basic cell can be passed over the basic cell without being bothered by the connection wiring in the basic cell, and the degree of freedom of the wiring layer is improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing wiring on a basic cell of an embodiment of a semiconductor device of the present invention. FIG. 2 is a sectional view taken along the power supply line VDD in FIG. 3 is a cross-sectional view taken along the power supply line VSS in FIG. FIG. 4 is an equivalent circuit diagram showing a method of connecting the constituent elements of FIGS. 1 and 8. FIG. 5 is an explanatory diagram of a case where a wiring passes in a cell in a lateral direction. FIG. 6 is an explanatory diagram showing the plan view of FIG. 1 as a symbol diagram. FIG. 7 is a plan view of an example of a basic cell of a semiconductor device of the present invention. FIG. 8 is a plan view of a conventional semiconductor device. [Explanation of symbols] 1,4 high impurity concentration region 2,5 source / drain region 3 polysilicon 6 contacts 7, 7a, 7b first layer metal wiring 8 through hole 9 second layer metal wiring 10, 11 channel stopper 12 oxide film 13 gate oxide films 14 and 15 insulating film 16 well

Claims (1)

Claims: (1) In a semiconductor device having a plurality of basic cell rows formed in a row in a first direction on a semiconductor substrate of a first conductivity type, each of the basic cell rows The basic cell is a source of the second conductivity type formed in a region of the first conductivity type in the semiconductor substrate.
A first transistor having a drain region and a gate electrode, and a second transistor having a first conductivity type source / drain region and a gate electrode formed in a region of the second conductivity type in the semiconductor substrate, The plurality of wiring layers are arranged adjacent to each other in a second direction which is substantially orthogonal to the first direction, and the plurality of wiring layers are provided above the basic cell row, and the lowermost wiring layer of the plurality of wiring layers is provided via contact holes. A semiconductor device, which is used for a wiring connected to a source / drain region and the gate electrode. (2) The wiring of the second layer of the plurality of wiring layers is arranged in the second direction and is connected to the wiring of the lowermost wiring layer. Semiconductor device.