JPH06112426A - Memory, its information read-out method, and information writing method - Google Patents

Abstract

PURPOSE:To provide a memory having a small area and composed of the number of elements as small as possible, its information read-out method and information writing method. CONSTITUTION:A row-address signal wire Ax, a pair of column address signal wires Ay 1 and Ay 2, a stand-by signal wire Sb, and a memory cell MC, which is provided on the crossing part between the row-address signal wire Ax and the column address wires Ay 1 and Ay 2, are provided on the title memory storage. The above-mentioned memory cell MC consists of a double-emitter construction transistor Tr, having a collector electrode C and two emitter electrodes E1 and E2 and also having negative differential characteristics and threshold value performance, and a gate G which controls the base current of the above-mentioned transistor Tr. One of the emitter electrodes E1 is connected to one of the Ay 1 of the column address signal wires other than the emitter electrode E2 is connected to the other Ay 2 of the column address signal wire, the collector electrode C is connected to the row-address signal wire Ax, and the gate G is connected to the stand-by signal wire (Sb).

Description

Detailed Description of the Invention

[0001]

The present invention relates to an SRAM (Static Ran)
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device suitable for a dom Acces Memory, etc., and more specifically, a RHET (Resonant-tunneling Hot Ele) having negative differential characteristics and threshold characteristics as memory cells.
ctron Transistor; resonance tunneling hot electron transistor) and RBT (Resonance Bipolar Tr)
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device using a transistor such as an anistor (resonance tunneling bipolar transistor), an information reading method and an information writing method thereof.

2. Description of the Related Art In recent years, the scale of semiconductor memory has increased, and today 64 Mb DRAMs (Dynamic Random Acces Mem) are used.
ory) and 16 Mb SRAMs are being developed.
However, the current memory cell structure has a limitation in increasing the density, and it is desired to develop a new semiconductor memory cell capable of increasing the density.

[0003]

2. Description of the Related Art Generally, a DRAM memory cell is composed of a capacitor using a junction capacitance of an FET (Field Effect Transistor) for storing information and an FET for writing and reading information to and from the capacitor. The SRAM has a flip-flop type memory cell structure, and is normally configured by using six FETs.

[0004]

As described above, the SRA
The memory cell of M requires an area of at least 6 FETs, and there is a limit in promoting miniaturization. An object of the present invention is to provide a memory device including a novel memory cell that can be configured with a smaller number of elements and a small area, an information reading method thereof, and an information writing method thereof.

[0005]

In order to solve the above-mentioned problems, a memory device according to a first aspect of the present invention has a row address signal line (Ax) and a pair of column addresses as shown in FIG. Signal lines (Ay1, Ay2) and standby signal lines (S
b) and a memory cell (MC) provided at the intersection of the row address signal line (Ax) and the column address signal line (Ay1, Ay2), the memory cell (MC) being
A transistor (Tr) having a double-emitter structure having one collector electrode (C) and two emitter electrodes (E1, E2) and exhibiting negative differential characteristics, and a base current of the transistor (Tr) depending on an applied voltage. And a gate (G) for controlling the transistor, and the transistor (Tr)
One emitter electrode (E1) is connected to one (Ay1) of the column address signal lines on the low potential side, and the other emitter electrode (E2) is the other (Ay2) of the column address signal lines on the high potential side. ), The collector electrode (C) of the transistor (Tr) is connected to the row address signal line (Ax), and the gate (G) is connected to the standby signal line (Sb). It is configured.

According to a second aspect of the present invention, as shown in FIG. 2, in the memory device according to the first aspect, one of the column address signal lines (Ay1, Ay2) is connected to one of the address signal lines. It is configured as a common ground wiring (GND). The invention according to claim 3 is, as shown in FIG. 15, a row address signal wiring layer (Ax), a column address signal wiring layer (Ay1, Ay2) arranged in parallel in a pair of two, and the column address. A standby signal wiring layer (Sb) arranged in parallel to the signal wiring layers (Ay1, Ay2), the row address signal wiring layer (Ax) and the column address signal wiring layer (Ay1, Ay2)
The row address signal wiring layer (Ax) and the column address signal wiring layer (Ay1, Ay2) facing each other at the intersection with
And a memory cell (MC) sandwiched between the memory cell layer and the memory cell layer, and the memory cell layer (MC) has a predetermined threshold voltage (Vth).
A collector-base junction layer (D3) having a threshold characteristic for flowing a current is formed by electrically contacting one surface thereof with the row address signal wiring layer (Ax).
Two base-emitter junction layers (D1, D2) having a negative differential characteristic are electrically connected in parallel between the other surface of the base junction layer (D3) and the column address signal wiring layers (Ay1, Ay2). A standby electrode wiring layer, which is formed in a laminated shape so as to contact with the gate electrode and controls a current flowing in the base-emitter junction layers (D1, D2) by expanding and contracting a depletion layer by a predetermined applied voltage. It is characterized in that it is formed in electrical contact with (Sb).

The invention described in claim 4 is the information reading method of the memory device according to claim 1, as shown in FIGS. 9 and 10, and at the time of reading the memory information of the memory cell (MC). , The other operation stable point (S2) of the two base-emitter junctions (D1, D2) of the memory cell (MC).
Where Vs2 is the voltage at the unstable point (Sm), Vsm is the voltage at the row address signal line (Ax), and Vth is the threshold voltage at the base-collector junction (D3). Vsm <VAx + Vth <Vsm, so that
Low-level potential (Low) on the row address signal line (Ax)
And a high level potential (High) is applied to the other (Ay2) of the column address lines, and a depletion layer is expanded and contracted from the gate (G) to flow into the two base-emitter junctions (D1, D2). In order to increase the current, a positive or zero potential is applied to the standby signal line (Sb) to maintain the storage state before and after reading the storage information of the memory cell (MC). It is characterized in that a negative potential is applied to the standby signal line (Sb) so that the depletion layer expands and contracts to reduce the current flowing through the two base-emitter junctions (D1, D2).

The invention described in claim 5 is based on FIG. 11 to FIG.
2. A method for writing information in a memory device according to claim 1, wherein the memory cell is formed by two base-emitter junction layers (D1, D2) of the memory cell (MC).
At the time of writing information to the stable point (S1) on the negative side among the two stable points and the unstable point, the voltage VAx of the row address signal line (Ax), the threshold voltage Vth of the base-collector junction (D3) and the anxiety Fixed point voltage Vsn is VAx + V
A low level potential (Low) is applied to the row address signal line (Ax) so that th <Vsn, and a high level potential (High) is applied to at least one of the column address signal lines (Ay2). , A positive or zero potential is applied to the standby signal line (Sb) so that the depletion layer expands and contracts from the gate (G) to increase the current flowing through the two base-emitter junction layers (D1, D2). , When writing information to the positive stable point (S2) of the operation stable points, the row address signal line (Ax) is set to a high level so that the negative stable point does not occur among the two stable points. A potential (High) is applied and a predetermined potential is applied to the column address signal line, and the depletion layer is expanded and contracted from the gate (G) to cause the two base-emitter junction layers (D1, D) to expand and contract.
2) A positive or zero potential is applied to the standby signal line (Sb) so as to increase the current flowing through it, and writing to the negative or positive stable points (S1, S2) of the two operation stable points. At the time of standby for holding the later memory state, the standby signal line (Sb) is set so that the depletion layer is expanded and contracted from the gate (G) to reduce the current flowing through the two base-emitter junction layers (D1, D2). ) Is applied with a negative potential.

According to a sixth aspect of the invention, as shown in FIG. 19, a row address signal line group (Ax consisting of a plurality of signal lines is provided.
1, Ax2, ...) and the row address signal line group (Ax1, Ax)
2, ...) A column address signal line group (Ay11, Ay12, ..., Ay21, consisting of a pair of signal lines arranged in a direction intersecting
Ay22, ...) and the column address signal line group (Ay11, A
y12, ..., Ay21, Ay22, ...) Standby signal line group (Sb1, Sb2) consisting of a plurality of signal lines arranged in parallel with y12 ,.
, ...) and the row address signal line group (Ax1, Ax2,
...) and the column address signal line group (Ay11, Ay12, ...,
Ay21, Ay22) A row address decoder for supplying a row address signal to a plurality of memory cells (MC) according to claim 1 provided at each intersection and row address signal line groups (Ax1, Ax2, ...). (1), a column address decoder (2) for supplying a column address signal to the column address signal line group (Ay11, Ay12, ..., Ay21, Ay22, ...) And a row address signal line group (Ax1, Ax2, ... Sense circuit (3) for detecting information stored in each memory cell (MC) from
And are provided.

[0010]

According to the first aspect of the present invention, the bistable structure is achieved by the characteristics of the two base-emitter junction layers D1 and D2 having the negative differential characteristics in the transistor (Tr) of the double emitter structure which constitutes the memory cell. The state is realized. Row address signal line Ax and column address signal line Ax
Even if the voltage signals are separately applied to 1 and Ax2, respectively, the bistable state is not broken and there is no current flowing through the base-collector junction layer D3 having the threshold characteristic.

However, each address signal line Ax, Ay1, A
When a predetermined voltage signal is applied to the respective lines of y2 at the same time, a stable state, that is, a current flowing through the base-collector junction layer D3 having a threshold characteristic according to the memory state is generated, and the stable state is changed to another state. It becomes possible to switch to a stable state. That is, this circuit is used as a memory cell vertically,
It is possible to configure a memory device capable of selectively writing information to and reading information from only a specific memory cell when the memory devices are arranged side by side in parallel.

Further, depending on the voltage applied to the gate G, 2
By controlling the currents flowing through the two base-emitter junction layers D1 and D2, it is possible to reduce the power consumption in the standby mode for holding the memory state and increase the speed of writing and reading information. According to the invention described in claim 2, by providing the common ground wiring GND, the address signal line can be shared, and the signal line becomes thick, so that it is possible to realize a memory resistant to power supply noise. .

According to the third aspect of the present invention, the stacked memory is sandwiched between the row address signal wiring layer (Ax) and the pair of column address signal wiring layers (Ay1, Ay2) intersecting each other. A cell can be configured, and the memory cell is realized by the sum of the area of two diodes, the area of the gap for separating the two diodes, and the area of the gate electrode provided around the two diodes. can do. Further, the row address signal line Ax, the column address signal line Ay1,
By arranging Ay2 so as to intersect with each other and arranging the memory cells between them, an area other than the arrangement of the memory cells is not necessary, that is, an area other than the area of the memory cells themselves and the area of the gap between the memory cells is not necessary. Memory cells can be arranged in high density without the need.

According to the invention of claim 4 or 5,
There are two stable points S1 and S with any combination of address signals.
It is possible to read and write any stored information with respect to 2. At the time of reading and writing, a positive or zero potential is applied to the gate G,
To reduce the extension of the depletion layer from the base-emitter junction layer D
By increasing the currents flowing through 1 and D2, the read and write speeds can be increased.

In addition, at the time of standby in which the memory state is maintained before and after reading the memory information or after the memory information is written, a negative potential is applied to the gate G, the depletion layer is extended from the gate G and flows to the base-emitter junction layers D1 and D2. By reducing the current, it is possible to reduce power consumption. According to the invention of claim 6, the memory cell MC of claim 1 is arranged at each intersection of the address signal lines arranged in a matrix in the matrix direction, and the row address decoder and the column address decoder are used. The stored information can be written in the specific memory cell MC selected, and the stored information can be read out through the sense circuit.

Further, a predetermined standby signal is supplied to a standby signal line arranged in parallel with the column address signal line to reduce the power consumption in the standby state for holding the memory state in the memory cell MC, and in the reading or writing. It is possible to increase the speed. That is, by integrating each element of the present invention, a higher density SRAM can be realized.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described with reference to the drawings. [I] Memory Cell MC (i) Circuit Configuration of Memory Cell MC As shown in FIG. 1, the row address signal line A is arranged in the row direction (X).
x is arranged, two pairs of column address signal lines Ay1 and Ay2 are arranged so as to intersect with the row address signal line Ax, and a standby signal line Sb is arranged in parallel to these column address signal lines Ay1 and Ay2. ing.

A memory cell MC is provided on the column address signal line Ay1.
The emitter E1 of the transistor Tr is connected to the column address signal line Ay2, and the second emitter E2 is connected to the column address signal line Ay2. The collector C is connected to the row address signal line Ax. A gate G that controls the base current of the transistor Tr is connected to the standby signal line Sb. Therefore, the transistor Tr and the gate G form a memory cell MC.

The transistor Tr has a double emitter structure, and an element having a resonant tunnel structure such as RHET or RBT is used. Here, the base-first emitter junction BE1 is D1, and the base-second emitter junction BE2 is
Will be described below, and the base-collector junction will be described as D3. In FIG. 2, one of the column address lines Ay1 is connected to the ground potential G.
An example in which the column address line Ay1 is shared as an ND is shown.

(Ii) Operating Principle of Memory Cell FIG. 3 shows the base current-voltage characteristics of the RHET with the emitter grounded. Here, FIG. 3A shows the standby signal line S.
This is the case where no voltage is applied to b, that is, when the gate G has a potential of 0 and the currents flowing in the base-emitter junction layers D1 and D2 are not changed, and FIG. If a negative voltage of
That is, the gate G has a negative potential, and the current flowing in the base-emitter junction layers D1 and D2 is reduced by the extension of the depletion layer from the gate G.

The peak current is defined as Ip, the valley current is defined as IV, the rising voltage is defined as Vth, the peak voltage is defined as Vp, the valley voltage is defined as Vv, and the voltage at which the same current as the peak current flows again is defined as Vp2. A suffix + is added to the positive direction of the base potential and a suffix of − is added to the negative direction. On the other hand, the base-collector current-voltage characteristic of RHET is shown in FIG. When the voltage exceeds the threshold value Vth, the current suddenly flows.

Next, the operation principle of the memory cell will be described with reference to FIGS. In this case, in order to make the explanation easy to understand, it is assumed that the gate G has a potential of zero. Figure 5
(A) and (b) show the base voltage dependence of the base current when the emitter of the RHET is grounded. Here, −Ie is a current due to electrons injected from the emitter (negative is added when the current is changed), and Ib → e is a component (current that loses energy at the base of electrons injected from the emitter to the base and becomes a base current). Direction from base to emitter), Ic
→ e is the component of the electrons injected from the emitter to the base that reaches the collector to become the collector current (collector to emitter in the direction of current), Ib → c is the base current due to the electrons flowing from the collector to the base through the collector barrier (From the base to the collector in the direction of current). Therefore, the base current Ib = Ib → e + Ib → c.

When the potential of the collector is lower than the rising voltage (collector-emitter voltage at which the collector current flows when the emitter is grounded), all the electrons injected from the emitter flow to the base, and the result is as shown in FIG. 5 (a). If the potential of the collector is higher than the rising voltage Vv, some of the electrons injected from the emitter reach the collector and become a current, so the current-voltage characteristic of the base is as shown in FIG. 5 (b).

As shown in FIG. 6A, the two emitters E1,
Address signal lines Ay1 (E1 side) and Ay2 (E2 side) on E2
Connect. When a voltage is applied between both address signal lines, there is one stable point until the applied voltage is 2 Vp (FIG. 6 (b)). However, when a higher voltage is applied, there are two stable points (S1, S2) and one unstable point (S1).
n) appears (FIG. 6 (c)). S1 is the first emitter E
The voltage applied between 1 and the base is lower than the peak voltage.
When the voltage applied between the emitter E2 and the base B is higher than the valley voltage, S2 is the opposite, and it can be memorized by which one of these two stable points.

As shown in FIG. 7A, in addition to FIG. 5A, the address signal line Ax is connected to the collector, and the voltage VAx, VAy1, VAy2 is applied to each address signal line Ax, Ay1, Ay2. 7 (b) (c) (d) and FIGS. 8 (a) (b), the current Ib → e1 flowing from the base to the first emitter E1 and the second emitter E2 from the base to the potential of the base at that time. FIG. 6 is a diagram showing a current Ie2 → b flowing and a current Ib → c flowing from the collector to the base (current Ic → e1 flowing from the collector to the emitter 1 is also shown for reference). Since the base current must be 0, the operating point is Ib → e1 = Ie2 → b + Ic → c.

FIG. 7 shows that when VAx <VAy1 + Vr, that is, when the collector potential is lower than the first emitter potential and the transistor does not operate, and FIG. 8 shows when VAx> VAy1 + Vr, that is, when the collector potential is higher than the first emitter potential and the transistor operates. And Vy1 <Vy2. Figure 7
(B) is a characteristic diagram in the memory holding state, where VAx + Vth> V
s2, indicating that there are two stable points and no current flows through the collector. FIG. 7C shows a stable point S2.
In the characteristic diagram when reading whether or not information is written in, Vsn <VAx + Vth <Vs2, there are two stable points, and when the stable point is S2, current flows to the collector, but the stable point is It shows that no current flows in the collector at S1.

FIG. 7 (d) is a characteristic diagram when information is written in the stable point S1. When VAx + Vth <Vsn, there is only one stable point, and the stable point is the voltage applied between the emitter E1 and the base. Indicates that it has the same property as S1 because it is lower than the peak. As described above, information is held, stable point S2 is read out and stable point S1 is read.
Can be written to.

On the other hand, the writing of S2 is performed by writing S1 of FIG.
If the writing of is applied, D3 has a positive side threshold voltage, but does not have a negative side threshold voltage (or even if it has a very low threshold voltage). As far as it can be seen, it seems that S2 cannot be written only by increasing VAx, but when VAx is increased, the memory cell operates as a transistor, so the characteristic changes from FIG. 7 to FIG.

The state shown in FIG. 8A is the first emitter E.
The current flowing from 1 flows out to the collector C and also partially to the second emitter E2. When the level VAx of Ax is not raised so much, there are still two stable points and writing cannot be performed.
FIG. 8 (b) is a characteristic diagram when the potential VAx of Ax is further raised. As the potential VAx is raised, the gain is improved, so that VAx> VAy1 + Vr and there is only one stable point S2. The stable point indicates that the voltage applied between the emitter E2 and the base is lower than the peak and has the same property as S2.

(Iii) Storage and retention of information At the time of retention, the state shown in FIG. Since the power consumption can be suppressed if the current does not flow as much as possible,
It is desirable to have two stable points in the valley.
Incidentally, in order to suppress the power consumption at the time of recording and holding, in this embodiment, the memory cell MC is provided with the gate G, but the details thereof will be described later (vi) after the description of the physical structure of the memory cell. Describe.

(Iv) Reading of Information Since the reading operation must read only the memory cell at the intersection of a certain address signal line Ax and Ay among the memory cells arranged in a matrix.
When the signal is applied to only Ay and when the signal is applied only to Ay, in the state of FIG.
The state of (b) must be obtained.

Here, adding a signal means changing the potential of the address signal line. At this time, when the thresholds are different between + and −, an offset that sets the intermediate potential to 0 may be considered in the following description, so a symmetrical characteristic will be considered in the description. Therefore, S2
At the time of reading, Ax is Low and Ay1 and Ay2 are High so that Vsn <VAx + Vth <Vs2. When Ax is set to Low, the potential of Ax + Vth2 drops. On the other hand, when Ay1 and Ay2 are set to High, the potential of Vs2 rises. The magnitude of the signal at that time is still VAx + Vth> Vs2 in the case of only one, that is, the state of FIG. 7B, and when both are added, Ax + Vth <Vs2, that is, the state of FIG.
If the state of (c) is determined, only the crossing points of both address signal lines Ax and Ay (Ay1, Ay2) will be read. In FIG. 9, (a) is Ax
When only Low is added to (x), when (b) is high only to Ay1 and Ay2, (c) is to Low, Ay1,
It shows the time when High is added to Ay2.

As shown in FIG. 10, (Ax: Low,
Instead of Ay1, Ay2: High, (Ax: Low,
Even with the combination of Ay2: High), the potential can be set so as to satisfy the above condition. In the above description, the initial state of the read operation is the same as the holding state. (This is because the holding state is normally set to suppress the power consumption most, and it is not necessary to set another potential.)
However, as long as the above conditions are satisfied,
The initial state does not have to be the same as the hold state. In the structure of the present invention, S3 cannot be read because D3 has a negative threshold voltage.

(V) Writing of information Since the writing operation must be performed only in the memory cells arranged in a matrix form at the intersections of certain address signal lines Ax and Ay, Ax
FIG. 7 (b), (c) or FIG. 8 (a) when a signal is applied to only Ay and when only a signal is applied to Ay. It must be in the state of 8 (b).

Here, adding a signal means changing the potential of the address signal line. At this time, when the thresholds are different between + and −, an offset that sets the intermediate potential to 0 may be considered in the following description, so a symmetrical characteristic will be considered in the description. In writing S1, Low is added to Ax and High is added to Ay1 and Ay2. When Ax is set to Low, the potential of VAx + Vth drops. On the other hand, when Ay2 is set to High, the potential of Vsn rises. The magnitude of the signal at that time is still VAx + Vth> Vsn, that is, the state of FIG. 7 (b) or (c) when only one is present, and when both are added, Ax + Vth <Vsn, that is, FIG.
If it is decided to be in the state of (c), there will be only one stable point at the intersection of both address signal lines Ax and Ay (Ay1, Ay2), and the stable point is the voltage applied to D1. Since it is lower than the peak, it has the same properties as S1. If both address signal lines are returned to the original holding state, the stable point becomes S1 and S1 can be written.

In FIG. 11, (a) shows a case where Low is added only to Ax, (b) shows a case where High is added to Ay1 and Ay2, and (c) shows Low to Ax and High to Ay1 and Ay2. It shows the time of addition. As shown in FIG. 12, (Ax:
Instead of Low, Ay1, Ay2: High, (Ax:
Similar conditions can be set even with a combination of Low, Ay2: High). Although not shown in the figure, similar conditions can be set with a combination of (Ax: Low, Ay1: High) depending on the characteristics.

In writing S2, Ax is High,
Add Low to Ay1 and Ay2. Even if only Ax is high, only Ay1 and Ay2 are low, VAx <VAy1 + Vr, that is, FIG. 7 (b) or VAx> VAy1 + Vr, the gain is not so large (electrons injected from the emitter 1 do not reach the collector so much). When there are two stable points, that is, as shown in FIG. 8A, when Ax is High and Ay1 is Low, VAx> VAy1 + Vr and the gain is large, and there is one stable point. Ax High so that it becomes the normal state, that is, the state as shown in FIG. 8 (b).
If you decide the Low level of Ay1 and Ay2 of
Only the intersection of Ay and Ay can be rewritten as S2.

In FIG. 13, (a) is high only for Ax.
When (b) adds Low only to Ay1 and Ay2, (c) shows High to Ax and Low to Ay1 and Ay2.
It shows the time when. As shown in FIG. 14, (A
x: (High, Ay1, Ay2: Low) instead of (Ax
: High, Ay1: Low) can be set to satisfy the above condition. Although not shown in the figure, depending on the characteristics, (Ax: High, Ay2: L
ow) and (Ax: High, Ay1: High), the potential can be set to satisfy the above condition.

In the above description, the initial state of the write operation is the same as the holding state. This is because the holding state is normally set to suppress the power consumption most, and it is not necessary to set another potential. However,
The initial state does not have to be the same as the holding state, as long as the above conditions are satisfied. In addition, the writing of information,
For each of the memory cells, S1,
You can write to S2. First, write all memory cells to S2.
It may be written in (S1).

(Vi) Physical Structure of Memory Cell FIG. 15 shows a three-dimensional structure of the memory cell. As shown in FIG. 15, a row address signal wiring layer Ax is arranged, and column address signal wiring layers Ay1 and Ay2 formed by parallel signal wiring layers in pairs are arranged so as to intersect with the row address signal wiring layer Ax. A standby signal wiring layer Sb is arranged in parallel with Ay1 and Ay2, and a memory cell layer MC is formed at the intersection of the row address signal wiring layer Ax and the column address signal wiring layers Ay1 and Ay2.

The memory cell layer MC has a base-collector junction layer D3 having a characteristic of flowing a current at a predetermined threshold voltage Vth on the row address signal wiring layer Ax side among the address signal wiring layers Ax, Ay1 and Ay2. Is formed on one surface of the row address signal wiring layer Ax in electrical contact,
A base-emitter junction layer D1 is formed in electrical contact between the other surface of the base-collector junction layer D3 and one of the column address signal interconnection layers Ay1 and Ay2, and the base is formed. A base-emitter junction layer D2 is formed in a laminated shape by electrically contacting the other surface of the collector junction layer D3 and the other wiring layer Ay2 of the column address signal wiring layers Ay1 and Ay2. . A depletion layer is expanded and contracted around the base / emitter junction layers D1 and D2 by a predetermined applied voltage to form base / emitter junction layers D1 and D2.
A gate electrode G for controlling the current flowing therethrough is formed, and the gate electrode G is in electrical contact with the standby signal wiring layer Sb.

FIG. 16A shows a sectional structure of the semiconductor layer 100 of the memory cell by RHET, and FIG. 16B shows an energy band diagram thereof. As shown in the figure, on a semi-insulating or insulating substrate (SI GaAs) 11, a good conductor layer (n ++-GaAs) 12 and a conductor layer (n +-) are sequentially formed.
GaAs) 13, single barrier layer (i-AlGaA)
s) 14, conductor layer (n + -GaAs) 15, resonance tunnel barrier layer (i-AlAs / i-GaAs / i-AlA)
s) 16, a conductor layer (n + -GaAs) 20 and a good conductor layer (n ++-GaAs) 21 are laminated.
Here, the resonant tunnel barrier layer 16 includes a quantum well layer (i-) between the tunnel barrier layers (i-AlAs) 17 and 19.
(GaAs) 18 is sandwiched to form a resonance tunnel structure.

The conductor layer (n + -GaAs) 15 and the single barrier layer (i-AlGaAs) 14 are laminated to form the base-collector junction layer D3, and the resonance tunnel barrier layer (i-AlAs / i). -GaAs / i-Al
As) 16 is a conductor layer (n + -GaAs) 15, a conductor layer (n + -GaAs) 20, and a good conductor layer (n ++-GaA).
The base-emitter junction layers D1 and D2 are formed by the resonant tunneling structure sandwiched between (s) 21.

Thus, the base-emitter junction layer D1
, D2 use a resonant tunneling structure, and as shown in FIG. 15, the gate electrode G connected to the standby signal wiring layer Sb has a resonant tunneling barrier layer (i-AlAs / i) around the base / emitter junction layers D1, D2. i-GaAs
/ I-AlAs) 16 above, a negative potential is applied to the gate electrode G to extend the depletion layer from the gate electrode G, thereby reducing the effective area of the resonant tunnel barrier. Become. This reduces the current flowing through the base-emitter junction layers D1 and D2.

On the contrary, when a positive potential is applied to the gate electrode G, the extension of the depletion layer from the gate electrode G is reduced,
The effective area of the resonance tunnel barrier is increased, and the current flowing through the base / emitter junction layers D1 and D2 is increased. Even when the gate electrode G is not formed, a depletion layer is generated by the surface level formed on the surface of the conductor layer (n + -GaAs) 20 and the effective area of the resonant tunnel barrier is increased to some extent. Since the gate electrode G has a small size, even if the gate electrode G has a potential of 0 instead of a positive potential, it has the effect of reducing the extension of the depletion layer and increasing the effective area of the resonant tunnel barrier.

Therefore, during standby, the above-mentioned FIG.
As shown in (b), a negative potential is applied to the gate electrode G,
By reducing the base current, it is possible to reduce the power consumption, and at the time of read / write operation, as shown in FIG. 3A, a positive or zero potential is applied to the gate electrode G to increase the base current. By doing so, it becomes possible to increase the speed of reading and writing information.

The memory cell MC in FIG. 16 is RH.
Although it is composed of ET, it may be composed of RBT instead of RHET. Memory cell MC in that case
16 is almost the same as that of FIG. 16, but the semiconductor layer forming the RBT is a semi-insulating or insulating substrate (S.
I. GaAs), n ++-GaAs layer, n +-
GaAs layer, p + -GaAs layer, resonance tunnel barrier layer (i-AlAs / i-GaAs / i-AlAs), n-
AlGaAs layer, n + -GaAs layer and n ++-GaA
The s layer is formed in a laminated shape. Here, the resonant tunnel barrier layer has a resonant tunnel structure in which a quantum well layer (i-GaAs) is sandwiched between tunnel barrier layers (i-AlAs).

[II] SRAM FIG. 17 shows an SRAM configured using the memory cell MC of FIG.
An example of RAM is disclosed. As shown in FIG. 17, row address signal line groups Ax1 to Ax5 are arranged in the row direction, and each pair of two column address signals electrically intersects these row address signal line groups Ax in a non-contact manner. Line groups Ay11 to Ay52 are arranged, and these column address signal line groups LY1 are arranged.
, LY2 parallel to the standby signal line groups Sb1 to Sb5
Are arranged. The base-emitter junction layers D1 and D2 and the base-collector junction layer D3 are provided at the respective intersections.
The memory cell MC including the gate electrode G is formed. Since each memory cell MC has the configuration shown in FIG. 1, its description is cited.

A row address decoder 1 for decoding row address data and applying a voltage corresponding to the data content is connected to one line end of the row address signal line group Ax. At the other line end of the row address signal line group Ax, a sense circuit 3 for detecting the current flowing in each column address signal line Ax1 to Ax5 and reading the information in the memory cell MC.
Are connected.

At the line ends of the column address signal line groups Ay1 and Ay2 and the standby signal line group Sb, the column address data is decoded and a voltage corresponding to the data content is applied, and at the time of writing or reading of information or standby. A column address decoder 2 for applying a predetermined voltage to the gate G is connected depending on the time. Writing of data to the memory cell MC is performed by supplying necessary row address data and column address data to the row address decoder 1 and the column address decoder 2 and selecting an address to be stored. At that time, a standby signal for applying a positive or zero potential to the gate G is supplied to the required standby signal line Sb. The row address signal line Ax and the column address signal line Ay in each memory cell MC
1. The manner of applying the voltage to the column address signal line Ay2 and the operation at the time of writing are as shown in FIGS. 3 to 14 and the related description thereof, and thus the description thereof will be omitted.

To read data from the memory cell MC, necessary row address data and column address data are supplied to the row address decoder 1 and the column address decoder 2, respectively, to select a read address, and the row address signal lines Ax1 to Ax5 are selected. The appearing current is detected by the sense circuit 3 to carry out. At that time, the necessary standby signal line Sb
Is supplied with a standby signal that gives a positive or zero potential to the gate G.

As described above, since each memory cell MC has address selectivity, data can be written in or read from the memory cell MC at an arbitrary address. At this time, a positive or zero potential is applied to the gate G via the standby signal line Sb to increase the current flowing through the base-emitter junction layers D1 and D2, thereby increasing the speed of writing or reading. be able to.

FIG. 18 is a circuit diagram when an SRAM is formed by using the memory cell shown in FIG. FIG.
As you can see, one of the column address signal lines, Ay1
1, Ay21, ... Ay51 can be connected to GND and commonly connected to the ground potential. FIG. 19 is a perspective view showing the three-dimensional structure of the SRAM of FIG. 17 using the memory cell of FIG. 1, and FIG. 20 is a plan layout view thereof.

As shown in FIG. 19, row address signal line layers Ax1 to Ax4 are formed in parallel with each other in the row direction, and a predetermined space is provided between the row address signal line layers Ax1 to Ax4. Column address signal line layers Ay11 to Ay22 in the crossing direction
Are formed parallel to each other. Further, the standby signal line layer S is provided in parallel with the column address signal line layers Ay11 to Ay42.
b1 to Sb4 are formed.

A pair of column address signal line layers (Ay11 and Ay12, or Ay21) is provided on each row address signal line layer Ax1 to Ax4.
And Ay22), a base-collector junction layer D3 having a length of a space between both ends thereof is formed. One surface of the base / collector junction layer D3 is in electrical contact with the row address signal line layer Ax. Also, the base / collector junction layer D
The base-emitter junction layer D2 is interposed between the other end of the other surface of the column 3 and the column address signal line layer Ayn2, and the other end of the other surface of the base-collector junction layer D3 and the column address signal line layer Ayn.
Base-emitter junction layer D1 is interposed between yn2 and
Base / emitter junction layer D2 and column address signal line layer Ayn
2. The base / emitter junction layer D1 and the column address signal line layer Ay n1 are electrically connected to each other.

Further, base / emitter junction layers D1 and D2
A gate electrode G for controlling the current flowing in the base-emitter junction layers D1 and D2 by expanding and contracting the depletion layer by a predetermined applied voltage is formed around the gate electrode G, and these gate electrodes G are respectively formed in the standby signal wiring layer. It is electrically connected to Sb1 to Sb4. Thus, the base / emitter junction layers D1 and D2 and the base / collector junction layer D3 are laminated so as to be sandwiched by both lines at the intersection of the row address signal line layer Ax and the column address signal line layer Ay intersecting each other. Since it is formed as described above, one memory cell MC can be formed with an area of about the width of two base / emitter junctions and the standby signal wiring layer Sb as shown in FIG. 18, and high density can be achieved.

FIG. 21 is a diagram of FIG. 17 using the memo cell of FIG.
3 is a perspective view showing a three-dimensional structure of the SRAM of FIG. FIG. 22 is a plan layout view thereof. In FIG. 21, Ax11 and A of FIG.
x21 is commonly connected to the GND wiring. [III] Manufacturing Method FIGS. 23 to 29 show an embodiment of the present invention. This embodiment discloses a method of manufacturing the above-mentioned SRAM and the like.

The manufacturing process is roughly classified into the semiconductor layer 10
0, growth of two base-emitter junction layers D1 and D2 by etching, and base-collector junction layer D
3, the formation of the row address signal line Ax, the formation of the row address signal line Ay and the standby signal line Sb, and the like. The semiconductor layer 100 uses an epitaxial growth method. That is, as shown in FIG. 15A, a good conductor layer (n ++-GaAs) 12 and a conductor layer (n + -G) are sequentially formed on a semi-insulating or insulating substrate (SI GaAs) 11.
aAs) 13, single barrier layer (i-AlGaAs)
14, conductor layer (n + -GaAs) 15, resonance tunnel barrier layer (i-AlAs / i-GaAs / i-AlAs)
16, a conductor layer (n + -GaAs) 20 and a good conductor layer (n ++-GaAs) 21 are grown.

Hereinafter, a series of processes will be described step by step with reference to FIGS. 23 to 29, the left column is a sectional view taken along the line II 'in FIG.
The right-hand column is a sectional view taken along the line II-II 'in FIG.
First, the semiconductor layer 100 is epitaxially grown. For the structure of the semiconductor layer 100, refer to FIG. Next, as shown in FIG. 23A, the good conductor layer 21
A metal film 201 is vapor-deposited on the surface of the metal film 201, and the metal film 201 is formed on the metal film 201 as shown in FIG.
After growing the insulating film 202 as shown in FIG.
As shown in (3), the resist 203 is used to pattern the base-emitter junction.

Next, as shown in FIG. 24D, the insulating film 202 is etched using the resist 203 as a mask to remove the insulating film 202 between the resists 203, and then the resist 203 is peeled off. Then, FIG.
As shown in (5), the metal film 201 is etched using the insulating film 202 as a mask. Then, FIG. 24 (6)
As shown in, the good conductor layer 21 and the conductor layer 20 of the semiconductor layer 100 are etched. Thereby, the good conductor layer 21
And a base-emitter junction layer D1 composed of a resonant tunnel barrier layer 16 sandwiched between the conductor layer 20 and the conductor layer 15,
A pattern of D2 will be formed.

Then, as shown in FIG. 25 (7), the base-emitter junction layer D1 and the base-emitter junction layer D2 are formed.
The insulating film 204 is grown to a thickness that fills the gap between the insulating film 202 and the insulating film 202. Then, as shown in FIG. 25 (8), the insulating film 202 is anisotropically etched. By this process, the insulating film 204a filling the space between the base-emitter junction layers D1 and D2
Thus, the base / emitter junction layer D1 and the base / emitter junction layer D2 are separated from each other, and the sidewall 204b that covers the side surfaces of the good conductor layer 21 and the conductor layer 20 is formed.

Next, as shown in FIG. 25 (9), the insulating film 202 on the metal film 201 is selectively removed by etching. Subsequently, as shown in FIG. 26 (10), a metal film is vapor-deposited and separated to form a metal film 205a on the metal film 201, and at the same time, a side surface of the base-emitter junction layer D1 is covered with a sidewall 204b. , D2 is formed on the exposed conductor layer 20 around the gate electrode 205b.

Next, as shown in FIG. 26 (11), the base 206 is patterned by the resist 206. Subsequently, as shown in FIG. 26 (12), the gate electrode 205b is etched using the resist 206 as a mask, and then the resist 206 is peeled off. Then, as shown in FIG. 27C, the semiconductor layer 10 is formed using the metal film 205a and the gate electrode 205b as a mask.
0 conductor layer 20, resonance tunnel barrier layer 16, conductor layer 1
5. The single barrier layer 14 and the conductor layer 13 are etched. As a result, a pattern of the base / collector junction layer D3 in which the conductor layer 15 and the single barrier layer 14 are joined is formed.

Then, as shown in FIG. 27 (14), patterning of the row address signal line Ax is performed by the resist 207. Subsequently, as shown in FIG. 27 (15), the good conductor layer 1 of the semiconductor layer 100 is formed using the resist 207 as a mask.
After the etching of 2, the resist 207 is peeled off. As a result, a pattern of the row address signal line Ax made of the good conductor layer 12 is formed.

Next, as shown in FIG. 28 (16), after a two-layer resist consisting of a resist (lower layer) 208 and a resist (upper layer) 209 is applied, as shown in FIG. 28 (17).
The row address signal line Ay and the standby signal line Sb are patterned. Subsequently, as shown in FIG. 29 (18), after depositing a metal film 210 on the entire surface, finally, as shown in FIG.
As shown in (19), perform lift-off and
The pattern of the column address signal lines Ay1 and Ay2 made of the metal film 210 is formed on the metal film 205a of the emitter junction layers D1 and D2, and at the same time, the metal film 2 is formed on the gate electrode 205b.
A pattern of the standby signal line Sb consisting of 10 is formed. Thus, the memory cell MC and each address signal line Ax
, Ay and the standby signal line Sb are formed.

Here, as shown in the right side of FIG. 29 (19), the resist (lower layer) 208 between the adjacent semiconductor layers 100 is removed, and the column address signal line Ay formed by the metal film 210 has an air bridge structure. Has become. With this air bridge structure, a void 211 is formed between adjacent memory cells. Since the void has a dielectric constant ε = 1, the parasitic capacitance is smaller than that in the state where the resist (lower layer) 208 is filled.

In the above embodiments, the memory cell M
Although C uses a GaAs semiconductor and uses the AlxGa1-xAs layer as a barrier, it is not limited to this compound semiconductor. For example, Inx that uses the InxAl1-xAs layer as a barrier is used.
It may be a GaAs semiconductor. Further, the present invention is not limited to a semiconductor, and can be configured with a memory cell containing metal. For example, it is possible to use a metal such as nickel aluminum as the row address signal line Ax and combine this with a necessary semiconductor to form a memory cell. The use of metal for the row address signal line Ax has the effect of reducing adverse effects (such as obstruction of speedup) due to resistance loss of the signal line.

Alternatively, the resonant tunnel diode as the base-emitter junction can be formed by using an appropriate metal (nickel aluminum or the like), and the same applies to the base-collector junction.

[0069]

As described above, according to the present invention, it is possible to provide a semiconductor memory including a novel memory cell that can be formed in a small area with a smaller number of elements.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a memory cell of a memory device according to the present invention.

FIG. 2 is an equivalent circuit diagram of another memory cell according to the present invention.

FIG. 3 is a characteristic diagram showing a base-emitter voltage dependency of a base current.

FIG. 4 is a characteristic diagram showing a base-collector voltage dependency of a base current.

FIG. 5 is an explanatory diagram of an operation principle of a memory cell.

FIG. 6 is a diagram illustrating the operating principle of a memory cell.

FIG. 7 is an explanatory diagram of an operation principle of a memory cell.

FIG. 8 is an explanatory diagram of an operation principle of a memory cell.

FIG. 9 is a characteristic diagram showing a read operation 1.

FIG. 10 is a characteristic diagram showing a read operation 2.

FIG. 11 is a characteristic diagram showing the write operation 1 at the stable point S1 of the memory cell.

FIG. 12 is a characteristic diagram showing the write operation 2 at the stable point S1 of the memory cell.

FIG. 13 is a characteristic diagram showing the write operation 1 at the stable point S2 of the memory cell.

FIG. 14 is a characteristic diagram showing the write operation 2 at the stable point S2 of the memory cell.

FIG. 15 is a perspective view showing a three-dimensional structure of a memory cell (RHET).

16 is a cross-sectional view showing a cross-sectional structure of the memory cell of FIG. 15 and its energy band diagram.

FIG. 17 is a block diagram of an SRAM circuit according to the present invention.

FIG. 18 is a block diagram of a circuit of another SRAM according to the present invention.

19 is a perspective view showing a three-dimensional structure of the SRAM of FIG.

20 is a plan layout view of the SRAM of FIG.

21 is a perspective view showing a three-dimensional structure of the SRAM of FIG.

22 is a plan layout view of the SRAM of FIG. 18. FIG.

FIG. 23 is a process chart for explaining the manufacturing process (1) of the memory device manufacturing method according to the present invention.

FIG. 24 is a process view for explaining the manufacturing process (2).

FIG. 25 is a process view for explaining the manufacturing process (3).

FIG. 26 is a process view for explaining the manufacturing process (4).

FIG. 27 is a process drawing for explaining the manufacturing process (5).

FIG. 28 is a process view for explaining the manufacturing process (6).

FIG. 29 is a process drawing for explaining the manufacturing process (7).

[Explanation of symbols]

E1, E2 ... Emitter electrode C ... Collector electrode Tr ... Transistor G ... Gate MC ... Memory cell Ax ... Row address signal line Ay, Ay1, Ay2 ... Column address signal line Sb ... Standby signal line GND ... Ground potential line D1 ... Base Emitter 2 junction layer (BE1) D2 ... Base-emitter 2 junction layer (BE2) D3 ... Base-collector junction layer S1, S2 ... Operation stable point VAx ... Row address voltage VAy, VAy1, VAy2 ... Column address voltage Vth ... Threshold Value voltage Vp1, Vp2 ... Peak voltage Vv ... Valley voltage 1 ... Row address decoder 2 ... Column address recorder 3 ... Sense circuit 11 ... Semi-insulating or insulating substrate (SI GaA)
s) 12 ... Good conductor layer (n ++-GaAs) 13 ... Conductor layer (n + -GaAs) 14 ... Single barrier layer (i-AlGaAs) 15 ... Conductor layer (n + -GaAs) 16 ... Resonant tunnel barrier layer ( i-AlAs / i-Ga
As / i-AlAs) 17 ... Tunnel barrier layer (i-AlAs) 18 ... Quantum well layer (i-GaAs) 19 ... Tunnel barrier layer (i-AlAs) 20 ... Conductor layer (n + -GaAs) 21 ... Good conductor layer (N ++-GaAs) 100 ... Semiconductor layer 201 ... Metal film 202 ... Insulating film 203 ... Resist 204 ... Insulating film 204a ... Insulating film 204b ... Sidewall 205a ... Metal film 205b ... Gate electrode 206 ... Resist 207 ... Resist 208 ... Resist (lower layer) 209 ... Resist (upper layer) 210 ... Metal film 211 ... Void

Claims (6)

[Claims] 1. A row address signal line (Ax), a pair of column address signal lines (Ay1, Ay2), a standby signal line (Sb), the row address signal line (Ax) and the column address signal line ( Ay1, Ay2) and a memory cell (MC) provided at an intersection with the memory cell (MC), wherein the memory cell (MC) has one collector electrode (C).
And a transistor having a double-emitter structure (T having two emitter electrodes (E1, E2) and exhibiting negative differential characteristics)
r) and the voltage applied to the transistor (Tr
), A gate (G) for controlling the base current of the transistor (Tr), and one emitter electrode (E1) of the transistor (Tr).
) Is one of the column address signal lines (Ay
1), the other emitter electrode (E2) is connected to the other (Ay2) of the column address signal lines on the high potential side, and the collector electrode (C) of the transistor (Tr) is the row address signal. A storage device characterized in that it is connected to a line (Ax) and the gate (G) is connected to the standby signal line (Sb). 2. The storage device according to claim 1, wherein one of the column address signal lines (Ay1, Ay2) is used as a common ground line (GND). apparatus. 3. A row address signal wiring layer (Ax) and two column address signal wiring layers (Ay1, Ay) arranged in parallel in pairs.
y2), a standby signal wiring layer (Sb) arranged in parallel with the column address signal wiring layers (Ay1, Ay2), the row address signal wiring layer (Ax) and the column address signal wiring layers (Ay1, Ay2). Memory cell (MC) sandwiched between the row address signal wiring layer (Ax) and the column address signal wiring layer (Ay1, Ay2) facing each other at the intersection with
The memory cell layer (MC) has a predetermined threshold voltage (V
a collector-base junction layer (D3) having a threshold characteristic of flowing a current at th) is formed by electrically contacting one surface of the collector-base junction layer (Ax) with the row address signal wiring layer (Ax). Two base-emitter junction layers (D1, D2) having negative differential characteristics are electrically connected in parallel between the other surface of D3) and the column address signal wiring layers (Ay1, Ay2). A gate electrode (G) formed in a laminated shape on the standby signal wiring layer (Sb) for controlling the current flowing in the base-emitter junction layers (D1, D2) by expanding and contracting the depletion layer by a predetermined applied voltage. A memory device, which is formed in electrical contact. 4. A method of reading information from a memory device according to claim 1, wherein when reading information stored in the memory cell (MC),
The voltage of the other operation stable point (S2) of the two base-emitter junctions (D1, D2) of the memory cell (MC) is set to V
s2, the voltage at the unstable point (Sm) is Vsm, the voltage at the row address signal line (Ax) is VAx, and the base-collector junction (D3)
When the threshold voltage of Vth is Vth, Vsm <V
A low level potential (Low) is applied to the row address signal line (Ax) and a high level potential (High) is applied to the other of the column address lines (Ay2) so that Ax + Vth <Vsm.
h) is added, and the depletion layer is expanded and contracted from the gate (G) to make the two base-emitter junctions (D1, D2).
), A positive or zero potential is applied to the standby signal line (Sb) to maintain the storage state before and after reading the storage information of the memory cell (MC) during standby. A storage device characterized by applying a negative potential to the standby signal line (Sb) so that the depletion layer expands and contracts from G) and the current flowing to the two base-emitter junctions (D1, D2) decreases. Information reading method. 5. The method for writing information in a memory device according to claim 1, wherein two stable operation points are created by two base-emitter junction layers (D1, D2) of the memory cell (MC), and When writing information to the stable point (S1) on the negative side of the unstable points, the voltage VAx of the row address signal line (Ax),
The low level potential (Lo) is applied to the row address signal line (Ax) so that the threshold voltage Vth and the unstable point voltage Vsn of the base-collector junction (D3) are VAx + Vth <Vsn.
w), a high level potential (High) is applied to at least one of the column address signal lines (Ay2), and the depletion layer is expanded and contracted from the gate (G) to form the two base-emitter junction layers. In order to increase the current flowing through (D1, D2), the standby signal line (Sb)
A positive or zero potential is applied to the row address signal to prevent the negative stable point of the two stable points from occurring when information is written to the positive stable point (S2) of the operation stable points. A high level potential (High) is applied to the line (Ax) and a predetermined potential is applied to the column address signal line, and a depletion layer is expanded and contracted from the gate (G) to cause the two base / emitter junction layers (D1) to expand and contract. ，
A positive or zero potential is applied to the standby signal line (Sb) so that the current flowing in D2) increases, and the negative or positive stable point (S1) of the two stable operating points is added.
, S2) in a standby state in which the memory state is maintained after writing to the gate (G), the depletion layer is expanded and contracted to reduce the current flowing through the two base-emitter junction layers (D1, D2). The standby signal line (S
A method for writing information in a memory device, characterized in that a negative potential is applied to b). 6. A row address signal line group (Ax1, Ax2, ...) Composed of a plurality of signal lines, and a pair of signal lines arranged in a direction intersecting the row address signal line group (Ax1, Ax2, ...). , Column address signal line group (Ay11, Ay12, ..., Ay21, Ay22, ...) And the column address signal line group (Ay11, Ay12 ,.
, Ay22, ...) Standby signal line groups (Sb1, Sb2, ...) Composed of a plurality of signal lines, row address signal line groups (Ax1, Ax2, ...) And column address signal line groups (Ay11, Ay12, ..., Ay21, Ay22
) And a plurality of memory cells (MC) according to claim 1, which are provided at respective intersections, and a row address decoder (1) for supplying a row address signal to the row address signal line group (Ax1, Ax2, ...). And the column address signal line group (Ay11, Ay12, ..., Ay21
, Ay22, ...) And a column address decoder (2) for supplying a column address signal to the column address signal line group (Ax1, Ax2, ...) And sense circuit (MC) for detecting the memory information of each memory cell (MC). 3) A storage device comprising: