JPH06112142A - Manufacture of superlattice semiconductor - Google Patents

Manufacture of superlattice semiconductor

Info

Publication number
JPH06112142A
JPH06112142A JP32267992A JP32267992A JPH06112142A JP H06112142 A JPH06112142 A JP H06112142A JP 32267992 A JP32267992 A JP 32267992A JP 32267992 A JP32267992 A JP 32267992A JP H06112142 A JPH06112142 A JP H06112142A
Authority
JP
Japan
Prior art keywords
semiconductor
substrate
superlattice
layer
growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32267992A
Other languages
Japanese (ja)
Other versions
JPH0817161B2 (en
Inventor
Junichi Nishizawa
潤一 西澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Science and Technology Agency
Original Assignee
Research Development Corp of Japan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Research Development Corp of Japan filed Critical Research Development Corp of Japan
Priority to JP4322679A priority Critical patent/JPH0817161B2/en
Publication of JPH06112142A publication Critical patent/JPH06112142A/en
Publication of JPH0817161B2 publication Critical patent/JPH0817161B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To manufacture a semiconductor device having the superlattice structure industrially at a molecule layer unit by a novel method. CONSTITUTION:Ultraviolet ray are applied to the surface of a substrate. Under this state, at least two kinds of raw material gases are alternately introduced on the surface of the substrate from the outside of a growing cell through at least two nozzles, whose tip openings face the vicinity of the surface of the semiconductor substrate. The specified number number of molecule layers are grown at 1-several molecule-layer unit for the first semiconductor only by the opening and closing of valves, which are arranged for the respective nozzles, and the evacuation of the growing cell in the first step. The spcified number of molecule layers are grown at 1-several molecule-layer unit for the second semiconductor, whose component element is different from that of the frist semiconductor. in the second step. The superlattice structure is formed by repeating the first and second steps by the specified number of times.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は自己停止機能を有した分
子層単位の超格子を有する半導体装置の製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a superlattice of a molecular layer unit having a self-stop function.

【0002】[0002]

【従来の技術】半導体単体では得られない特性の実現の
ために、異なる半導体を周期的に形成したものとして超
格子構造の半導体装置が知られている。しかし、この超
格子構造の半導体装置は、結晶の一次元方向に、母結晶
の格子定数に比べて十分長く、電子の平均自由行程より
は短かい周期的ポテンシャルを設けた構造としなければ
ならないことから、製造が難かしく、現在までのところ
製造は実験室段階に止り工業化に至っていない。という
のは、半導体の製造法として従来より分子線エピタキシ
ャル法(以下、MBE法と略す)、有機金属による結晶
成長法(以下、MO−CVD法と略す)原子層エピタキ
シャル法(以下、ALE法と略す)等が知られている
が、いずれも膜厚制御性や結晶性が悪く超格子構造とす
るのは容易ではないもしくは形成できないからである。
即ち、MBE法の場合は、分子線ソースを基板に当てて
成長を行なうために化学量論的組成(ストイキオメトリ
ー)を完全には満しにくいこと、基板に吸着した原子が
液相成長のようには結晶表面を自由に動きまわらないこ
とから良好な結晶構造が得られない欠点があった。
2. Description of the Related Art A semiconductor device having a superlattice structure is known as one in which different semiconductors are periodically formed in order to realize characteristics that cannot be obtained by a single semiconductor. However, this superlattice structure semiconductor device must have a structure in which a periodic potential is provided in the one-dimensional direction of the crystal that is sufficiently longer than the lattice constant of the host crystal and shorter than the mean free path of electrons. Therefore, it is difficult to manufacture, and so far, the manufacturing has stopped at the laboratory stage and has not been industrialized. As a semiconductor manufacturing method, a molecular beam epitaxial method (hereinafter abbreviated as MBE method), a crystal growth method using an organic metal (hereinafter abbreviated as MO-CVD method), an atomic layer epitaxial method (hereinafter referred to as an ALE method) are conventionally used. Although abbreviated) and the like are known, it is not easy to form a superlattice structure or it is not possible to form a superlattice structure due to poor film thickness controllability and crystallinity.
That is, in the case of the MBE method, it is difficult to completely satisfy the stoichiometric composition (stoichiometry) because the molecular beam source is applied to the substrate for growth, and the atoms adsorbed on the substrate are subjected to liquid phase growth. As described above, since the crystal surface does not move freely, there is a drawback that a good crystal structure cannot be obtained.

【0003】MO−CVD法では、Japan.J.A
ppl.Phys.19,(1980)L551〜L5
54等に超格子構造の形成例が示されているが、異なる
半導体相互の境界層(遷移層)の厚みが60Å(約20
分子層)と示されているように分子層単位の精度での成
長膜厚の制御が困難なこと、600℃といった高温の基
板温度が要求されること、熱分解反応によることからも
ともと結晶性が悪いという欠点があった。ALE法は特
開昭55−130896号公報に示されるように化合物
半導体の成分元素を含む蒸気をガラス基板表面に交互に
導入し、交換表面反応により薄膜を形成するものである
が、多結晶やアモルファスであるため格子定数が定義さ
れず、超格子構造を形成できない欠点があった。またA
LE法では蒸気交互導入1サイクルで1/3分子層以下
しか成長できない欠点があった。さらにALE法ではII
I−V族化合物半導体やSiが成長できないというよう
な欠点を有していた。
In the MO-CVD method, Japan. J. A
ppl. Phys. 19, (1980) L551 to L5
54, etc., an example of forming a superlattice structure is shown, but the thickness of the boundary layer (transition layer) between different semiconductors is 60Å (about 20
It is difficult to control the grown film thickness with the accuracy of each molecular layer as shown in (Molecular layer), a high substrate temperature of 600 ° C. is required, and the thermal decomposition reaction causes the crystallinity to be originally high. It had the drawback of being bad. The ALE method, as disclosed in Japanese Patent Application Laid-Open No. 55-130896, alternately introduces a vapor containing a component element of a compound semiconductor onto the surface of a glass substrate to form a thin film by an exchange surface reaction. Since it is amorphous, the lattice constant is not defined, and there is a drawback that a superlattice structure cannot be formed. Also A
The LE method has a drawback that only 1/3 molecular layer or less can be grown in one cycle of alternate steam introduction. Furthermore, in the ALE method, II
It has a defect that the IV compound semiconductor and Si cannot grow.

【0004】[0004]

【発明が解決しようとする課題】本発明は上記の点に鑑
み、新規な方法により超格子構造の半導体装置を工業的
に分子層単位で精密に製造できる方法を提供することを
目的とする。
SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide a method capable of industrially precisely manufacturing a semiconductor device having a superlattice structure in units of molecular layers by a novel method.

【0005】[0005]

【課題を解決するための手段】本発明は真空に排気する
成長槽内に外部より結晶成分元素を含むガスを所定の条
件で交互に導入することにより、ガス導入1サイクルで
少なくとも1分子層形成し成長膜厚を分子層単位で制御
し、化学量論的組成を満たす結晶を成長させることによ
り、分子層数で設計可能な超格子半導体装置が得られる
ようにしたことを特徴としている。
According to the present invention, at least one molecular layer is formed in one cycle of gas introduction by alternately introducing a gas containing a crystal component element from the outside into a growth tank evacuated to a vacuum under predetermined conditions. The growth film thickness is controlled on a molecular layer basis, and a crystal satisfying the stoichiometric composition is grown to obtain a superlattice semiconductor device which can be designed by the number of molecular layers.

【0006】[0006]

【実施例】以下、本発明の実施例をGaAs−Ga1-x
AlxAs1-yyの超格子半導体装置を製造する場合を
例にとり説明する。
EXAMPLES Examples of the present invention will be described below with reference to GaAs-Ga 1-x.
A case of manufacturing a superlattice semiconductor device of Al x As 1-y P y will be described as an example.

【0007】図1は本発明の一実施例に係る結晶成長装
置の構成図を示したものである。図において、1は成長
槽で材質はステンレス等の金属、2はゲートバルブ、3
は成長槽1を超高真空に排気するための排気装置、4は
GaCl3またはTMG(トリメチルガリウム)等のG
aを含む化合物ガスを導入するノズル、5はAsH3
のAsを含む化合物ガスを導入するノズル、6はTMA
(トリメチルアルミニウム)等のAlを含む化合物ガス
を導入するノズル、7はPH3、PCl3等のPを含む化
合物ガスを導入するノズル、8,9,10,11は前記
ノズルを開閉するバルブで、ガス源12(GaCl
3等)、13(AsH3)、14(TMA等)、15(P
3等)との間に設けられたもの、16は基板加熱用の
ヒーターで石英ガラスに封入したタングステン(W)線
で配線は図示省略しているもの、17は測温用の熱電
対、18はGaAs基板で、ノズル4,5,6,7の先
端開孔部はGaAs基板表面方向を向き、しかも基板表
面にできるだけ近づけて配置されている。19は成長槽
内の圧力を測定するための圧力計である。
FIG. 1 is a block diagram of a crystal growth apparatus according to an embodiment of the present invention. In the figure, 1 is a growth tank, the material is metal such as stainless steel, 2 is a gate valve, 3
Is an exhaust device for evacuating the growth tank 1 to an ultrahigh vacuum, and 4 is G such as GaCl 3 or TMG (trimethylgallium).
Nozzle for introducing a compound gas containing a, 5 is a nozzle for introducing a compound gas containing As such as AsH 3 , 6 is TMA
Nozzle for introducing a compound gas containing Al such as (trimethylaluminum), 7 is a nozzle for introducing a compound gas containing P such as PH 3 and PCl 3 , and 8, 9, 10, 11 are valves for opening and closing the nozzle. , Gas source 12 (GaCl
3 ), 13 (AsH 3 ), 14 (TMA, etc.), 15 (P
H 3 etc., 16 is a heater for heating the substrate, a tungsten (W) wire enclosed in quartz glass and wiring is not shown, 17 is a thermocouple for temperature measurement, Reference numeral 18 denotes a GaAs substrate, and the tip end openings of the nozzles 4, 5, 6 and 7 face the GaAs substrate surface direction and are arranged as close to the substrate surface as possible. Reference numeral 19 is a pressure gauge for measuring the pressure in the growth tank.

【0008】この構成で、GaAs基板18上にGaA
sをエピタキシャル成長させる場合は、先ず、ゲートバ
ルブ2を開け、超高真空排気装置3により成長槽1内を
10-7〜10-8Pascal(以下、Paと略す)程度
に排気する。次に、GaAs基板18を300〜800
℃望ましくは300〜500℃にヒーター16により加
熱した後に、TMG12を成長槽1内の圧力が10-1
107Paとなる範囲で1分子吸着層形成に必要な分子
数よりも十分多く0.5〜10秒間バルブ8を開けて導
入し、1分子吸着層を形成する。次に、1分子吸着層形
成に余った余分のTMGを成長槽1内より排気後、As
313を成長槽1内の圧力が10-1〜107Paとなる
範囲で1分子吸着層形成に必要な分子数よりも十分多く
2〜200秒間バルブ5を開けて導入する。1分子吸着
層形成に余った余分のAsH313はその後排気する。
このガス導入1サイクルに伴う交換表面反応でGaAs
1分子層が自己停止機能を有して成長できる。このガス
導入サイクルを所望の回数繰り返せば、所望の分子層数
のGaAsが、特別な膜厚モニタを使わなくても形成で
きる。
With this structure, GaA is formed on the GaAs substrate 18.
In the case of epitaxially growing s, first, the gate valve 2 is opened, and the inside of the growth tank 1 is evacuated to about 10 −7 to 10 −8 Pascal (hereinafter abbreviated as Pa) by the ultrahigh vacuum evacuation device 3. Next, the GaAs substrate 18 is set to 300-800.
° C. Preferably after heating by the heater 16 to 300 to 500 ° C., pressure in the growth chamber 1 TMG12 is 10 -1 to
In the range of 10 7 Pa, the number of molecules is sufficiently larger than the number of molecules necessary for forming the one-molecule adsorption layer, and the valve 8 is opened for 0.5 to 10 seconds to introduce the one-molecule adsorption layer. Next, after exhausting the excess TMG remaining for the formation of the adsorption layer for one molecule from the growth tank 1,
H 3 13 is introduced by opening the valve 5 for 2 to 200 seconds, which is sufficiently larger than the number of molecules necessary for forming a monomolecular adsorption layer within a range where the pressure in the growth tank 1 is 10 −1 to 10 7 Pa. The excess AsH 3 13 remaining for forming the one-molecule adsorption layer is then exhausted.
GaAs is formed by the exchange surface reaction accompanying this gas introduction cycle.
A monolayer can grow with a self-terminating function. By repeating this gas introduction cycle a desired number of times, GaAs having a desired number of molecular layers can be formed without using a special film thickness monitor.

【0009】続いて、このようにして成長させたGaA
s分子層の上にGa1-xAlxAs1-yyをヘテロエピタ
キシャル成長させる場合は、GaAsの成長と同じよう
にIII族のGaとAlを導入した後に、V族のAsとP
を導入することによって1分子層が成長でき、これを繰
り返せば所望の分子層数が得られる。
Subsequently, the GaA thus grown
In the case of heteroepitaxially growing Ga 1-x Al x As 1-y P y on the s molecular layer, Ga and Al of group III are introduced in the same manner as the growth of GaAs, and then As and P of group V are added.
By introducing, one molecular layer can be grown, and by repeating this, a desired number of molecular layers can be obtained.

【0010】図2は、上記分子層エピタキシャル成長乃
至ヘテロエピタキシャル成長によるGa1-xAlxAs
1-yy超格子半導体装置の製造過程を示したもので、先
ず、同図(a)に示すように、GaAs基板20上にG
aAs層21を分子層単位で所定の分子層数たとえば3
0分子層にエピタキシャル成長させる。続いて、同図
(b)に示すように、そのGaAs層21上にGa1-x
AlxAs1-yy層22をやはり分子層単位で所定の分
子層数たとえば40分子層を制御してヘテロエピタキシ
ャル成長させる。更に、以上の操作を所定の周期たとえ
ば100サイクル繰り返すことにより、超格子構造が形
成される。同図(c)に示したのは3層のGaAs層2
1とGa1-xAlxAs1-yy層22とを交互に分子層単
位で成長させた例である。このとき、GaAsに格子整
合させるためのGa1-xAlxAs1-yyの混晶の組成は
x=0.3,y=0.01とする。このようにして形成
した超格子構造に、同図(d)に示すように、Au−G
e合金を数100Å真空蒸着して電極23,24を形成
する。これは、例えば450℃、H2気流中で1分間熱
処理して形成する。これにより、超格子ダイオード25
が製造できる。図2(c)、(d)に示したようにGa
As層21とGa1-xAlxAs1-yy層22との間の遷
移層は全く無く、正確に分子層単位で超格子構造が製造
できる。
FIG. 2 shows Ga 1 -x Al x As formed by the above-mentioned molecular layer epitaxial growth or heteroepitaxial growth.
1-y P y This is a process for manufacturing a superlattice semiconductor device. First, as shown in FIG.
The aAs layer 21 has a predetermined number of molecular layers, for example, 3 for each molecular layer.
Epitaxially grow on the 0 molecular layer. Then, as shown in FIG. 3B, Ga 1 -x is formed on the GaAs layer 21.
The Al x As 1-y P y layer 22 is heteroepitaxially grown by controlling a predetermined number of molecular layers, for example, 40 molecular layers in a molecular layer unit. Further, by repeating the above operation for a predetermined cycle, for example, 100 cycles, a superlattice structure is formed. FIG. 3C shows three GaAs layers 2.
In this example, 1 and Ga 1-x Al x As 1-y P y layers 22 are alternately grown in molecular layer units. At this time, the composition of the mixed crystal of Ga 1-x Al x As 1-y P y for lattice matching with GaAs is x = 0.3 and y = 0.01. In the superlattice structure thus formed, as shown in FIG.
The electrodes 23 and 24 are formed by vacuum-depositing an e-alloy of several hundred liters. This is formed, for example, by heat treatment at 450 ° C. in a H 2 gas flow for 1 minute. As a result, the superlattice diode 25
Can be manufactured. As shown in FIGS. 2C and 2D, Ga
There is no transition layer between the As layer 21 and the Ga 1-x Al x As 1-y P y layer 22, and the superlattice structure can be accurately manufactured in a molecular layer unit.

【0011】ところで、上述のようにして超格子半導体
を製造する際、成長中に基板へ紫外線を照射することに
よって、成長温度を300℃以下といった低温に低下さ
せることができ、結晶品質を良くすることができる。こ
の紫外線源としては、水銀ランプ、Xeランプ、エキシ
マレーザ、アルゴンイオンレーザ等を用いることがで
き、成長槽1に窓を設け外部より基板18上に照射する
ようにすれば良い。
By the way, in manufacturing the superlattice semiconductor as described above, by irradiating the substrate with ultraviolet rays during the growth, the growth temperature can be lowered to a low temperature such as 300 ° C. or lower, and the crystal quality is improved. be able to. As the ultraviolet ray source, a mercury lamp, a Xe lamp, an excimer laser, an argon ion laser, or the like can be used, and a window may be provided in the growth tank 1 to irradiate the substrate 18 from the outside.

【0012】尚、以上の実施例においては、Ga1-x
xAs1-yyの超格子半導体装置について説明してき
たが、成長槽へ更に不純物を含むガスを導入することに
よって、GaAs、Ga1-xAlxAs1-yyへ不純物添
加できることは言う迄もない。この場合、GaAs、G
1-xAlxAs1-yy共に、n形の不純物を含むガスと
して、H2S等のVI族のTe,Se等の水素化物、フッ
化物を用いることができる。また、p形の不純物として
はZnCl3、デイメチル亜鉛等のガスをIII族乃至はV
族のガスと一緒に導入すれば良い。
In the above embodiment, Ga 1 -x A
The superlattice semiconductor device of l x As 1-y P y has been described. However, by introducing a gas containing impurities into the growth tank, impurities are added to GaAs and Ga 1-x Al x As 1-y P y . It goes without saying that you can do it. In this case, GaAs, G
As a gas containing an n-type impurity for both a 1-x Al x As 1-y P y , hydrides and fluorides of Group VI Te and Se such as H 2 S can be used. Further, as p-type impurities, a gas such as ZnCl 3 or demethylzinc may be used as a group III or V gas.
It can be introduced with the tribe gas.

【0013】また、超格子となる半導体の組合せは、上
記の実施例のほかに、InAs−GaSb、GaSb−
AlSb、InAs−AlSb、InP−In1-xGax
1-zAsz、InP−In1-xGaxAs、GaAs−G
aAs1-xx、GaP−GaP1-xAsx、GaAs−G
1-xInxAs、GaP−AlP、GaSb−InS
b、Ge−GaAs、Si−GaP、Si−Si1-x
x、CdTe−HgTe、PbTe−Pb1-xSnx
e、PbTe−Pb1-xGexTe等の組合せ、p形とn
形半導体の組合せ、3つの半導体の組合せ、例えばIn
As−GaSb−AlSb等に適用できる。
In addition to the above embodiments, the combination of semiconductors forming the superlattice is InAs-GaSb, GaSb-.
AlSb, InAs-AlSb, InP-In 1-x Ga x
P 1-z As z , InP-In 1-x Ga x As, GaAs-G
aAs 1-x P x , GaP-GaP 1-x As x , GaAs-G
a 1-x In x As, GaP-AlP, GaSb-InS
b, Ge-GaAs, Si- GaP, Si-Si 1-x G
e x , CdTe-HgTe, PbTe-Pb 1-x Sn x T
e, PbTe-Pb 1-x Ge x Te, etc. combination, p-type and n
Shaped semiconductor combinations, three semiconductor combinations, eg In
It can be applied to As-GaSb-AlSb and the like.

【0014】[0014]

【発明の効果】以上のように本発明によれば、半導体の
結晶膜を自己停止機能を有して分子層単位で結晶性良く
低温で成長させることができることから、従来のMO−
CVD法等の気相成長法で形成した超格子構造の場合に
存在する異なる半導体相互間の遷移層の全くない超格子
半導体装置を工業的に生産できるようになる。本発明に
よれば通常の気相成長におけるキャリアガス、あるいは
ALE法におけるガス相拡散バリアのような原料ガス以
外の不活性なガスを用いる必要もなく装置の構成が簡単
となる。さらに本発明によれば、自己停止機能による成
長なのでガス導入サイクルを数えるのみで、膜厚モニタ
を必要としないため、装置の構成や操作が容易で、分子
層単位の制御ができ工業的利点は大きい。
As described above, according to the present invention, since a semiconductor crystal film has a self-stopping function and can be grown in a molecular layer unit with good crystallinity at a low temperature, the conventional MO-
It becomes possible to industrially produce a superlattice semiconductor device having no transition layer between different semiconductors existing in the case of a superlattice structure formed by a vapor phase growth method such as a CVD method. According to the present invention, there is no need to use an inert gas other than a raw material gas such as a carrier gas in ordinary vapor phase growth or a gas phase diffusion barrier in the ALE method, and the apparatus configuration is simplified. Further, according to the present invention, since the growth is performed by the self-stop function, only gas introduction cycles are counted, and a film thickness monitor is not required. Therefore, the configuration and operation of the device are easy, and it is possible to control the molecular layer unit, which is an industrial advantage. large.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係る結晶成長装置の構成
図。
FIG. 1 is a configuration diagram of a crystal growth apparatus according to an embodiment of the present invention.

【図2】(a)〜(d)は図1の装置により製造される
超格子半導体装置の製造過程説明図。
2A to 2D are explanatory views of the manufacturing process of the superlattice semiconductor device manufactured by the apparatus of FIG.

【符号の説明】[Explanation of symbols]

1 成長槽 2 ゲートバルブ 3 排気装置 4,5,6,7 ノズル 8,9,10,11 バルブ 12,13,14,15 ガス源 16 ヒーター 17 熱電対 18,20 GaAs基板 19 圧力計 21 GaAs層 22 Ga1-xAlxAs1-yy層 23,24 電極 25 超格子ダイオード1 Growth Tank 2 Gate Valve 3 Exhaust Device 4,5,6,7 Nozzle 8,9,10,11 Valve 12,13,14,15 Gas Source 16 Heater 17 Thermocouple 18,20 GaAs Substrate 19 Pressure Gauge 21 GaAs Layer 22 Ga 1-x Al x As 1-y P y layer 23, 24 electrode 25 superlattice diode

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成4年11月30日[Submission date] November 30, 1992

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0003[Name of item to be corrected] 0003

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0003】MO−CVD法では、Japan.J.A
ppl.Phys.19,(1980)L551〜L5
54等に超格子構造の形成例が示されているが、異なる
半導体相互の境界層(遷移層)の厚みが60Å(約20
分子層)と示されているように分子層単位の精度での成
長膜厚の制御が困難なこと、600℃といった高温の基
板温度が要求されること、熱分解反応によることからも
ともと結晶性が悪いという欠点があった。ALE法は特
開昭55−130896号公報に示されるように化合物
半導体の成分元素を含む蒸気をガラス基板表面に交互に
導入し、交換表面反応により薄膜を形成するものである
が、多結晶やアモルファスであるため格子定数が定義さ
れず、超格子構造を形成できない欠点があった。またA
LE法では蒸気交互導入1サイクルで1/3分子層以下
しか成長できない欠点があった。さらにALE法では
の基本特許である特開昭51−77589号公報に記載
のように原理的にSiのような単元素半導体が成長でき
ないというような欠点を有していた。さらにALE法は
使用できる原料ガスが限定されるので、原料ガスの交互
導入によってIII−V族化合物半導体が成長できない
欠点を有していた。
In the MO-CVD method, Japan. J. A
ppl. Phys. 19, (1980) L551 to L5
54, etc., an example of forming a superlattice structure is shown, but the thickness of the boundary layer (transition layer) between different semiconductors is 60Å (about 20
It is difficult to control the grown film thickness with the accuracy of each molecular layer as shown in (Molecular layer), a high substrate temperature of 600 ° C. is required, and the thermal decomposition reaction causes the crystallinity to be originally high. It had the drawback of being bad. The ALE method, as disclosed in Japanese Patent Application Laid-Open No. 55-130896, alternately introduces a vapor containing a component element of a compound semiconductor onto the surface of a glass substrate to form a thin film by an exchange surface reaction. Since it is amorphous, the lattice constant is not defined, and there is a drawback that a superlattice structure cannot be formed. Also A
The LE method has a drawback that only 1/3 molecular layer or less can be grown in one cycle of alternate steam introduction. Furthermore, its in the ALE method
Japanese Patent Application Laid-Open No. 51-77589
In principle, there is a drawback that a single element semiconductor such as Si cannot grow. Furthermore, the ALE method
Since the raw material gases that can be used are limited, alternating raw material gases
III-V compound semiconductor cannot grow due to introduction
It had drawbacks.

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0005[Name of item to be corrected] 0005

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0005】[0005]

【課題を解決するための手段】本発明は真空に排気する
成長槽内に外部より結晶成分元素を含むガスを所定の条
件で交互に導入することにより、単分子吸着層を介した
交換表面反応を用いてガス導入1サイクルで少なくとも
1分子層形成し成長膜厚を分子層単位で制御し、化学量
論的組成を満たす結晶を成長させることにより、分子層
数で設計可能な超格子半導体装置が得られるようにした
ことを特徴としている。
According to the present invention, a gas containing a crystal component element is alternately introduced from the outside into a growth tank which is evacuated to a vacuum, and a single molecule adsorption layer is interposed therebetween.
By using the exchange surface reaction , at least one molecular layer is formed in one cycle of gas introduction, the growth film thickness is controlled in units of molecular layers, and by growing crystals satisfying the stoichiometric composition, it is possible to design by the number of molecular layers. The feature is that a lattice semiconductor device can be obtained.

【手続補正3】[Procedure 3]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0010[Correction target item name] 0010

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0010】図2は、上記分子層エピタキシャル成長乃
至ヘテロエピタキシャル成長によるGa1−xAl
1−y超格子半導体装置の製造過程を示したもの
で、先ず、同図(a)に示すように、GaAs基板20
上にGaAs層21を分子層単位で所定の分子層数たと
えば30分子層をガス導入サイクルを30回繰り返すこ
とによりエピタキシャル成長させる。続いて、同図
(b)に示すように、そのGaAs層21上にGa
1−xAlAs1−y層22をやはり分子層単位
で所定の分子層数たとえば40分子層をガス導入サイク
ルを40回繰り返すことによりヘテロエピタキシャル成
長させる。更に、以上のGaAs層21とGa1−x
As1−y層22とを交互に積む操作を所定の
周期たとえば100サイクル繰り返すことにより、超格
子構造が形成される。同図(c)に示したのは3層のG
aAs層21とGa1−xAlAs1−y層22
とを交互に分子層単位で成長させた例である。このと
き、GaAsに格子整合させるためのGa1−xAl
As1−yの混晶の組成はx=0.3,y=0.0
1とする。このようにして形成した超格子構造に、同図
(d)に示すように、Au−Ge合金を数100Å真空
蒸着して電極23,24を形成する。これは、例えば4
50℃、H気流中で1分間熱処理して形成する。これ
により、超格子ダイオード25が製造できる。図2
(c)、(d)に示したようにGaAs層21とGa
1−xAlAs1−y層22との間の遷移層は全
く無く、正確に分子層単位で超格子構造が製造できる。
FIG. 2 shows Ga 1-x Al x A formed by the above-described molecular layer epitaxial growth or heteroepitaxial growth.
1 shows a manufacturing process of an s 1-y P y superlattice semiconductor device. First, as shown in FIG.
The gas introduction cycle is repeated 30 times with the GaAs layer 21 having a predetermined number of molecular layers, for example, 30 molecular layers on a molecular layer basis.
And epitaxially grow. Then, as shown in FIG.
The 1-x Al x As 1-y P y layer 22 is also provided with a predetermined number of molecular layers, for example, 40 molecular layers in a gas introduction cycle in a molecular layer unit.
Heteroepitaxial growth is repeated 40 times . Furthermore, the above GaAs layer 21 and Ga 1-x A
The superlattice structure is formed by repeating the operation of alternately stacking the l x As 1-y P y layers 22 at a predetermined cycle, for example, 100 cycles. In the same figure (c), three layers of G are shown.
aAs layer 21 and Ga 1-x Al x As 1-y P y layer 22
In this example, and are alternately grown in a molecular layer unit. At this time, Ga 1-x Al x for lattice matching with GaAs
The composition of the mixed crystal of As 1-y P y is x = 0.3, y = 0.0.
Set to 1. On the superlattice structure thus formed, as shown in FIG. 4D, an Au—Ge alloy is vacuum-deposited by several hundred Å to form electrodes 23 and 24. This is, for example, 4
It is formed by heat treatment at 50 ° C. for 1 minute in an H 2 stream. Thereby, the superlattice diode 25 can be manufactured. Figure 2
As shown in (c) and (d), the GaAs layer 21 and Ga are
There is no transition layer between the 1-x Al x As 1-y P y layer 22 and the superlattice structure can be accurately manufactured in molecular layer units.

【手続補正4】[Procedure amendment 4]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0014[Correction target item name] 0014

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0014】[0014]

【発明の効果】以上のように本発明によれば、半導体の
結晶膜を自己停止機能を有して分子層単位で結晶性良く
低温で成長させることができることから、従来のMO−
CVD法等の気相成長法で形成した超格子構造の場合に
存在する異なる半導体相互間の遷移層の全くない超格子
半導体装置を工業的に生産できるようになる。本発明に
よれば通常の気相成長におけるキャリアガス、あるいは
ALE法におけるガス相拡散バリアのような原料ガス以
外の不活性なガスを用いる必要もなく装置の構成が簡単
となる。さらに本発明によれば、自己停止機能による
子層単位の成長なのでガス導入サイクルを数えるのみ
で、膜厚モニタを必要としないため、装置の構成や操作
が容易で、分子層単位の制御ができるさらに本発明に
よればALE法では原理的に不可能であった単元素半導
体の超格子の形成が可能なので、工業的に重要なSi−
Si1−xGeといった超格子が分子層単位で形成で
きる。さらに本発明によればALE法では使用できなか
ったTMG,TEG,GaCl等の蒸気圧の低いガス
が使用可能なので、最も超格子構造の応用されているI
II−V族化合物半導体の超格子が実現できるので工業
的利点は大きい。さらに本発明によれば紫外光を照射す
ることにより、光エネルギーで表面泳動等の表面反応を
促進し、ホール移動度が高い等の結晶品質の高い超格子
が実現できるので、極めて高速で、高効率で動作する超
格子半導体装置が実現できる。
As described above, according to the present invention, since a semiconductor crystal film has a self-stopping function and can be grown in a molecular layer unit with good crystallinity at a low temperature, the conventional MO-
It becomes possible to industrially produce a superlattice semiconductor device having no transition layer between different semiconductors existing in the case of a superlattice structure formed by a vapor phase growth method such as a CVD method. According to the present invention, there is no need to use an inert gas other than a raw material gas such as a carrier gas in ordinary vapor phase growth or a gas phase diffusion barrier in the ALE method, and the apparatus configuration is simplified. Further according to the present invention, minute by self-limiting feature
Since the growth is carried out in units of child layers, only gas introduction cycles are counted and a film thickness monitor is not required. Therefore, the configuration and operation of the apparatus are easy, and control can be performed in units of molecular layers. Further in the present invention
According to this, single-element semiconductivity, which was impossible in principle by the ALE method
Since it is possible to form a superlattice of the body, Si-
A superlattice such as Si 1-x Ge x can be formed in molecular layer units.
Wear. Further, according to the present invention, it cannot be used in the ALE method.
Gas with low vapor pressure such as TMG, TEG, GaCl 3
Can be used, so that the most applied superlattice structure is I
Since a superlattice of II-V compound semiconductors can be realized,
The economic advantage is great. Further, according to the present invention, ultraviolet light is irradiated.
By doing so, light energy can cause surface reactions such as surface migration.
Superlattice with high crystal quality such as promoting and high hole mobility
Because it can be realized, it is extremely fast and operates with high efficiency.
A lattice semiconductor device can be realized.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 先端開孔が半導体基板表面近傍に向いた
少なく共2本のノズルのそれぞれを介して、少なく共2
種類の原料ガスを成長槽の外部から該基板表面に交互に
導入し、該ノズルのそれぞれに配設されたバルブの開閉
と、該成長槽の真空排気のみにより、前記基板表面上の
交換表面反応を実現し、該交換表面反応の1サイクルに
付き半導体単結晶の少なく共1分子層を形成し、同時に
紫外光を前記基板表面上に照射し、前記半導体単結晶の
結晶品質を向上させ、該サイクルを繰り返すことによっ
て所望の分子層数の単結晶を得る方法であって、 (i)第1の半導体を1乃至数分子層単位で所定の分子
層数成長させる工程と、 (ii)前記第1の半導体の上に、前記第1の半導体とは
成分元素の異なる第2の半導体を1乃至数分子層単位で
所定の分子層数成長させる工程とを所定の回数交互に繰
り返すことにより超格子半導体構造を形成することを特
徴とする超格子半導体装置の製造方法。
1. A tip opening is directed toward the vicinity of the surface of a semiconductor substrate, and at least two nozzles are provided through each of the two nozzles.
An exchange surface reaction on the surface of the substrate is performed by alternately introducing different kinds of source gas from the outside of the growth tank to the surface of the substrate, opening and closing valves provided in each of the nozzles, and evacuating the growth tank. And a monomolecular layer containing less semiconductor single crystal is formed in one cycle of the exchange surface reaction, and at the same time, ultraviolet light is irradiated onto the substrate surface to improve the crystal quality of the semiconductor single crystal. A method of obtaining a single crystal having a desired number of molecular layers by repeating a cycle, comprising: (i) growing a first semiconductor in a predetermined number of molecular layers in a unit of one to several molecular layers; A superlattice is formed by alternately repeating a predetermined number of molecular layer growth steps of a second semiconductor having a constituent element different from that of the first semiconductor in a unit of one to several molecular layers on the first semiconductor. Specialized in forming semiconductor structures A method for manufacturing a superlattice semiconductor device.
JP4322679A 1992-11-06 1992-11-06 Method for manufacturing superlattice semiconductor device Expired - Lifetime JPH0817161B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4322679A JPH0817161B2 (en) 1992-11-06 1992-11-06 Method for manufacturing superlattice semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4322679A JPH0817161B2 (en) 1992-11-06 1992-11-06 Method for manufacturing superlattice semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP59153968A Division JPH0787179B2 (en) 1984-07-26 1984-07-26 Method for manufacturing superlattice semiconductor device

Publications (2)

Publication Number Publication Date
JPH06112142A true JPH06112142A (en) 1994-04-22
JPH0817161B2 JPH0817161B2 (en) 1996-02-21

Family

ID=18146408

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4322679A Expired - Lifetime JPH0817161B2 (en) 1992-11-06 1992-11-06 Method for manufacturing superlattice semiconductor device

Country Status (1)

Country Link
JP (1) JPH0817161B2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6134929A (en) * 1984-07-26 1986-02-19 Res Dev Corp Of Japan Growing device of semiconductor device
JPS6134921A (en) * 1984-07-26 1986-02-19 Res Dev Corp Of Japan Manufacture of semiconductor device
JPS6134922A (en) * 1984-07-26 1986-02-19 Res Dev Corp Of Japan Manufacture of super lattice semiconductor device
JPS6134927A (en) * 1984-07-26 1986-02-19 Res Dev Corp Of Japan Growing process of compound semiconductor single crystal thin film
JPH04322680A (en) * 1991-04-23 1992-11-12 Heiwa Corp Card system pinball machine

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6134929A (en) * 1984-07-26 1986-02-19 Res Dev Corp Of Japan Growing device of semiconductor device
JPS6134921A (en) * 1984-07-26 1986-02-19 Res Dev Corp Of Japan Manufacture of semiconductor device
JPS6134922A (en) * 1984-07-26 1986-02-19 Res Dev Corp Of Japan Manufacture of super lattice semiconductor device
JPS6134927A (en) * 1984-07-26 1986-02-19 Res Dev Corp Of Japan Growing process of compound semiconductor single crystal thin film
JPH04322680A (en) * 1991-04-23 1992-11-12 Heiwa Corp Card system pinball machine

Also Published As

Publication number Publication date
JPH0817161B2 (en) 1996-02-21

Similar Documents

Publication Publication Date Title
US5250148A (en) Process for growing GaAs monocrystal film
US5294286A (en) Process for forming a thin film of silicon
JPS63132421A (en) Epitaxial growth method for compound semiconductor
JPS6134928A (en) Growing process of element semiconductor single crystal thin film
US7625447B2 (en) Method of growing semiconductor crystal
US6334901B1 (en) Apparatus for forming semiconductor crystal
GB2162862A (en) Process for forming monocrystalline thin film of compound semiconductor
JPS6134927A (en) Growing process of compound semiconductor single crystal thin film
JP2003332234A (en) Sapphire substrate having nitride layer and its manufacturing method
JP2577550B2 (en) Impurity doping of III-V compound semiconductor single crystal thin films
JPH06112142A (en) Manufacture of superlattice semiconductor
JPH0787179B2 (en) Method for manufacturing superlattice semiconductor device
JP2821557B2 (en) Method for growing compound semiconductor single crystal thin film
JP2577542B2 (en) Semiconductor crystal growth equipment
JPS61260622A (en) Growth for gaas single crystal thin film
JP2577543B2 (en) Single crystal thin film growth equipment
JPH01245512A (en) Formation of iii-v compound semiconductor by epitaxial growth
JP2577544B2 (en) Method for manufacturing semiconductor device
JPH0728079B2 (en) Method for manufacturing semiconductor laser
JP2567331B2 (en) Method of growing compound semiconductor single crystal thin film
JP2654608B2 (en) Method for manufacturing GaAs semiconductor diode
JP2753832B2 (en) III-V Vapor Phase Growth of Group V Compound Semiconductor
JP2620546B2 (en) Method for producing compound semiconductor epitaxy layer
JPH0292891A (en) Molecular beam epitaxial growth process and apparatus therefor
JPH0766908B2 (en) Semiconductor single crystal growth method

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term