JPH06111460A - Device for driving magnetic disk - Google Patents

Abstract

PURPOSE:To excellently record and reproduce data for a disk by reducing the influence of various kinds of fluctuation main causes. CONSTITUTION:A prescribed value for programble operation measured considering various fluctuation at the manufacturing time is stored in a programable register 144 in an R/W controller 50 controlling an access for the disk by a prescribed value setting part 58A in a micro computer 58. A signal is processed by a characteristic based on the prescribed value in an AGC circuit 100, etc., in the R/W controller 50. Thus, the influence of various kinds of fluctuation main causes are reduced, and the data are recorded and reproduced. Further, since the prescribed value is reset or revised by a start time resetting part 58B or a prescribed value revision part 58c at the time of restarting a motor or detecting an data error, the occurrence of an error is reduced further, and then, the data are recorded and reproduced excellently.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a disk size of 2.5 inch, 1.8 inch, or 1.3 inch used for a so-called notebook type personal computer, palm-sized palmtop type personal computer or the like. The present invention relates to improvement of a magnetic disk drive device suitable for recording and reproducing data on and from a relatively small magnetic disk.

[0002]

2. Description of the Related Art Magnetic disks such as hard disks are
For example, as shown in FIG. 9, concentric tracks T0, ..., T100, ... Having a constant width are divided in the diameter direction, and each track T is a sector S1.
The rotation direction is divided by S2, ..., S48. Servo signals SV1, SV2, ..., SV4 for positioning the head and generating a speed signal of the spindle motor are provided on the heads of these sectors S1, S2 ,.
8 is recorded.

As shown in FIG. 10, each servo signal has a burst signal SYNC for synchronization, an erase gap GAP as a reference timing signal for generating a servo signal, and one sector for one rotation of the disk. An index recognition signal INDEX indicating an eye, an absolute address formed by a 11-bit great code for each track for rough track direction positioning, and two burst signals A shifted by half a track for accurate positioning , B and burst signals C and D at the track center, respectively.

Such a disc is assembled in a room with a high degree of cleanliness because it is necessary to reduce the dust that causes a head crash to the maximum extent, and the base and the housing are sealed with a sealing material. The structure of the magnetic disk drive will be further described with reference to FIG. 9. The spindle motor for rotating the disk 900 at, for example, 3600 rpm is an in-hub type with respect to a predetermined base (not shown). A magnetic circuit is arranged on the inner diameter side of the disk 900. Recording (writing) and reproducing (reading) information on the disc
The heads 902 are provided on the front and back surfaces of the disc 900, respectively.

Next, the head 902 is supported on one end of a rotary actuator 904. The rotary actuator 904 is configured around a rotary arm 908 rotatably supported by a pivot shaft 906, a head 902 is provided at one end thereof, and the rotary arm 908 is rotationally driven at the other end thereof. Voice coil motor (hereinafter referred to as "VCM") 91 for
A 0 voice coil 912 is provided. VCM91
No. 0 magnet is provided on the base side (not shown), and the spindle motor and the pivot shaft 9 are attached to the base.
The bearing portion 06 is fixedly supported. The base is sealed in a housing (not shown) via a sealing means (not shown).

Further, the base yoke of the VCM is provided with a connector for electrical connection with the outside. An FPC (flexible printed circuit board) having a required circuit is provided between the connector and the head 902 or the rotary actuator 904 to form an integral assembly. By the way, in such a magnetic disk drive, since the disk may be rotationally servoed at a constant angular velocity (CAV), access is easy. However, both the inner and outer circumferences have the same data recording density, and the efficiency is not good. On the other hand, when the number of sectors is changed for each track and the rotary servo is performed at a constant linear velocity (CLV), the recording density is improved. However, this method makes the rotary servo extremely complicated.

Therefore, a method is considered in which the advantages of both methods are utilized, and for example, there is a patent application as Japanese Patent Application No. 4-13173. The allocation of physical sectors of the magnetic disk according to this prior art is similar to that of the prior art in FIG. 10, and 48 servo areas S are radially arranged at appropriate intervals.
V1, SV2, SV3, ..., SV48 are provided, and the physical sectors S1, S2, S3 ,. As described above, the servo signal follows the conventional general sector servo system, the temporal position of the servo signal is the same on the inner and outer circumferences of the track, and the servo signals of the servo areas SV1, SV2 ,. , S2, ... The positions are synchronized. Therefore, the trailing edge of the servo gate is the logical sector S1, S
2, ... has begun.

Next, in order to facilitate understanding of the present invention, allocation of logical sectors in the prior art will be described with reference to FIGS. FIG. 11 shows allocation of logical sectors of the magnetic disk according to the present technology. Further, FIG. 12 shows the logical sector structure of FIG. 11 cut open in the circumferential direction. In these figures,
Many tracks are in zones Z1, Z2, Z3, Z4, Z
It is divided into five. The same logical sector is allocated in each zone.

As mentioned above, the physical sector S of FIG.
If data is recorded as it is for 1, S2, S3, .. Therefore, it is possible to increase the memory capacity of the disk by setting the linear recording density at the inner and outer circumferences to be substantially the same and making the data recording density on the outer circumference side higher than that on the inner circumference side. However, while the format capacity per logical sector is fixed at 512 bytes (actually, SYNC bytes and others are added), the relative line between the head and the magnetic disk on the inner and outer circumferences of the track is fixed. The speed difference is about 1.5. Therefore, it is necessary to change the format capacity per one servo section in order to record data with the same linear recording density on the inner and outer circumferences.

Therefore, in the present technology, the physical sectors S1,
Logical sectors are allocated differently from S2, ..., and the structure is such that the format capacity of one servo section is not fixed to 512 bytes but is increased or decreased in 1-byte units. That is, from zone Z1 to zone Z3, there are 5
The format is 12 bytes or more, and zone Z
4 has a 512-byte format. However, zone Z5 has a format of 512 bytes or less.

For example, the zone Z1 will be described.
The unformatted capacity of the physical sector S1 between the servo areas SV1 and SV2 is 755 bytes, whereas the unformatted capacity of one logical sector may be 580 bytes or more. Therefore, in the first servo section ΔS1 (see FIGS. 11 and 12A), the first logical sector LS1 and the second logical sector LS1
163 bytes of the front part of the logical sector LS2 of are inserted (see FIGS. 11 and 12D).

Similarly, the next servo section ΔS2 (see FIG. 1)
1, FIG. 12A), the second logical sector LS2
The rear part 453 bytes and the front part 302 bytes of the third logical sector LS3 are inserted (see FIGS. 11 and 12D). Thereafter, in the same manner, logical sectors are sequentially allocated as shown in the figure. For zones Z2 and Z3 as well, although the unformat capacity of the servo sections ΔS1, ΔS2, ... Is different from that of zone Z1, logical sector allocation is performed in the same manner.

Next, in the zone Z4, the unformat capacity of the servo sections ΔS1, ΔS2, ... Is 580.
Each byte corresponds to one physical sector and one logical sector. Therefore, 1
580 bytes are entered in the servo section (Figs. 11 and 12).
(See (F)), the sector allocation is the same as in the prior art of FIG.

Next, regarding the zone Z5, the zone Z1
On the contrary, since the unformat capacity of the servo sections ΔS1, ΔS2, ... Is as narrow as 566 bytes, one in one servo section.
Cannot fit 580 bytes of logical sector. Therefore, in the servo section ΔS1 (see FIG. 9A), the first
The 566 bytes of the front portion of the logical sector LS1 of the above are inserted (see FIG. 12H). Then, the remaining 50 bytes are put into the next servo section ΔS2 (see (H) in the figure). In the servo section ΔS2, 516 bytes of the front part of the second logical sector LS2 are also included (see FIG. 11H). Thereafter, in the same manner, logical sectors are sequentially allocated as shown in the figure. FIG. 12B shows an index pulse indicating the starting point of data recording.

FIG. 13D shows an example of a detailed data format in the logical sector of zone Z1. 12A to 12C are shown in FIGS.
It is similar to (C). Explaining the second logical sector LS2, SYNC (16 bytes), ID (15 bytes) from the beginning of the portion included in the first servo section ΔS1.
Byte), SYNC (16 bytes), DATA (108
Byte) and PAD (3 bytes). Next, the format after splitting by the servo area SV2 is SYNC (16 bytes), DATA (40
The order is 4 bytes), ECC (11 bytes), and PAD (3 bytes).

That is, as is clear from comparison with the format of the first logical sector LS1 in FIG. 1D, the PAD portion indicating the end of data after the data split by the servo areas SV1, SV2 ,. Is added to the beginning of the split data for synchronization.
A YNC part is added. The data written to or read from the magnetic disk by the drive device described later is DA
The portion other than the TA portion is written in advance at the time of formatting the magnetic disk at the time of factory shipment.

Further, in the ID section, for example, FIG.
It contains information such as To explain from the beginning, SYNC, AM, OFFSET (information indicating the jump destination address of the alternative sector), HEAD, CYL, SEC,
The order is FLG, SPLIT, CRC, PAD. Each information is usually composed of 1 byte (8 bits), but is composed of 4 bits or 12 bits as required.

Of these, the FLG section (4 bits) is flagged as to whether or not the data is split, and the SPLIT section (12 bits) is located at the position of the logical sector by the servo gate. Data indicating whether or not the data is split, for example, the number of bytes to be split is stored. The number of bytes to be split is different for each zone and each logical sector, and is the following Table 1 in the present technology.

[0019]

[Table 1]

In Table 1, the ID column includes 16 bytes of the SYNC part before the ID part (FIG. 13 (D)).
reference). Further, because of the periodicity described later, the data in Table 1 is repeated at a constant cycle. In this table, GAP is a gap between data, PSEC is a pseudo sector pulse which will be described later, and REST shows a remaining portion.

The table 1 will be further described. For example, the physical sector S1 of the zone Z1 has a first logical sector LS.
1 ID (+ head SYNC) = 31 bytes, SYNC
= 16 bytes, DATA = 512 bytes, ECC = 11
Byte, PAD = 3 bytes are recorded respectively, and after that,
ID of second logical sector LS2 (+ leading SYNC) = 3
1 byte, SYNC = 16 bytes, DATA = 108 bytes, PAD = 3 bytes are recorded (FIG. 13).
(See (A) and (D)).

Next, in the front portion of the next physical sector S2 in the zone Z1, the remaining S of the second logical sector LS2 is described.
YNC = 16 bytes, DATA = 404 bytes, ECC
= 11 bytes and PAD = 3 bytes are recorded in that order. That is, for the second logical sector LS2, 10
8 bytes are split into the physical sector S1, the remaining 404 bytes are split into the physical sector S2, and so on. The same applies to the following logical sectors.

In the zone Z4, the physical sector and the logical sector coincide with each other as described above.
ID = 31 bytes, SYNC = 16 bytes, DATA =
Only 512 bytes, ECC = 11 bytes, and PAD = 3 bytes are recorded in order.

Such split information is recorded in the ID part. Therefore, the FLG part of the ID part (see FIG. 13E)
It is possible to know from the reference) whether or not the logical sector is split, and further, from the SPLIT section, it is possible to know at which byte the split occurs. Based on these pieces of information, it becomes possible to access the logical sectors LS1, LS2, ....

Next, in the zones Z1 to Z3 and Z5, the respective logical sectors LS1, LS2 ,.
2, ... does not necessarily match. Therefore, a signal for servoing the logical sector is required.
In the present technology, such sector servo is performed by using the pseudo sector pulse indicating the head of each logical sector LS1, LS2, ... (FIG. 12 (C),
(E), (G) and FIG. 13 (C)).

Next, a method of generating this pseudo sector pulse will be described. First, the pseudo sector pulse will be described. As shown in FIG. 11 or 10, the servo sections ΔS1, ΔS2 ,.
In the present technology, the pseudo sector pulse is generated at a constant cycle. For example, in the zone Z1, the pseudo sector pulse allocation in the servo sections ΔS1 to ΔS4 is the same as the pseudo sector pulse allocation in the servo sections ΔS5 to ΔS8 (FIG. 12 (A),
(See (C)). That is, 5 logical sectors are periodically allocated in 4 physical sectors. In the present technology, the pseudo sector pulse is generated by repeating the greatest common divisor 4 or more for all zones.

On the other hand, such a pseudo sector pulse is generated from the servo gate which detects the servo signals of the servo areas SV1, SV2, .... That is, the time information from the servo gate to the generation of the pseudo sector pulse is obtained in advance, and the pseudo sector pulse is generated based on this time information. In the PSEC column of Table 1, an example of such time information is shown as the number of bytes. However, since the pseudo sector pulse has the above-mentioned periodicity, it is not necessary to provide the time information for all the pseudo sector pulses for one round of the magnetic disk. For example, in zone Z1, 4 physical sectors × 2 pseudo sector pulses = 8 pieces of time information are sufficient. Table 2 below summarizes these relationships for each zone.

[0028]

[Table 2]

As shown in Table 2, 1 in zone Z2
It is possible to generate all pseudo sector pulses with time information of 2, 24 in the zone Z3, 2 in the zone Z4, and 24 in the zone Z5. 8 + 12 + in all zones
24 + 2 + 24 = 70. On the other hand, if there is no repetition of the pseudo sector pulse, 48 physical sectors x
2 pseudo sector pulses = 96 pieces of time information are required,
96 × 5 = 480 in all zones.

As a result, the memory capacity for storing the time information for generating the pseudo sector pulse can be reduced, and the number of gates of the gate array forming the timing generating circuit for generating the sector pulse can be reduced. The cost of the array can be reduced. Further, by providing such periodicity to reduce the amount of data, the operation of setting the time information of the pseudo sector pulse generation in the timing generation circuit while performing the access control in one logical sector is performed during the seek of the head. You will be able to complete it.

Next, referring to FIG. 14, a drive device for the magnetic disk of the above-mentioned format will be described. In the figure, the gate array 28 is provided with a timing generation circuit 28A, in which the servo gate in each zone and the time information of the pseudo sector pulse are set to generate the pseudo sector pulse. The format of the magnetic disk 10 is as shown in FIG. 11, and the time information of the servo gate and the pseudo sector pulse described above is stored in the microcomputer 30.
It is stored in advance in the internal memory.

The operation of this drive device is basically the same as that of a general hard disk drive that has been put into practical use, and when the magnetic disk 10 is accessed from the personal computer through the connection terminal 32, the gate array is operated. 28, microcomputer 30, servo control unit 42
The VCM 38 is driven by each driver 40 based on the instruction. Then, the heads 12 and 14 move to access a required address on the magnetic disk 10, and the R / W amplifier 16 reads or writes data based on an instruction from the R / W controller 18. In addition, SPM3
4 is controlled by the SPM driver 36 to rotate at a constant speed.

In this case, the servo areas SV1, SV
As shown in FIG. 11, the servo pulse of V2, ...
The positions are temporally coincident with each other on any track of the magnetic disk 10. Therefore, the gate array 2
No complicated circuit is required to generate the window for detecting the servo pulse in FIG. Further, the servo pulse can be accurately detected regardless of the position of the heads 12 and 14,
The rotation control of the PM 34 is performed well. Further, similarly, the servo pulse detection by the predictive control of the seek of the heads 12 and 14 is also accurately performed.

Next, when accessing the magnetic disk 10, the time information from the servo pulse of the pseudo sector pulse in the zone to which the corresponding track belongs is transferred from the microcomputer 30 to the register 28B of the timing generation circuit 28A of the gate array 28. Set. In the timing generation circuit 28A, the time from the servo gate is set in the counter 28C according to the contents of the register 28B and the counting operation is performed to generate up to two pseudo sector pulses in one servo section. The pseudo sector pulse is
It is output to the hard disk controller 24. In addition,
Since the time information of the pseudo sector pulse is common to all tracks in each zone, it is supplied from the microcomputer 30 to the timing generation circuit 28A only when the heads 12 and 14 seek in different zones.

On the other hand, in the ID portion of the data recorded on the magnetic disk 10, as described above, the logical sector LS is used.
1, LS2, ... Are included in the servo areas SV1, SV2, ..., And the number of split bytes is included (FIG. 13D,
(E), see Table 1).

The hard disk controller 24 reads the data based on the pseudo sector pulse and the information of the ID section. For example, in FIG. 13, logical sector LS2
The case of reading the data of will be described. The hard disk controller 24 uses the pseudo sector pulse (see FIG.
Search for the ID part of the data after the input (see (C)) in order,
If the ID of the logical sector LS2 matches the corresponding one, the FL is checked to see if it is split.
It is recognized by the G section, and further, the SPLIT section recognizes at which byte of the data the data is split (see (E) in the figure).

In this example, since the first half 108 bytes are split, 108 bytes of data in the DATA portion are read first, then the PAD portion is read, and then the servo area S is read.
The reading is interrupted because the V2 servo gate comes.
After the servo gate is completed, the SYNC unit regains the synchronization and the latter 404-byte data reading is restarted.
The same applies to writing. In this way, although the physical sector and the logical sector do not match, the data of the logical sector can be read or written well by utilizing the pseudo sector pulse.

[0038]

According to the above-mentioned prior art, the track is divided into a plurality of zones from the inner circumference to the outer circumference, and the recording density is high on the outer circumference. Therefore, the data transfer rate is from 17.1 to 12.8.
It changes to MBPS (bit / sec). Therefore, in accordance with the corresponding recording frequency (when the modulation method is 1 to 7 RLL, 1/3 of the transfer rate is the highest frequency),
The cutoff frequency (cutoff frequency) of the low-pass filter at the input stage of the R / W controller 18 is switched.

However, in such a method, when there are a plurality of heads, variations in the physical dimensional accuracy of the heads and variations in mounting, and when using a MIG (metal in gap) type head, the gap Dimensional accuracy such as shape and track width, fluctuation of magnetic characteristics including crystal structure of material itself that determines magnetic characteristics of head,
Difference in head signal quality due to difference in flying height due to dimensional accuracy of head, warpage due to flatness of disk surface and stress when clamping disk, magnetic characteristics of disk and partial defect (magnetic or physical defect) , The difference in signal quality due to the difference in recording density of each area divided into zones on the inner and outer circumferences, the difference in external noise depending on the position of the disk (for example, the lower head on the inner circumference is a magnetic noise generated from the spindle motor The reproduction signal is affected by various factors such as variations in the characteristics of each circuit, and the quality of the reproduction signal deteriorates due to variations in output, S / N, and frequency characteristics.

The present invention focuses on these points,
A highly reliable magnetic disk drive device capable of recording / reproducing data on / from a disk on which high-density recording has been favorably performed by reducing the influence of various fluctuation factors without causing a decrease in data transfer rate. The purpose is to provide.

[0041]

A first invention has a function of controlling recording / reproducing of data on / from a magnetic disk, and at least one circuit can change operating conditions.
A media control means including a first memory means for storing a prescribed value indicating this operating condition, and a second means for measuring and storing an optimum value of the prescribed value for each magnetic disk drive device.
Memory means, interface control means for controlling the exchange of data with the host side, spindle control means for controlling the drive of the magnetic disk, actuator control means for controlling the drive of the head,
A system control means for controlling the overall operation is provided, and the system control means stores a predetermined value data of the second memory means in the first memory means at the time of start-up and a predetermined value setting means. When an operating condition is reached, at least one optimum value of the specified values is measured, and specified value resetting means is stored again in the first memory means.

The second invention has a function of controlling recording / reproduction of data to / from a magnetic disk and control of re-execution of reproduction, and at least one circuit can change operating conditions,
A media control means including a first memory means for storing a prescribed value indicating this operating condition, and a second means for measuring and storing an optimum value of the prescribed value for each magnetic disk drive device.
Memory means, and interface control means having a function of controlling data exchange with the host side, including error detection means for detecting data errors, spindle control means for controlling magnetic disk drive,
An actuator control means for controlling the drive of the head and a system control means for controlling the entire operation are provided, and the system control means stores the specified value data of the second memory means in the first memory means at the time of starting. Specified value setting means for storing, and stipulated value for changing at least one of the specified values to a predetermined value and storing again in the first memory means when an error is detected by the error detecting means. And changing means.

In a third invention, the magnetic disk of the first and second inventions records servo information of a sector at a position common to each track, and divides a large number of tracks into a plurality of zones. The number of sectors is set to be the same in each zone, and the number of sectors is set to correspond to the difference between the inner and outer circumferences, and the format is such that data is recorded and reproduced at the multi-transfer rate. It is set to.

[0044]

According to the first invention, at least one circuit of the media control means, for example, the cutoff frequency of the LPF, the level slice circuit, the window adjust circuit, etc.,
The operating conditions such as slice level and window can be changed. Then, optimum values indicating these operating conditions are measured for each driving device at the time of manufacture and stored in the second memory means. Then, at the time of startup, the specified value is stored in the first memory means from the second memory means, and the corresponding circuit of the media control means operates based on this specified value. Since the specified value is set and reset at a predetermined operating condition, for example, every time the starting operation is performed, the operating condition of the corresponding circuit of the media control means is programmable.

According to the second aspect of the invention, when an error is detected in the reproduced data, the specified value of the second memory means is changed. Then, the reproduction of the changed data is executed again. According to the third invention, a large number of tracks on the magnetic disk are divided into a plurality of zones, and the respective prescribed values are set for each zone. Therefore, the operating condition of the corresponding circuit of the media control means is changed for each zone.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a magnetic disk drive according to the present invention will be described below with reference to the accompanying drawings.
The same reference numerals are used for the same components as those of the above-described conventional technique or components corresponding to the conventional technique.

<Overall Configuration> First, the overall configuration will be described with reference to FIG. In the figure, heads 12 and 14 for accessing the magnetic disk 10 of the above-mentioned format are connected to a read / write (R / W) amplifier 16, which reads and writes data. It is connected to an R / W controller 50 that controls writing. This R / W controller 50
On the other hand, is connected to a hard disk controller 52 that controls the exchange of data with the outside.

The hard disk controller 52 is connected by a bus 54 to a gate array 56 for generating a clock and the like and a microcomputer 58 for controlling the operation of the whole, and is connected to a connection terminal 32 by a bus 60. The connection terminal 32 is connected to a personal computer (not shown) on the host side. Furthermore, the hard disk controller 52 and the gate array 5
6 are connected by a bus 62, and the gate array 5
6 and the microcomputer 58 are connected by a bus 64. In addition, the microcomputer 58 and R / W
The controller 50 is also connected by a serial bus 66.

On the other hand, SP for rotating the magnetic disk 10
An SPM driver 36 is connected to the M (spindle motor) 34, and a VCM for moving the heads 12 and 14
A VCM driver 40 is connected to the (voice coil motor) 38. Further, the gate array 56 described above is
It is connected to the SPM driver 36 and the VCM driver 40, respectively. In addition, the SPM 34 and VCM 38 are also connected to the microcomputer 58.

The gate array 28 is provided with a timing generation circuit 28A, in which the servo gate in each zone and the time information of the pseudo sector pulse are set to generate a pseudo sector pulse. . The format of the magnetic disk 10 is as described above, and the time information of the servo gate and the pseudo sector pulse is stored in advance in the memory in the microcomputer 58.

<Structure of Each Part> Next, each part will be described in more detail. [Heads 12, 14] First, the heads 12, 14 will be described. The sliders at the tips of the heads 12 and 14 have a length of 2,04 mm, a width of 1.5 mm, and a thickness of 0.43 m.
A small m (a so-called 50% slider manufactured by TDK Co., Ltd.) is used. Therefore, the weight of the heads 12 and 14 is reduced, the moment of inertia of the entire actuator is reduced, and the average access time is 16 msec or less.

Further, the disk 1 is exposed to an external shock.
In order to prevent the heads 12 and 14 from colliding with 0, a load force is applied. This value also decreases from 9.5 gram force to 5.0 gram force or less with the weight reduction, so the disk 10 and the head 1
The load between 2 and 14 is reduced. Therefore, SPM3
The starting torque of No. 4 is small, and the power consumption at the time of starting when the SPM driver 36 requires the most power is 3.5 watts or less.

[Microcomputer 58] Next, the microcomputer 58 for controlling the entire operation will be described. The microcomputer 58 has a configuration including, for example, a microprocessor unit,
For example, “μPD78356” manufactured by Company C can be used.
The microcomputer 58 includes an arithmetic unit, a storage device,
Timer, pulse width modulation (PWM) circuit, A / D converter,
A D / A converter and the like are included. The pulse width modulation circuit is used to control the speed of the SPM 34 and uses four A
The / D converter is used for detecting the phase of the SPM 34.
Further, four A / D converters are used to measure the burst signals of A, B, C and D in the servo signal described above, and the VCM is used.
A D / A converter is used to control the speed and position of the 38.

With this microcomputer 58,
Management of heads 12 and 14, seek to target track, tracking, speed control of SPM 34, management of tracks and sectors, read / write operation control, controller 50,
52 and the gate array 56 are controlled.

[SPM 34, VCM 38] Next, SPM
As 34, an in-hub type brushless motor is used. The torque is generated by the action of the magnetic field of the coil on the stator side and the magnetic field of the magnet on the rotor side. Next, in the magnetic circuit of the VCM 38, a magnet which is a sintered body of iron neodymium boron and has a high magnetic flux density of BH product of 40 mega gauss Oersted or more is used. Further, it is necessary to reduce the air gap for the purpose of increasing the permeance coefficient. For this reason, the coil is held by three arms outside the magnetic circuit. As a result, only the thickness of the coil is included in the gap of the magnetic circuit, which results in high efficiency.

[SPM driver 36, VCM driver 4
0] Next, referring to FIG. 2, the SPM driver 36,
The VCM driver 40 will be described. As shown in the figure, the SPM driver 36 includes a commutation switch circuit 3 including six MOSFETs for controlling current in both directions in the three-phase motor windings 34U, 34V, 34W of the SPM 34.
6A and the PWM signal is smoothed by the integrator and SPM3
Current control circuit 36 for controlling 4 to the rated speed
It is composed of B and. Commutation switch circuit 36A
Each terminal of is connected to the gate array 56,
4U, 34V, 34W terminals are microcomputer 5
8 is connected to the A / D converter, and the current control circuit 36
The terminal B is connected to the PWM circuit of the microcomputer 58.

When the magnetic disk 10 is started to rotate,
First, from the state in which the heads 12 and 14 are on standby in the shipping area, the windings 34U, 34V and 34W of the SPM 34 are energized by open loop. Then, when the start-up is started, in order to detect the rotational position of the SPM 34, the voltage of each phase of U, V, W is taken into the microcomputer 58 through the A / D converter and measured, and the phase of the winding to be energized The phase information for switching is obtained. Then, the speed signal and the phase signal for controlling at the rated speed are obtained by counting with a timer, and are supplied to the commutation switch circuit 36A via the gate array 56 to rotate the SPM 34 until the rated speed is reached. Pull up.

After the rated rotation is reached, in order to detect the rotational position of the SPM 34, the sector signals on the magnetic disk 10 which are associated in advance with the windings 34U, 34V, 34W are
It is converted into a position signal by resetting with an index signal once per rotation, and the phases to be driven of the windings 34U, 34V, 34W are switched corresponding to the sector. Then, the speed signal for control is compared with a prescribed value to obtain an error signal, and a PWM signal based on this is output to the current control circuit 36B, whereby desired rated rotation control is performed.

Next, the VCM driver 40 will be described. As shown in the figure, the VCM driver 40
An energization control circuit 4 composed of four MOSFETs for controlling the current in both directions at both ends of the voice coil 38A of No. 38.
0A and current feedback amplifier 40C for controlling the current value
And a current control circuit 40B including
Each terminal of the energization control circuit 40A is connected to the gate array 56, and the terminal of the current control circuit 40B is connected to the D / A converter of the microcomputer 58.

When the VCM 38 is driven, the servo signals read by the heads 12 and 14 from the magnetic disk 10 are amplified by the R / W amplifier 16 and further read by the R / W controller 5.
Digital data is obtained at 0 and supplied to the gate array 56. The gate array 56 detects the timing signal of the servo signal data, converts the address information of the gray code into digital data by using this as a reference signal, and sends it to the microcomputer 58 via the bus 54. On the other hand, in the R / W controller 50, the analog levels of the above-mentioned burst signals A, B, C and D are sampled and held at each timing, and the A / W is fed to the microcomputer 58.
It is input after D conversion.

The microcomputer 58 recognizes the positions of the heads 12 and 14 based on these signals, and first calculates the difference from the target position. Then, the current corresponding to the calculation result is supplied to the VCM driver 4 via the gate array 56.
0 is supplied to the energization control circuit 40A. Then, a current corresponding to the voice coil 38A flows, and a seek operation to a target track and a following operation on the track are performed. At the time of startup, control is performed so that the heads 12 and 14 move to the minus 1 track on the outer peripheral side of the magnetic disk 10.

In the configuration example of FIG. 2, the drivers 36,
All of 40 are separately present outside the gate array 56, but since their drivers are constituted by 7 and 5 MOSFETs, they should be integrated as DMOS inside the gate array 56. Good.
This can reduce the number of connections and contribute to downsizing of the device.

[Gate Array 56] Next, the gate array 56 will be described. The gate array 56 includes a crystal oscillator oscillator circuit, which divides a signal having an oscillation frequency of 30 MHz to obtain a reference clock of the R / W controller 50, a clock of the hard disk controller 52, and a clock of the microcomputer 58. There is. Also,
The burst signal SYNC and the erase gap GAP in the servo signal described above are respectively detected, and a track transition detection timing signal is generated based on this timing. Then, based on this, the index recognition signal INDEX indicating one sector per one rotation of the disk and the 11-bit gray code set for each track for rough positioning in the track direction are detected, and the parallel bus is detected. It also has a function of sending to the microcomputer 58 via 54.

Further, in order to perform accurate head positioning on a track, burst signals A and B shifted by half a track and burst signals C and D at the track center are generated and sampled and held. There is also a function to send the timing signal of R to the R / W controller 50.

Further, the timing signal generated by the microcomputer 58 for controlling the SPM 34 is changed to SP.
Six FEs of the commutation switch circuit 36A of the M driver 36
Output to T. In addition, the D / A conversion value given from the microcomputer 58 for controlling the VCM 38 is V
The current is supplied to the current feedback loop of the current control circuit 40B of the CM driver 40 to switch the current direction. In addition, the gate array 56 also includes a circuit of a portion in which the microcomputer 58 cannot process in time due to the measurement of the rotation accuracy of the disk rotation speed and the data exchange in the R / W controller 50.

[Hard Disk Controller 52] Next, the hard disk controller 52 will be described. The hard disk controller 52 functions as a read data cache buffer, write data temporary storage, timing control, etc. in response to data read (read) and write (write) commands from an external device (not shown). In addition, it has an interface with an external device, that is, a host, and in particular, has a function of exchanging data for which the microcomputer 58 cannot process in time. The hard disk controller 52 has a built-in RAM 26 memory 26 and is also connected to a 16-bit parallel bus 54.
Further, it is connected to the gate array 56 by an 8-bit parallel bus 62. The memory 26 may be provided externally as in the prior art, but it is advantageous to incorporate the memory 26 for integration and miniaturization.

[Bus 54, 62, 64, 66] Next, the bus configuration of this embodiment will be described. The hard disk controller 52, the gate array 56, and the microcomputer 58 are connected by a parallel bus 54 for address setting of 16 bits. Data transmission / reception among the hard disk controller 52, the gate array 56, and the microcomputer 58 is performed bidirectionally via the gate array 56 by 8-bit data buses 62 and 64. This data bus 62,6
Data of 4 is 8 bits or more because data is transmitted and received in a relatively short instruction cycle.

The microcomputer 58 sets addresses on the bus 54 while polling the hard disk controller 52 and the gate array 56, and sends information from the host written in the registers of the hard disk controller 52 via the buses 62 and 64. Or a timing signal from the gate array 56 via the bus 64.

On the other hand, the bus 66 between the R / W controller 50 and the microcomputer 58 stores, in a programmable register, serially set data including data, clocks, and chip select signals, as described later. It is for. The data can be switched at a speed of about 347 μsec per sector at the earliest when calculated from the fact that there are 48 sectors per revolution at a disk rotation speed of 3600 rpm. Therefore, the bus 66 is a serial bus. This is more convenient for downsizing the device because the area of the substrate is smaller and the number of pins of the integrated circuit is smaller.

[R / W Controller 50] Next, a configuration example of the R / W controller 50 will be described with reference to FIG. The circuit shown in the figure is a circuit of a portion corresponding to one channel. That is, in the present embodiment, the heads 12 and 14 are alternately switched by the R / W amplifier 16 and driven in a time-division manner.
The R / W controller 50 reads / writes data from / to No. However, it is also possible to provide an R / W controller for each head. FIG. 4 shows the signal waveform of the main part.

In the figure, the data read side will be described first. The analog signal output from the R / W amplifier 16 is input to the AGC circuit 100, where it is programmable (described later) regardless of the input amplitude. It is controlled to a constant amplitude. The signal after gain control is input to the LPF / equalizer 102, where high-frequency noise components are programmably cut based on the cutoff frequency set for each zone in Table 1. In addition, the high range is emphasized for each zone by the equalization process (cosine equalization).
The signal shown in (A) is obtained (in the figure, the dotted line shows the slice level). On the one hand, this signal is full-wave rectified by the full-wave rectifier circuit 104, and further, the sample hold circuit 1
Supplied to 10. Here, the sample and hold of the signal is performed based on the sample timing signal input from the gate array 56, and the four burst signals A, B, C, D in the servo signal described above are converted into the microcomputer 58.
Sent to.

The signal of FIG. 4 (A) also corresponds to the differentiating circuit 10
6 is differentiated to be as shown in FIG. 6C, and is pulsed by the zero cross detector 112 to obtain the pulse signal shown in FIG. The signal shown in FIG. 9A is further supplied to the level slice circuit 108, where it is sliced at a programmable level to obtain the signal shown in FIG. Both of these signals (B) and (D) are input to the read pulse generator 114, where AND
And the read data shown in FIG. 7E is obtained.

On the other hand, the R / W controller 50 has
Two PLL circuits on the read side and the write side are provided. The write side PLL circuit 116 includes phase comparators 118 and L.
It is composed of a PF / charge pump 120 and a VCO 122, and a frequency division signal of a frequency divider 124 whose frequency division ratio is programmable is inputted to the phase comparator 118. The read side PLL circuit 126 includes a phase comparator 128, an LPF / charge pump 130, and a VCO 132.
The output signal of the PLL circuit 116 is input to the phase comparator 128.

As shown in Table 1 above, the data transfer rate is different in each zone of each track. For this reason, it is necessary to change the basic frequency at the time of decoding and encoding the data in accordance with the transfer rate. Therefore, the reference clock supplied from the gate array 56 is frequency-divided by the programmable frequency divider 124 into a frequency corresponding to each zone and input to the phase comparator 118 of the PLL circuit 116, and the output of the PLL circuit 116 is output. By inputting it to the phase comparator 128 of the other PLL circuit 126, the signal of the fundamental frequency corresponding to each zone is generated.

The above-mentioned read data is input to the window adjust circuit 134 in which the center value of the window is set in a programmable manner, processed there by the window pulse, and supplied to the 1 to 7 decoder 136.
The 1 to 7 decoder 136 decodes the signal based on the output clock of the PLL circuit 126 corresponding to the transfer rate of each zone. As a result, NRZ (No
The final read data decoded to Return to Zero is obtained.

Next, the data writing side will be described. The read data output from the read pulse generator 114 is input to the address mark detector 138, where the head of the ID portion shown in FIG. The address mark on the copy is detected. Then, with this as a reference, the NRZ write data is input to the 1 to 7 encoder 140 from the outside and the encoding is performed. At this time, the PLL circuit 116
Output clock is used. The encoded write data is input to the write precompensation circuit 132 which shifts the timing in advance so as to correct the peak shift expected from the magnetic characteristics depending on the data interval, and the processing by the write precompensation circuit 132 is programmable to perform R / W. It is output to the amplifier 16. Then, after being amplified by the R / W amplifier 16, the magnetic disk 1 is supplied to the heads 12 and 14.
It is recorded in the corresponding sector of 0. Furthermore, the PLL circuit 1
The output sides of 16 and 126 are connected to the input side of the clock generator 146, whereby the RR clock (read reference clock: clock for reading data).
Is being generated.

In the R / W controller 50 configured as described above, six programmable AGs are configured.
C circuit 100, LPF / equalizer 102, level slice circuit 108, frequency divider 124, window adjust circuit 134, write precompensation circuit 142
Are configured to perform their respective programmable operations based on the data stored in the programmable register 144. The data is stored in the programmable register 144 by transferring the data for the programmable operation, the serial data composed of the clock and the chip select signal, by the microcomputer 58 via the bus 66. There is.

The data stored in the programmable register 144 is, for example, about 7 bits.
Each circuit such as the GC is supplied in a required signal form. In this embodiment, the AGC circuit 1
00, LPF / equalizer 102, and level slice circuit 108 are converted into analog signals and supplied. In addition, the window adjustment circuit 134,
The write pre-compensation circuit 142 is supplied as a tap switching signal for those delay lines.

[Main part for performing programmable operation] Of the above parts, the main part for performing the programmable operation of this embodiment is shown in FIG. In the figure, in the R / W controller 50, the AGC circuit 100,
LPF / equalizer 102, level slice circuit 10
8, frequency divider 124, window adjusting circuit 134,
The write precompensation circuits 142 are connected to the programmable registers 144, respectively. The programmable register 144 has a data storage area for each of these circuits, and the data corresponding to each area is stored.

For example, the optimum signal amplitude value is stored in the area corresponding to the AGC circuit 100. An optimum cutoff frequency value is stored in a region corresponding to the LPF / equalizer 102. An optimum slice level value is stored in the area corresponding to the level slice circuit 108. Frequency divider 1
A value of a prescribed frequency division ratio is stored in the area corresponding to 24. An optimum window center value (the center of the window with respect to the read reference clock on the time axis) is stored in the area corresponding to the window adjusting circuit 134. Write pre-compensation circuit 142
An optimal timing deviation value is stored in the area corresponding to. It should be noted that each of these values corresponds to each head 12, 14.
It is set for each sector, each sector, and each zone.

Next, the hard disk controller 52 includes an error detector 52A, which detects an error in the data read from the magnetic disk 10. The microcomputer 58 has a prescribed value setting unit 5
8A, a resetting section 58B at startup, and a specified value changing section 58C are included. The specified value setting unit 58A is for storing in the programmable register 144 the specified value for performing the above-described programmable operation, which is measured at the manufacturing stage (hereinafter referred to as "initial specified value"). This initial specified value is recorded in the minus first track of the magnetic disk 10 or the EEPROM 70, for example. The startup resetting section 58B is for measuring an optimum value with respect to a predetermined initial specified value at the startup of the drive device, and resetting the optimum value in the programmable register 144. The specified value changing unit 58C uses the error detection unit 52A of the hard disk controller 52 for the data read from the magnetic disk 10.
When any error is detected in, the specified value is changed, and the data is read again after the change. Further, the ROM (not shown) of the microcomputer 58 stores the provisional prescribed value required for starting.

[Measurement Method of Initial Prescribed Value] Next, a method of measuring the initial prescribed value for performing the above-described programmable operation at the time of manufacturing will be described. First, the AGC circuit 10
For 0, the test data of a single pattern is written and read, and the amplitude of the read signal is measured. Then, the control amount for making this amplitude a predetermined value is set as an initial specified value. This work is performed on each head 12,
14 and each zone area to obtain initial specified values.

Next, regarding the LPF / equalizer 102, there is a relation that if the cutoff frequency of the filter and the equalizer is increased, the signal jitter increases, and conversely if the cutoff frequency is decreased, the peak shift of the signal increases. In addition, variations in the characteristics of ICs that make up the circuit also affect. Therefore,
There will be the best points for both to cross. Therefore, writing and reading of test data having a pattern in which peak shift is likely to occur are performed while switching the frequency of the test data and the cutoff frequency of the filter and the equalizer, respectively, and measure the jitter and the peak shift, respectively. Then, the cutoff frequency at which the two cross is set as the initial specified value. This work is performed for each head 12, 14.
And for each zone area to obtain initial specified values.

Next, in the level slice circuit 108, when the slice level (dotted line in FIG. 4A) is lowered, unnecessary data is generated (see the dotted pulse in FIG. 4E) and the slice level is raised. There is a relationship that data is missing. Therefore, while changing the slice level value, write and read with multiple patterns of test data, etc., measure until a data error occurs in both directions, and initialize the intermediate value of the level where the error in both directions occurs. Use the specified value. This operation is performed for each of the heads 12 and 14 and each zone area to obtain initial specified values.

Next, regarding the window adjust circuit 134, similarly, a data error occurs even if the window center value is increased, and a data error occurs even if the window center value is delayed. In other words, a data error occurs regardless of whether the window pulse is moved forward or backward on the time axis. In addition, variations in the characteristics of ICs that make up the circuit also affect. For this reason, while changing the window center value, write and read with test data of a predetermined pattern of a single frequency, measure until a data error occurs in both directions, and measure in the middle of the window time when an error occurs in both directions. The value is the initial value. This operation is performed for each of the heads 12 and 14 and each zone area to obtain initial specified values.

Next, regarding the write precompensation circuit 142, the magnetic disk 10 and the heads 12, 1
Since the specified value is determined by the characteristic of 4,
2 and 14 are obtained for each zone to obtain an initial specified value. Next, with respect to the frequency divider 124, since a prescribed frequency division ratio exists in each zone, that value becomes the initial setting value. The initial specified value obtained for each drive unit as described above is the minus one track outside the use area of the magnetic disk 10 corresponding to the time of manufacture (or factory shipment), or EEPRO.
Written to M70.

<Overall Operation> Next, the overall operation of the above embodiment will be described. [Acquisition and Setting of Initial Prescribed Value at Power-on] First, the operation of taking in the initial prescribed value used for the programmable operation will be described with reference to the flowchart of FIG. The flowchart of FIG. 6 is executed during the operation of the entire driving device (see FIGS. 7 and 8 described later).
The same).

In the case of loading the initial specified value from the magnetic disk 10. In this case, first, the provisional specified value stored in advance in the ROM (not shown) in the microcomputer 58 before the motor is started is programmable by the R / W controller 50. It is stored in the register 144. The provisional stipulated value tentatively stipulates the operation of the R / W controller 50 when reading the initial stipulated value from the minus one track of the magnetic disk 10.

Next, as described above, the SPM 34,
When the magnetic disk 10 is started by the SPM driver 36 and the specified rotation speed is reached (step S10 in FIG. 6),
First, the heads 12 and 14 are moved to the minus 1 track on the outer peripheral side of the disk outside the used area (step S12),
After the arrival, the initial specified value data written in the minus 1 track is read (step S14). This data is sent from the R / W amplifier 16 and the R / W controller 50 to the hard disk controller 52, and then the bus 6
2, sent to the microcomputer 58 via the gate array 56 and the bus 64 (step S16).

In the microcomputer 58, the prescribed value setting section 58A outputs the initial prescribed value data to the programmable register 144 of the R / W controller 50 via the bus 66, and the prescribed value data corresponding to the corresponding area. Are respectively stored (step S1)
8). These specified values are supplied to each circuit that operates in a programmable manner. As a result, the R / W controller 50
Then, the R / W control is performed based on the initial specified value.

In the case of fetching the initial specified value from the EEPROM 70. When the EEPROM 70 is connected to the microcomputer 58 and the initial specified value data is stored therein (see FIG. 5), the EEPROM 7 is started before starting the motor.
The initial prescribed value data is read from 0 and stored in the programmable register 144 (step S20).

[Resetting of stipulated value when motor is restarted after power-on] Next, the operation of resetting the initial stipulated value set at power-on as described above when the motor is restarted will be described with reference to FIG. This will be described with reference to the flowchart of FIG.
It should be noted that the operation shown in the figure shows an example in which the initial prescribed value of the level slice circuit 108 is reset.
For portable type personal computers,
There is an operation mode in which the motor drive of the magnetic disk drive is temporarily stopped after the power is turned on to save power. When the motor is restarted in such a case, the following operation is performed.

The initial specified values for performing the programmable operation described above are optimally set at the time of manufacturing.
Therefore, under the actual use condition of the drive device, the optimum value may deviate due to the influence of aging, temperature change and the like. Therefore, an optimum specified value is obtained for those required when the motor of the drive device is restarted, and resetting is performed. This resetting operation is executed by the startup resetting unit 58C of the microcomputer 58.

In this case, if the measurement for resetting takes a long time, the performance of the driving device is deteriorated. Therefore, the measurement is simplified. Further, in this measurement, since the user may be writing data in the usable area of the magnetic disk 10, a portion other than the usable area,
That is, the minus 1 track on the outer circumference side of the disk and the plus 1 track on the inner circumference side of the disk are used.

When the drive unit is activated (step S
30) First, the heads 12 and 14 are moved to the minus 1 track (step S32). Next, by using the empty area in which the initial specified value of the minus 1 track is not recorded, the slice level value is changed for each sector in the same manner as when the initial specified value is measured. Writing and reading are performed to detect a data error (step S34). Then, the intermediate value at which an error has occurred is measured in both directions of the level (step S3).
6).

Next, the heads 12 and 14 are moved to the plus 1 track on the inner circumference side of the disk and the same measurement is performed to measure the intermediate value of error occurrence (steps S38 and S4).
0, S42). Then, the initial setting values are reset from the measured values obtained on each of these tracks (step S44). For example, if the measured value is compared with the initial set value, the range of change due to the use conditions is predicted in advance, and if the range is confirmed and the initial prescribed value is reset, the probability of error decreases. Reset the default value for each zone from this value. In addition, the optimum value of each zone is predicted from the measured value obtained on each track from an appropriate prediction method or statistical tendency, and the specified value is reset based on this. The same applies to resetting the specified values of circuits other than the level slice circuit 108.

[Data Writing / Reading Operation] Next, after the specified value of the programmable register 144 of the R / W controller 18 is set as described above, access to the magnetic disk 10 is requested by the host side. Will be done accordingly. This operation is performed by A of the R / W controller 18.
GC circuit 100, LPF / equalizer 102, level slice circuit 108, frequency divider 124, window adjust circuit 134, write precompensation circuit 14
2 is almost the same as the above-described prior art, except that 2 operates based on the specified value stored in the programmable register 144.

When the host computer (not shown) accesses the magnetic disk 10 via the connection terminal 32, the VCM driver 40 drives the VCM 38 based on the instruction from the microcomputer 58. Then, the heads 12 and 14 move to access a required address on the magnetic disk 10, and write data is written and read data is read via the R / W amplifier 16. The SPM 34 is the SPM driver 3
It is controlled by 6 to rotate at a constant speed.

In this case, the servo areas SV1 and SV
As described above, the V2, ... Servo pulses are located at the same position in time on any track of the magnetic disk 10. Therefore, a complicated circuit is not required for generating the window for detecting the servo signal. Further, the servo pulse can be accurately detected regardless of the position of the heads 12 and 14, and the rotation control of the SPM 34 can be performed well. Further, the servo pulse detection by the predictive control of the seek of the heads 12 and 14 is similarly accurately performed.

Next, when accessing the magnetic disk 10, the time information from the servo pulse of the pseudo sector pulse in the zone to which the corresponding track belongs is transferred from the microcomputer 58 to the register 28B of the timing generation circuit 28A of the gate array 56. Set. In the timing generation circuit 28A, the time from the servo gate is set in the counter 28C according to the contents of the register 28B and the counting operation is performed to generate up to two pseudo sector pulses in one servo section. The pseudo sector pulse is
It is output to the hard disk controller 52. In addition,
Since the time information of the pseudo sector pulse is common to all tracks in each zone, it is given from the microcomputer 58 to the timing generation circuit 28A only when the heads 12 and 14 seek in different zones.

On the other hand, in the ID portion of the data recorded on the magnetic disk 10, as described above, the logical sector LS is used.
1, LS2, ... Are included in the servo areas SV1, SV2, ..., And the number of split bytes is included (FIG. 13D,
(E), see Table 1).

In the hard disk controller 52, data is read based on the pseudo sector pulse and the information of the ID section. For example, in FIG. 13, logical sector LS2
The case of reading the data of will be described. The hard disk controller 52 uses the pseudo sector pulse (see FIG.
Search for the ID part of the data after the input (see (C)) in order,
If the ID of the logical sector LS2 matches the corresponding one, the FL is checked to see if it is split.
It is recognized by the G section, and further, the SPLIT section recognizes at which byte of the data the data is split (see (E) in the figure).

In this example, since the first half 108 bytes are split, 108 bytes of data in the DATA portion are read first, then the PAD portion is read, and then the servo area SV is read.
The reading is interrupted because the second servo gate comes. After the servo gate is finished, resynchronize again in the SYNC section,
Resume reading of the last 404 bytes of data. The same applies to writing. In this way, although the physical sector and the logical sector do not match, the data of the logical sector can be read or written well by using the pseudo sector pulse.

[Default value changing operation when error is detected] Next,
During the above operation, the hard disk controller 52
In the error detection unit 52A, the error is detected in the read data. When an error is detected, the specified value changing operation shown in the flowchart of FIG. 8 is executed.

When an error is detected in the read data (step S50 in the figure), this is transmitted from the error detection unit 52A of the hard disk controller 52 to the specified value change unit 58C of the microcomputer 58. Then,
The specified value changing unit 58C first changes the specified value for the level slice circuit 108 stored in the programmable register 144 of the R / W controller 50 (step S).
52). It should be noted that this changed value is set in advance and stored in the microcomputer 58, and is a value that changes the currently set slice level in both positive and negative directions. After that, the R / W controller 50
Then, the corresponding data is read again (step S54).

As a result of the retry, if an error is detected again in the read data (step S56), the fact is transmitted from the error detecting section 52A to the specified value changing section 58C. Then, the specified value changing unit 58C changes the specified value for the window adjusting circuit 134 to a value stored in advance (step S58). This causes the window to expand from the currently set value in both directions. Then, the R / W controller 50 again reads the corresponding data (step S60).

As a result of the retry, if an error is detected again in the read data (step S62), the fact is transmitted from the error detecting section 52A to the specified value changing section 58C. Then, the specified value changing unit 58C causes the specified value for the LPF / equalizer circuit 102 to be stored in advance, plus,
Change to a value that changed in both negative directions (step S
64). Then, the R / W controller 50 again reads the corresponding data (step S66).
As a result of the retry, if an error is detected again in the read data (step S68), this is notified to the host side through the connection terminal 32 (step S7).
0).

<Effects of Embodiment> As described above, according to this embodiment, the following effects are obtained. (1) Since the R / W controller 50 operates in a programmable manner based on the specified value set for each device, the influence of various parts existing between the devices and variations in the assembled state is reduced, and the magnetic property is excellent. Data can be written to and read from the disc. (2) When an error occurs, by changing the specified values and reading the data again, the final error occurrence can be favorably reduced. (3) Further, the above functions are realized by the programmable register in the R / W controller and the software in the microcomputer, and the programmable setting operation is performed by using the serial bus. There is no particular inconvenience in terms of mounting area, and there is no hindrance to reduction in size and weight.

(4) It is possible to reduce the defective rate at the manufacturing stage caused by variations in parts and assembly. (5) Further, between the ICs configuring each unit, a bus that requires high-speed data transfer is a parallel bus having different addresses and data, and a bus that does not require high-speed data transfer is a serial bus. , The number of wirings and the number of IC pins are reduced, and the size is further reduced without lowering the performance.
The weight can be reduced.

<Other Embodiments> The present invention is not limited to the above embodiments, and includes, for example, the following. (1) In the above-described embodiment, which of the circuits included in the R / W controller 50 is to be programmable-operated is arbitrary, and may be appropriately set as necessary. The same applies to changing the specified value of which circuit when an error is detected. For example, the specified values of the two circuits may be changed at the same time. In addition, various design changes can be made so as to achieve the same operation.

(2) As a preferred application example of the present invention, 5
The disk diameter of the built-in battery-operated palmtop type personal computer or notebook type personal computer that is driven in the low voltage range of about 3V is 2.5.
~ 1.8 inch small magnetic disk drive (H
DD), but it is also applicable to other disc diameters. (3) Further, as the magnetic disk, the above-mentioned prior art is a preferable example, but in addition, for example, Japanese Patent Publication No. 59-90.
No. 1, JP-A-58-88874, JP-A-55-1.
It is also applicable to the magnetic disk disclosed in Japanese Patent No. 25578. (4) In the above-described embodiment, the preset value is reset at the time of startup, but it may be performed in a desired operating condition, for example, every 1 hour after startup.

[0112]

As described above, the magnetic disk drive device according to the present invention has the following effects. (1) Since the specified value, which is the reference for the control operation for recording (writing) and reproducing (reading) data, is reset as necessary when the device is started, the data transfer speed is not reduced. Data can be recorded / reproduced favorably on the disc by reducing the influence of various fluctuation factors such as temperature. (2) When an error is detected, the specified value is changed and the data is reproduced again. Therefore, the data can be reproduced more favorably.

(3) Servo information is provided at the same position on each track, the number of logical sectors is provided corresponding to the difference between the inner and outer circumferences of the tracks, and data is recorded on the magnetic disk which is accessed using pseudo sector pulses. Since the reproduction control is programmable, it is possible to reduce the influence of various fluctuation factors and perform recording / reproduction of data with respect to a disk on which high-density recording is favorably performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a magnetic disk drive device according to the present invention.

FIG. 2 is a circuit diagram showing a motor drive portion of the embodiment.

FIG. 3 is a block diagram showing a configuration example of an R / W controller of the embodiment.

FIG. 4 is a time chart showing signal waveforms of main parts leading to read data generation in the R / W controller.

FIG. 5 is an explanatory diagram showing a main part of the embodiment.

FIG. 6 is a flow chart showing an operation of setting an initial prescribed value in the embodiment.

FIG. 7 is a flowchart showing a preset value resetting operation in the embodiment.

FIG. 8 is a flowchart showing an operation of changing a specified value when an error is detected in the embodiment.

FIG. 9 is an explanatory diagram showing a general magnetic disk and a head.

FIG. 10 is an explanatory diagram showing an example of a servo signal.

FIG. 11 is an explanatory diagram showing allocation of logical sectors of a magnetic disk according to the prior art.

FIG. 12 is an explanatory diagram showing allocation of logical sectors to servo sections in the prior art.

FIG. 13 is an explanatory diagram showing a detailed format example of a logical sector in the prior art.

FIG. 14 is a block diagram showing a magnetic disk drive device in the prior art.

[Explanation of symbols]

10 ... Magnetic disk (second memory means), 12, 14
... head, 16 ... R / W amplifier, 26 ... memory, 56 ...
Gate array, 28A ... Timing generation circuit, 28B ...
Register, 28C ... Counter, 32 ... Connection terminal, 34 ...
SPM, 36 ... SPM driver (spindle control means), 38 ... VCM, 40 ... VCM driver (actuator control means), 50 ... R / W controller (media control means), 52 ... Hard disk controller (interface control means), 52A ... Error detection unit (error detection means), 5
4, 60, 62, 64, 66 ... Bus, 58 ... Microcomputer (system control means), 58A ... Specified value setting section (specified value setting means), 58B ... Startup resetting section (specified value resetting means), 58C ... Specified value changing section (specified value changing means), 70 ... EEPROM (second memory means), 100 ... AGC circuit, 102 ... LPF / equalizer, 108 ... Level slice circuit, 134 ... Window adjust circuit, 142 ... Write Precompensation circuit, 124 ... Divider, 144 ... Programmable register (first memory means), LS1, LS2, LS3 ...
Logical sector, S1, S2, S3 ... Physical sector, SV1,
SV2, SV3 ... Servo area, Z1, Z2, Z3 ... Zone, ΔS1, ΔS2, ΔS3 ... Servo section.

[Procedure amendment]

[Submission date] March 2, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 2

[Correction method] Change

[Correction content]

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

[0007] Therefore, thought both type scheme to take advantage of, is for example, those patent applications as Japanese Patent Application No. 4-1317 1 No. 3. The allocation of physical sectors of the magnetic disk according to this prior art is similar to that of the prior art in FIG. 10, and 48 servo areas SV1, SV2, SV3, ..., SV48 are radially provided at appropriate intervals. Physical sectors S1, S2, S3 between them ...
Is also the same as the conventional one. As described above, the servo signal follows the conventional general sector servo system, the temporal position of the servo signal is the same on the inner and outer circumferences of the track, and the servo signals of the servo areas SV1, SV2 ,. , S2, ... The positions are synchronized. Therefore, the trailing edge of the servo gate is the logical sector S1, S
2, ... has begun.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0041

[Correction method] Change

[Correction content]

[0041]

SUMMARY OF THE INVENTION The first invention has a function of controlling the data recording and reproduction on the magnetic disk, one circuit also less can be changed operating conditions, the operating conditions Media control means including first memory means for storing the specified value, second memory means for measuring and storing the optimum value of the specified value for each magnetic disk drive, and data for the host side The system control means includes interface control means for controlling transfer, spindle control means for controlling magnetic disk drive, actuator control means for head drive control, and system control means for overall operation control. Is a specified value for storing the specified value data of the second memory means in the first memory means at the time of startup. A constant section, and characterized in that it comprises a specified value resetting means for re-stored in the first memory means to measure least one optimum value even in the specified value when it becomes and Activity a predetermined To do.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction content]

[0042] The second invention has a function of controlling the recording playback and reproduction of the re-execution of data to the magnetic disk, one circuit also less can be changed operating conditions, shows the operating conditions Media control means including a first memory means for storing a prescribed value, second memory means for measuring and storing an optimum value of the prescribed value for each magnetic disk drive, and data exchange with the host side Interface control means including error detection means for detecting data errors, spindle control means for magnetic disk drive control, actuator control means for head drive control, and System control means for performing operation control, and the system control means is configured to operate when the second memory is activated. Changes and specified value setting means for storing the stage of the specified value data in said first memory means, the least a predetermined value the one also of the specified value when the error detection is performed by said error detection means And a specified value changing means for re-storing in the first memory means.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0085

[Correction method] Change

[Correction content]

[0085] Next, the window adjustment circuit 134, similarly, the data error occurs even faster window center value, a relationship data errors even at slow window center value occurs. In other words, a data error occurs regardless of whether the window pulse is moved forward or backward on the time axis. In addition, variations in the characteristics of ICs that make up the circuit also affect. For this reason, while changing the window center value, write and read with test data of a predetermined pattern of a single frequency, measure until a data error occurs in both directions, and measure in the middle of the window time when an error occurs in both directions. The value is the initial value. This operation is performed for each of the heads 12 and 14 and each zone area to obtain initial specified values.

Claims (3)

[Claims] 1. A first memory means having a function of controlling recording / reproducing of data to / from a magnetic disk, wherein at least one circuit can change an operating condition, and stores a prescribed value indicating the operating condition. A second memory means for measuring and storing the optimum value of the specified value for each magnetic disk drive, an interface control means for controlling data exchange with the host side, A spindle control means for controlling the drive of the disk, an actuator control means for controlling the drive of the head, and a system control means for controlling the overall operation are provided, and the system control means stores the second memory means at startup. Specified value setting means for storing specified value data in the first memory means, and a predetermined operating condition And a prescribed value resetting means for measuring at least one optimum value of the prescribed values and re-storing it in the first memory means. 2. A function of controlling recording / reproduction of data to / from a magnetic disk and re-execution of reproduction, at least 1
The operating conditions of the two circuits are changeable. Media control means including a first memory means for storing a specified value indicating the operating condition, and an optimum value of the specified value are measured for each magnetic disk drive device. A second memory means for storing the data, an interface control means having a function of controlling the exchange of data with the host side and including an error detecting means for detecting an error in the data, and a spindle control for controlling the drive of the magnetic disk. Means, an actuator control means for controlling the drive of the head, and a system control means for controlling the overall operation,
The system control means includes a prescribed value setting means for storing prescribed value data of the second memory means in the first memory means at the time of starting, and the prescribed value when the error detection means detects an error. A specified value changing means for changing at least one of the values to a predetermined value and re-storing it in the first memory means. 3. The magnetic disk drive according to claim 1, wherein the magnetic disk records sector servo information at a position common to each track, and divides a large number of tracks into a plurality of zones. The number of sectors is set to be the same in each zone, and the number of sectors is set to correspond to the difference between the inner and outer circumferences, and the format is such that data is recorded and reproduced at the multi-transfer rate. A magnetic disk drive device characterized by being set to.