JPH06111032A - Microcomputer - Google Patents

Abstract

PURPOSE:To easily execute rewriting and erasure of a program in a flash memory in a state mounted to a printed board by providing a serial input terminal and an SIO (serial data communication) circuit. CONSTITUTION:This microcomputer is provided with an input terminal 21 of a data rewriting permitting signal, an input terminal 22 of serial data, and an SIO circuit 23 for executing a series-parallel conversion of data inputted to the terminal 22. The SIO circuit 23 includes a receiving shift register 24 for the series-parallel conversion, and a receiving buffer 25 for storing temporarily received data. In such a state, the SIO circuit 23 converts series data inputted to the input terminal 22 to parallel data, and transfers the data to a command latch 14, an address latch 11, or a data latch 13 used by a control circuit 3 or a W-E-R(write-erasure-readout) circuit 2 under the control of the control circuit 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer incorporating a flash memory.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing the main part of a conventional one-chip microcomputer incorporating a flash memory.

In the drawing, reference numeral 1 is a read-only memory, that is, flash memory, which is capable of collectively erasing electrical writing.
Is a write-erase-read circuit (hereinafter, W) for reading, erasing and writing to the flash memory 1.
-E-R circuit. ) 3 is a control circuit for controlling the W-E-R circuit 2 and the like, 4 is an input / output port connected to the address bus 5, and 6 is an input / output port connected to the data bus 7. The address bus 5 and the data bus 7 are also connected to a central processing unit (CPU, not shown).

Further, 11 is an address latch for latching address data on the address bus 5, 12 is an automatic address generation circuit for generating a large number of continuous address data,
Reference numeral 13 is a data latch for latching data on the data bus 7, 14 is a command latch for latching a command on the data bus 7, 33, 34, 36 to 39 are gates, 35 is an address input of the WER circuit 2. It is a switch for switching.

Next, the operation will be described. First, the operation when writing data to the flash memory 1 will be described. In this case, first, a command designating writing and write data are sequentially applied to the input / output port 6 from the outside. Further, the write address is given to the input / output port 4.

When a command is given to the input / output port 6, the control circuit 3 opens the gate 39, and further sequentially opens the gates 36 and 37. As a result, the command is transferred to the command latch 14 and the write data is transferred to the data latch 13 via the data bus 7. Further, the control circuit 3 opens the gates 38 and 34, and the write address is
It is transferred to the address latch 11 via the address bus 5.

Next, the control circuit 3 connects the switch 35 to the address latch 11 side in accordance with the content of the command and outputs W.
A write control signal is supplied to the E-R circuit 2. WE-
The R circuit 2 transfers the data latched in the data latch 13 to the address latch 11 according to the write control signal.
The flash memory 1 is written according to the write address latched in.

The block erase of the flash memory 1 is executed as follows. First, a command for designating block erase is externally given to the input / output port 6. In addition, a start address indicating the start address of the block erase target address is given to the input / output port 4.

The control circuit 3 controls the gate 3 when a command for designating block erase is input to the input / output port 6.
9 is opened, and further the gate 36 is opened. As a result, the command is transmitted via the data bus 7 to the command latch 14
Latched on. Further, the control circuit 3 includes gates 39 and 3
Open 3 Then, the start address is transferred to the address automatic generation circuit 12 via the address bus 5.

Next, the control circuit 3 connects the switch 35 to the address automatic generation circuit 12 side in accordance with the content of the command, and gives a control signal to the WER circuit 2 and the address automatic generation circuit 12. The address automatic generation circuit 12 continuously generates addresses starting with the address indicated by the start address in response to the control signal, and sequentially generates W-
It is supplied to the E-R circuit 2. In addition, the W-E-R circuit 2
In response to the control signal, as a preparation for block erasing, each address supplied from the automatic address generation circuit 12 is used to write to all addresses in the block of the flash memory 1. When the writing is completed, W-ER
The circuit 2 erases all the addresses in the block.

When rewriting the program after the microcomputer in which the program data is written in the flash memory 1 is mounted on the printed wiring board (printed circuit board), the microcomputer is removed from the printed circuit board and rewritten. The contents of the flash memory 1 are rewritten by the container. Alternatively, the contents of the flash memory 1 are rewritten by supplying data for rewriting through the input / output port 6 with the microcomputer mounted on the printed circuit board.

[0012]

Since the conventional microcomputer having the built-in flash memory is configured as described above, it has the following problems. That is, in the case of rewriting the program in the flash memory 1, according to the method of rewriting by removing the microcomputer from the printed circuit board, the lead wire of the integrated circuit and the pattern of the printed circuit board are removed at the time of removal and remounting. Often damaged. In particular, a microcomputer with a multi-terminal flat package has a high possibility of damage, and it is actually difficult to rewrite a program by this method. Further, according to the method of rewriting while mounted on the printed board, since the input / output port 6 is connected to another circuit on the printed board, the line for supplying rewriting data is also connected to another circuit. As a result, other circuits may be short-circuited or overloaded to other circuits.

The present invention has been made to solve the above problems, and provides a microcomputer capable of easily rewriting a program stored in a flash memory mounted on a printed circuit board. The purpose is to

[0014]

According to a first aspect of the present invention, there is provided a microcomputer including a flash memory, a command latch for holding a command for designating writing or erasing of the flash memory, and write data for the flash memory. A data latch to hold, an address latch to hold an address to be written to or erased from the flash memory, and write data in the data latch to the flash memory or erase the flash memory according to the address data in the address latch W-E- R-circuit and write or erase instruction according to the data in the command latch W-ER
And a control circuit to be supplied to the circuit, and further, serial input terminals for inputting command, address data and write data, and data supplied to the serial input terminals are converted into parallel and supplied to a command latch, an address latch or a data latch. And a serial data communication circuit.

A microcomputer according to a second aspect of the present invention is the microcomputer according to the first aspect of the present invention, further comprising: when the receive shift register provided together with the receive shift register in the serial data communication circuit is not empty, A transmission start prohibition signal generation circuit for outputting a transmission start prohibition signal to the outside is provided.

The microcomputer according to a third aspect of the present invention is the microcomputer according to the first aspect of the present invention, further, in the case where the address data indicates a start address of continuous writing, the start is continued from the start address. An automatic address generation circuit for generating an address and supplying it to the W-E-R circuit is provided.

A microcomputer according to a fourth aspect of the present invention is directed to an address bus through which address data passes, a data bus through which data passes, a plurality of flash memories, and a command for designating writing or erasing to the flash memories. Command latch that holds the data, multiple data latches that hold the write data to the flash memory, multiple address latches that hold the write or erase target address of each flash memory, and the flash memory according to the address data in the address latch. A plurality of W-E-R circuits for writing data in the data latch or erasing the flash memory; a control circuit for giving a write or erase instruction to the W-E-R circuit according to the data in the command latch; A serial input terminal for inputting address data and write data, a serial data communication circuit for parallel-converting data supplied to the serial input terminal and supplying the data to a command latch, an address latch or a data latch, and each W-E-R circuit One of the WE
-A memory access prohibition circuit that prohibits the CPU from accessing the flash memory when the R circuit is accessing the corresponding flash memory, and a command latch or address latch from the serial data communication circuit via the address bus or the data bus. Alternatively, it is provided with a bus access prohibition circuit that prohibits access to the address bus and data bus of the CPU when data is being transferred to the data latch.

[0018]

According to the first aspect of the invention, the serial data communication circuit converts serial data input to the serial input terminal into parallel data, and under the control of the control circuit, the control circuit or the W-E-R circuit. Transfer data to the command latch, address latch or data latch used by the.

The reception shift register and the reception buffer according to the second aspect of the present invention pre-receives data relating to data rewriting from the outside, and shortens the time required for data rewriting. Further, the transmission start prohibition signal generation circuit is
Prevents overwriting of data in the receive shift register.

According to the third aspect of the present invention, the automatic address generation circuit generates a continuous address to be rewritten when rewriting continuous address data in the flash memory.

In the duplicated flash memory and W-E-R circuit, and the memory access prohibition circuit and the bus access prohibition circuit in the invention of claim 4, one flash memory is the object of data rewriting or erasing. The CPU allows access to other flash memory without competing with its operation.

[0022]

【Example】

Example 1. FIG. 1 is a block diagram showing the main part of a one-chip microcomputer incorporating a flash memory according to an embodiment of the present invention. In the figure, 21 is an input terminal for a data rewrite permission signal, 22 is an input terminal for serial data (serial input terminal), and 23 is a serial data communication circuit that performs serial-parallel conversion of data input to the input terminal 22 (hereinafter, referred to as SIO circuit) and includes a reception shift register 24 for serial-parallel conversion and a reception buffer 25 for temporarily storing received data.

Reference numeral 26 is a transmission start prohibition signal generation circuit (hereinafter referred to as BUSY circuit), and 27 is an output terminal of a transmission start prohibition signal (hereinafter referred to as BUSY signal). Others are the same as those shown in FIG. 8 with the same reference numerals.

Next, the operation will be described. First, the writing of data to a certain address in the flash memory 1 will be described. In this case, SIO via the input terminal 22
As shown in FIG. 2, the serial data supplied to the circuit 23 is composed of command data, upper address data, lower address data, and write data. Each data has a length of 8 bits, for example. Further, as a communication method for transferring each data, an asynchronous method with a start bit and a stop bit as shown in FIG. 3 is generally adopted.

The command based on the command data is for selecting an instruction for writing or erasing. In this case, since the writing operation is executed, it indicates a writing instruction. Further, the address data by the upper address and the lower address specifies the address of the flash memory 1, and in the example shown in FIG. 2, up to 2 ¹⁶ addresses can be specified.

When a data rewrite permission signal is externally applied to the input terminal 21, the gate in the SIO circuit 23 is opened and the SIO circuit 23 is ready to receive data. Further, the control circuit 3 closes the gates 38 and 39 to set the state in which the rewriting of the contents of the flash memory 1 from the input / output ports 4 and 6 is prohibited. Here, if command data is applied to the SIO circuit 23 from the input terminal 22, SI
The O circuit 23 detects the start bit attached to the command data. Then, the subsequent 8-bit data is sequentially given to the reception shift register 24.

When the SIO circuit 23 detects the start bit, the SIO circuit 23 informs the BUSY circuit 26 accordingly. B
The USY circuit 26 outputs the BUSY signal from the output terminal 27 accordingly. When the SIO circuit 23 detects the stop bit and the reception buffer 25 is empty, the SIO circuit 23 transfers the data in the reception shift register 24, that is, the command data, to the reception buffer 25. At this time, the SIO circuit 2
3 sends a reception completion signal indicating the completion of reception of the command data to the control circuit 3 and the BUSY circuit 26. Then B
The USY circuit 26 stops outputting the BUSY signal. The external circuit detects that the BUSY signal is off, knows that the reception shift register 24 is empty, and detects that the next data can be transmitted. Further, the control circuit 3 opens the gates 32 and 36 when receiving the reception completion signal. Therefore, the data in the reception buffer 25 is transferred to the command latch 14 via the data bus 7.

Thereafter, similarly, the upper address data, the lower address data and the write data are sequentially transmitted from the outside to the SIO circuit 23 via the input terminal 22.
The upper address data and the lower address data are transferred from the reception buffer 25 to the address latch 11 via the gate 31, the address bus 5 and the gate 34, and the write data is the gate 32, the data bus 7 and the gate 3.
7 is transferred to the data latch 13.

When the write data is latched by the data latch 13, the control circuit 3 connects the switch 35 to the address latch 11 side and gives a write control signal to the WR circuit 2. The W-E-R circuit 2 writes the data latched in the data latch 13 into the flash memory 1 according to the write address latched in the address latch 11 according to the write control signal. WE
When writing, the R circuit 2 reads the data at the address and determines whether the writing has been performed normally. Then, when it is determined that the writing is not normally performed, the writing of the write data is repeated until the writing is normally performed.

If data for rewriting the next data is sent from the outside before the W-E-R circuit 2 completes writing, these data are received.
And held in the reception buffer 25. When the next data transfer is extremely fast as compared to the write operation of the W-E-R circuit 2, the next command data is stored in the reception buffer 25, and the upper address following the command is stored in the reception shift register 2.
The BUSY signal is still output while being held at 3 (see FIG. 4). When the W-E-R circuit 2 determines that the data writing is normally completed, it sends a write completion signal to the control circuit 3.

When the control circuit 3 receives the write end signal, if there is data in the reception buffer 25, the gates 32, 3
6 is opened and the data in the reception buffer 25 is sent to the command latch 14. If the reception shift register 24 has 8-bit data, the data in the reception shift register 24 is transferred to the empty reception buffer 25. At this time, since the reception shift register 24 becomes empty, the BUSY circuit 26 stops outputting the BUSY signal. After that, the data continuing from the outside is sequentially transmitted and the rewriting of the data is continued.

Example 2. Next, data writing to consecutive addresses of the flash memory 1 will be described. From the outside, data as shown in FIG. 5 is sequentially applied to the input terminal 22. In this case, the command data specifies a continuous write command. The upper start address data indicates the upper side of the write start address, and the lower start address data indicates the lower side of the write start address. The byte number data is the flash memory 1 that is the target of continuous writing.
Indicates the number of addresses. If the number-of-bytes data indicates n, then n pieces of write data are transmitted subsequently to the number-of-bytes data.

Next, the operation will be described with reference to FIG. Similar to the case of the first embodiment, when the data rewrite permission signal is externally applied to the input terminal 21, the SIO circuit 23
Is ready to accept data. Further, the control circuit 3 closes the gates 38 and 39 to prohibit the rewriting of the contents of the flash memory 1 from the input / output ports 4 and 6. Command data is input from the input terminal 22 to the SIO circuit 2
3, the SIO circuit 23 detects the start bit attached to the command data. Then, the subsequent 8-bit data is sequentially given to the reception shift register 24.

When the SIO circuit 23 detects the start bit, the BUSY circuit 26 outputs the BUSY signal from the output terminal 27 accordingly. When detecting the stop bit, the SIO circuit 23 transfers the command data in the reception shift register 24 to the reception buffer 25. Also,
The control circuit 3 opens the gates 32 and 36, and the data in the reception buffer 25 is transferred to the command latch 14 via the data bus 7.

When the control circuit 3 recognizes that the data in the command latch 14 specifies continuous writing, the control circuit 3 opens the gates 31 and 33, and then the higher order received by the SIO circuit 23. The start address data, the lower start address data and the byte number data are transferred to the address automatic generation circuit 12. The upper start address data and lower start address data are
In the automatic address generation circuit 12, the upper and lower bits of the address counter are set. Further, in the address automatic generation circuit 12, the byte number data is set in the byte number counter.

Next, the control circuit 3 opens the gates 32 and 37, transfers the write data received by the SIO circuit 23 from the reception buffer 25 to the data latch 13, and the gate 3
Close 2, 37. To do. When the write data is latched, the data latch 13 sends a data latch completion signal to the control circuit 3. The control circuit 3 connects the switch 35 to the address automatic generation circuit 12 side and gives a write signal to the W-E-R circuit 2 according to the data latch completion signal. WE
The -R circuit 2 writes the data latched in the data latch 13 to the address of the flash memory 1 indicated by the content of the address counter of the address automatic generation circuit 12 according to the write signal.

When the W-E-R circuit 2 confirms that the writing has been completed normally, it sends a write completion signal to the control circuit 3. The control circuit 3 sends an increment signal to the address automatic generation circuit 12 in response to the write completion signal.
Further, the gates 32 and 37 are opened again to open the reception buffer 25.
The data inside is transferred to the data latch 13. When the address automatic generation circuit 12 receives the increment signal, it increments the content of the address counter by 1 and decrements the content of the byte number counter by 1. When the data latch 13 latches the data, it outputs a data latch completion signal.

Next, the control circuit 3 gives a write signal to the W-E-R circuit 2 in response to the data latch completion signal.
The W-E-R circuit 2 writes the data latched in the data latch 13 to the address of the flash memory 1 indicated by the content of the address counter of the address automatic generation circuit 12 according to the write signal.

Thereafter, every time the writing to the flash memory 1 is normally completed, the content of the address counter of the automatic address generation circuit 12 is incremented by 1, the content of the byte number counter is decremented by 1, and the data in the data latch 13 is It is written in the flash memory 1. Then, when the content of the byte number counter becomes 0, the continuous writing ends.

In the above embodiment, the case where the byte number counter is provided in the address automatic generation circuit 12 and the continuous writing is ended when the content of the byte number counter becomes 0 has been described. 12 may be provided with a stop address holding register. That is, instead of the byte number data, a stop address may be transmitted from the outside, the stop address may be set in the stop address holding register, and the continuous writing may be ended when the write address matches the contents of the stop address holding register.

Example 3. Next, block erase of the flash memory 1 will be described. In this case, the data shown in FIG. 6 is transmitted from the outside. Here, the command data specifies block erase data. The upper start address data specifies the upper part of the start address of the block of the flash memory 1 to be erased, and the lower start address data specifies the lower part of the start address.

Next, the operation will be described with reference to FIG. Similar to the case of the first embodiment, when the data rewrite permission signal is externally applied to the input terminal 21, the SIO circuit 23
Is ready to accept data. Further, the control circuit 3 closes the gates 38 and 39 to prohibit the rewriting of the contents of the flash memory 1 from the input / output ports 4 and 6. Command data is input from the input terminal 22 to the SIO circuit 2
3, the SIO circuit 23 detects the start bit attached to the command data. Then, the subsequent 8-bit data is sequentially given to the reception shift register 24.

When the SIO circuit 23 detects the start bit, the BUSY circuit 26 outputs the BUSY signal from the output terminal 27 accordingly. When detecting the stop bit, the SIO circuit 23 transfers the command data in the reception shift register 24 to the reception buffer 25. Also,
The control circuit 3 opens the gates 32 and 36, and the data in the reception buffer 25 is transferred to the command latch 14 via the data bus 7.

When the control circuit 3 recognizes that the data in the command latch 14 specifies the block erase, the control circuit 3 opens the gates 31 and 33, and then the upper start received by the SIO circuit 23. The address data and the lower start address data are transferred to the address automatic generation circuit 12.

The control circuit 3 is the W-ER circuit 2
A control signal for block erasing is given to. Then W
The -ER circuit 2 operates in the same manner as in the conventional case to erase the block of the flash memory 1.

Example 4. FIG. 7 is a block diagram showing the main part of a one-chip microcomputer incorporating a flash memory according to another embodiment of the present invention. In the figure, 8 is a CPU, 9 is a memory access prohibition circuit for generating a signal for prohibiting memory access of the CPU 8, and 10 is a C
This is a bus access prohibition circuit that generates a signal for prohibiting bus access of PU8. 1a and 1b are flash memories, 2a and 2b are W-E-R circuits, 11a and 11b are address latches similar to the address latch 11 shown in FIG. 1, and 13a and 13b are data shown in FIG. It is a data latch similar to the latch 13.

As described above, since the flash memory and the data rewriting section are duplicated, for example, the CPU
8 can execute the program in the flash memory 1b by using the address bus 5 and the data bus 7 while the W-E-R circuit 2a is writing or erasing data in the flash memory 1a. If the CPU 8 tries to access the flash memory 1a while the W-E-R circuit 2a is rewriting the data in the flash memory 1a, the memory access prohibition circuit 9 sends a signal for prohibiting memory access to the CPU 8 Give to. Then, the CPU 8 performs an interrupt process triggered by the signal and knows that the access conflicts.

The memory access prohibition circuit 9 is, for example, W
The address bus 5 is monitored when it is notified from the -ER circuit 2a that data writing to the flash memory 1a is being executed. And flash memory 1
When the address assigned to a appears on the address bus 5, the CPU 8 outputs a signal for inhibiting the memory access. Further, when the address bus 5 and the data bus 7 are transferring data from the reception buffer 25 to each latch, for example, the control circuit 3 causes the bus access prohibition circuit 1 to operate.
Notify 0 to that effect. Then, the bus access prohibition circuit 10 outputs a signal for prohibiting the bus access of the CPU 8. The CPU 8 stands by so as not to perform bus access while the signal is being output.

[0049]

As described above, according to the first aspect of the present invention, a microcomputer is provided with a serial input terminal for inputting command, address data and write data, and parallel conversion of data applied to the serial input terminal. Since it is configured to include a command latch, an address latch, or an SIO circuit for supplying data latch, it is possible to easily rewrite or erase the program in the flash memory when mounted on the printed circuit board. It is effective.

According to the second aspect of the present invention, in the microcomputer, the SIO circuit has a reception shift register and a reception buffer, and a BUSY signal for outputting a BUSY signal is output.
Since the configuration is provided with the circuit, there is an effect that it is possible to more rapidly and safely rewrite the data of the built-in flash memory.

According to the third aspect of the present invention, since the microcomputer is configured to have the automatic address generation circuit, there is an effect that the writing time can be further shortened.

According to the fourth aspect of the invention, the microcomputer includes a flash memory and a WE.
Since the configuration is such that the -R circuit is multiplexed, and further the memory access prohibition circuit and the bus access prohibition circuit for prohibiting the memory access and the bus access of the CPU are provided, it is possible that the flash memory is being rewritten. Also has the effect of being able to execute the program.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a one-chip microcomputer according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of data given from the outside when writing data.

FIG. 3 is an explanatory diagram showing a data communication system.

FIG. 4 is a timing chart showing how data is transferred.

FIG. 5 is an explanatory diagram showing an example of data given from the outside during continuous writing.

FIG. 6 is an explanatory diagram showing an example of data given from the outside when erasing a block.

FIG. 7 is a block diagram showing a main part of a one-chip microcomputer according to another embodiment of the present invention.

FIG. 8 is a block diagram showing a main part of a conventional one-chip microcomputer.

[Explanation of symbols]

1, 1a, 1b Flash memory 2, 2a, 2b W-E-R circuit (write-erase-read circuit) 3 Control circuit 5 Address bus 7 Data bus 9 Memory access prohibition circuit 10 Bus access prohibition circuit 11, 11a, 11b Address latch 12 Address automatic generation circuit 13, 13a, 13b Data latch 14 Command latch 22 Serial input terminal 23 SIO circuit (serial data communication circuit) 24 Reception shift register 25 Reception buffer 26 BUSY circuit (transmission start prohibition signal generation circuit)

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[Procedure amendment]

[Submission date] February 22, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

The control circuit 3 controls the gate 3 when a command for designating block erase is input to the input / output port 6.
9 is opened, and further the gate 36 is opened. As a result, the command is transmitted via the data bus 7 to the command latch 14
Latched on. Further, the control circuit 3 includes gates 38 , 3
Open 3 Then, the start address is transferred to the address automatic generation circuit 12 via the address bus 5.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

[0014]

According to another aspect of the present invention, there is provided a microcomputer including a flash memory, a command latch for holding a command for designating writing and erasing of the flash memory, and write data for the flash memory. Hold data latch and write or read flash memory or
An address latch that holds the address to be erased, and writing and reading of the data in the data latch to the flash memory according to the address data in the address latch
ER circuit for writing or erasing flash memory and writing or erasing according to the data in the command latch.
And a control circuit for giving an instruction to the W-E-R circuit to the W-E-R circuit, and further, a serial input terminal for inputting commands, address data and write data, and a command by parallel-converting the data given to the serial input terminal. And a serial data communication circuit for supplying to a latch, an address latch or a data latch.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

According to a second aspect of the present invention, there is provided a microcomputer according to the first aspect, further comprising a serial data communication circuit for receiving data.
It is provided with a transmission start prohibition signal generation circuit that outputs a transmission start prohibition signal to the outside when the reception shift register provided together with the buffer is not empty.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

According to a fourth aspect of the present invention, there is provided a microcomputer in which an address bus through which address data passes, a data bus through which data passes, a plurality of flash memories, and writing and erasing to the flash memories.
A command latch that holds a command that specifies leaving etc. ,
A plurality of data latch for holding the write data to the flash memory, the writing of the flash memory or
Or a plurality of address latches for holding addresses to be read or erased, and a plurality of W-E-s for writing and reading data in the data latch to the flash memory or erasing the flash memory according to the address data in the address latch. W-commands such as writing and erasing according to the data in the R circuit and command latch
A control circuit to be given to the E-R circuit, a serial input terminal for inputting command, address data and write data, and a serial input terminal for serially converting the data given to the serial input terminal and supplying it to a command latch, an address latch or a data latch. A data communication circuit and a memory access prohibition circuit for prohibiting the CPU from accessing the flash memory when one of the W-E-R circuits is accessing the corresponding flash memory And a bus access prohibition circuit that prohibits access to the address bus and data bus of the CPU when data is transferred from the serial data communication circuit to the command latch, address latch or data latch via the address bus or data bus. Be prepared.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

When a data rewrite permission signal is externally applied to the input terminal 21, the gate in the SIO circuit 23 is opened and the SIO circuit 23 is ready to receive data. Further, the control circuit 3 closes the gates 38 and 39 to prohibit the rewriting of the contents of the flash memory 1 from the input / output ports 4 and 6. Here, when the command data is given from the input terminal 22 to the SIO circuit 23, the SIO
The circuit 23 detects the start bit attached to the command data. Then, the subsequent 8-bit data is sequentially given to the reception shift register 24.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

Next, the control circuit 3 opens the gates 32 and 37, transfers the write data received by the SIO circuit 23 from the reception buffer 25 to the data latch 13, and the gate 3
Close the 2, 37. De Taratchi 13, when latches the write data, control data latch completion signal circuit 3
Send to. The control circuit 3 connects the switch 35 to the address automatic generation circuit 12 side and gives a write signal to the W-E-R circuit 2 according to the data latch completion signal. The W-E-R circuit 2 has an address automatic generation circuit 1 according to a write signal.
The data latched in the data latch 13 is written into the address of the flash memory 1 indicated by the contents of the address counter 2 of FIG.

Claims (4)

[Claims] 1. A flash memory, which is a read-only memory capable of electrically erasing data in batch, a command latch that holds a command that specifies writing or erasing to the flash memory, and a data latch that holds write data to the flash memory. An address latch for holding an address to be written or erased in the flash memory, and a write-erase for writing data in the data latch to the flash memory or erasing the flash memory according to address data in the address latch A microcomputer provided with a read circuit and a control circuit for giving a write or erase instruction to the write-erase-read circuit according to the data in the command latch; A serial input terminal for inputting address data and write data, and a serial data communication circuit for parallel-converting data supplied to the serial input terminal and supplying the parallel data to the command latch, address latch or data latch. Characteristic microcomputer. 2. A flash memory, which is a read-only memory capable of electrically erasing data in batch, a command latch that holds a command that specifies writing or erasing to the flash memory, and a data latch that holds write data to the flash memory. An address latch for holding an address to be written or erased in the flash memory, and a write-erase for writing data in the data latch to the flash memory or erasing the flash memory according to address data in the address latch A microcomputer provided with a read circuit and a control circuit for giving a write or erase instruction to the write-erase-read circuit according to the data in the command latch; , A serial input terminal for inputting address data and write data, a reception shift register for converting data given to the serial input terminal in parallel, and a reception buffer for receiving the contents of the reception shift register, and the contents of the reception buffer To a command latch, an address latch, or a data latch, and a transmission start prohibition signal generation circuit that outputs a transmission start prohibition signal to the outside when the reception shift register is not empty. And a microcomputer. 3. A flash memory, which is a read-only memory capable of electrically erasing data in batch, a command latch holding a command designating writing or erasing to the flash memory, and a data latch holding write data to the flash memory. An address latch for holding an address to be written or erased in the flash memory, and a write-erase for writing data in the data latch to the flash memory or erasing the flash memory according to address data in the address latch A microcomputer provided with a read circuit and a control circuit for giving a write or erase instruction to the write-erase-read circuit according to the data in the command latch; , A serial input terminal for inputting address data and write data, a serial data communication circuit that parallel-converts the data given to the serial input terminal and supplies the parallel data to the command latch, address latch or data latch, and the address data A microcomputer provided with an address automatic generation circuit for generating a continuous address starting from the start address when supplying the start address of continuous write and supplying the same to the write-erase-read circuit. 4. An address bus through which address data passes, a data bus through which data passes, a flash memory which is a read-only memory capable of erasing a plurality of electrically writable data, and writing or erasing to each of the flash memories is specified. A command latch for holding a command, a plurality of data latches for holding write data for the flash memory, a plurality of address latches for holding an address to be written or erased in each flash memory, and an address in the address latch. A plurality of write-erase-read circuits for writing data in the data latch to the flash memory or erasing the flash memory according to data, and for issuing a write or erase instruction according to the data in the command latch. The control circuit applied to the write-erase-read circuit, the serial input terminal for inputting the command, the address data and the write data, and the data applied to the serial input terminal are parallel-converted to convert the command latch, the address latch or A serial data communication circuit for supplying to a data latch and each of the above-mentioned write-
A memory access inhibition circuit for inhibiting access to the flash memory of the central processing unit when one of the erase-read circuits is accessing the flash memory corresponding to the write-erase-read circuit; and the serial data communication. And a bus access prohibition circuit for prohibiting access to the address bus and the data bus of the central processing unit when data is transferred from the circuit to the command latch, the address latch or the data latch via the address bus or the data bus. A microcomputer characterized by being provided.