JPH06110582A - Signal synchronizing circuit - Google Patents

Abstract

PURPOSE:To decrease the number of terminals required for synchronizing an external device (such as a tester, for example,) and a semiconductor integrated circuit by deciding timing for starting generating an internal clock synchronized with a reference clock in response to the input of an external reset signal. CONSTITUTION:When an external reset signal RSTX is smaller than a prescribed width, a noise filter 1 outputs no signal. An internal reset circuit 2 outputs the reset signal outputted by the noise filter 1 as an internal reset signal. Based on this internal reset signal, a pulse forming circuit 3 forms a pulse provided with the prescribed pulse width. While receiving the output of the pulse forming circuit 3, an internal clock generating circuit 4 forms two internal clocks KAP and KBP provided with various phases synchronized with the reference clock. A filter pass circuit 5 is a flag showing whether the external reset signal RSTX to be inputted without passing through the noise filter 1 is inputted to the pulse forming circuit 3 or not. Thus, synchronizing timing can be decided.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal synchronization circuit for controlling the rising or falling timing of an internal clock synchronized with a reference clock by an external signal in, for example, a one-chip semiconductor integrated circuit.

2. Description of the Related Art In recent years, one-chip semiconductor integrated circuits have been
Some of them perform operations such as data input, instruction execution, and data output in synchronization with an internal clock. When performing a functional test of such a semiconductor integrated circuit, it is necessary to synchronize the tester and the semiconductor integrated circuit. The reason is that if the tester and the semiconductor integrated circuit are asynchronous, the semiconductor integrated circuit inputs data in synchronization with its own internal clock, executes instructions, and outputs data, but the tester is different from the semiconductor integrated circuit. This is because the data output at the timing may be detected and may not match the expected value. Therefore, conventionally, in order to synchronize the tester and the semiconductor integrated circuit, the internal circuit of the semiconductor integrated circuit is reset by the external reset signal input to the reset terminal, and in that state, the internal clock of the external clock different from the reset terminal is used. A signal instructing to start the operation is input. The operation start instruction signal of the internal clock is given from the tester to match the operation timing of the tester.

However, conventionally, in order to synchronize the tester and the semiconductor integrated circuit, two terminals, that is, a reset terminal and an external terminal other than the reset terminal are required. In a semiconductor integrated circuit, if the number of terminals is large, the cost becomes high, and if the total number of terminals is determined, it may not be possible to provide the necessary terminals, so it is also desirable to reduce the number of terminals required for synchronization. Therefore, an object of the present invention is to reduce the number of terminals required for synchronizing an external device (for example, a tester) with a semiconductor integrated circuit.

To achieve the above object, the present invention comprises a terminal to which an external reset signal is input, a means for generating a reference clock, and a means for generating an internal clock synchronized with the reference clock. In addition, the internal clock generation start timing is determined in response to the input of the external reset signal. Further, a noise removing means connected to the terminal to which the external reset signal is input, and a bypass means for bypassing the noise removing means when determining the timing of starting the generation of the internal clock in response to the input of the external reset signal. Configured to have.

In the present invention, since the external reset signal itself is used to determine the timing of starting the generation of the internal clock, no extra terminal other than the external reset signal terminal is required. Further, even if the noise removing means is provided at the input of the external reset signal, the noise removing means is bypassed and the external reset signal is supplied when the timing of starting the generation of the internal clock is determined in response to the input of the external reset signal. Therefore, it is not necessary to consider the influence of the delay amount due to manufacturing variations when forming the noise removing means.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will be described below with reference to FIG. FIG. 1 is a block diagram of a reset input synchronizing circuit. Reference numeral 1 is a noise filter, which does not output as noise when the reset signal (RSTX) is less than or equal to a predetermined width, 2 is an internal reset circuit, and the reset signal output from the noise filter 1 is used as an internal reset signal (NRSX). Outputting and resetting each circuit in the semiconductor integrated circuit to an initial state, 3 is a pulse forming circuit, which forms a pulse having a predetermined pulse width based on an internal reset signal, 4 is an internal clock generation Circuit, which receives the output of the pulse forming circuit 3 and has two internal clocks (KAP,
What forms a KBP), and 5 is a filter pass circuit, which is a flag indicating whether or not the reset signal (RSTX) that is input without passing through the noise filter 1 is input to the pulse forming circuit. Next, the synchronizing operation of the present invention will be described using the waveform of the reset signal (RSTX) in FIG. 2 and the reset input synchronizing circuit in FIG. The reset signal (RSTX) operates normally at a high level (hereinafter referred to as "H"), and when at a low level (hereinafter referred to as "L"), the internal reset signal (NRSX) is at "L". Is output to reset each circuit in the semiconductor integrated circuit to the initial state. Figure 2
During the middle period A, the external reset terminal is pulled up to the high potential power supply outside the chip, and the reset signal (RST
X) is "H". In this state, the semiconductor integrated circuit operates normally. At this time, in the reset input synchronizing circuit of FIG. 1, the internal reset signal (NRSX) is "H".
Therefore, each circuit in the semiconductor integrated circuit is not reset to the initial state. Since the internal register of the filter pass circuit 5 is “L”, the path through which the reset signal (RSTX) is directly input to the pulse forming circuit 3 without passing through the noise filter 1 is cut off. The pulse forming circuit 3 outputs "H" because there is no change in the internal reset signal (NRSX). The internal clock generation circuit 4 includes a pulse forming circuit 3
In response to the output of "H", two internal clocks (KAP, KBP) having different phases synchronized with the reference clock are generated and supplied to each circuit in the semiconductor integrated circuit. In Fig. 2, forcibly set the external reset pin as in period B.
L "initializes each circuit in the semiconductor integrated circuit. At this time, in the reset input synchronizing circuit of FIG. 1, the filter pass circuit 5 is the same as the period of A. The reset signal (RSTX) is" By changing from H "to" L ", the internal reset signal (NRSX) becomes" L ", and each circuit in the semiconductor integrated circuit is reset to the initial state. The pulse forming circuit 3 has a predetermined pulse width" L ". ", And the internal clock generation circuit 4 outputs the internal clock (KAP, KAP, synchronized with the reference clock after the pulse output is completed (" H ")).
KBP). As described above, each circuit of a normal semiconductor integrated circuit can be initialized by changing only the reset signal (RSTX) in the periods A and B. The present invention is characterized by having the periods C and D described below. In FIG. 2, in the period C, the reset signal (RSTX)
Is "H". Therefore, in the reset input synchronizing circuit of FIG. 1, the pulse forming circuit 3 and the internal clock generating circuit 4 are in the same state as the period A. The filter pass circuit 5 is
Write "H" to the internal register from the external terminal,
The reset signal (RSTX) is set to be directly input to the pulse forming circuit 3. This is the reset signal (R
STX) is the pulse forming circuit 3 via the noise filter 1.
Since the delay component in the noise filter 1 varies depending on the manufacturing process, the timing of changing the reset signal (RSTX) from “H” to “L” is different for each semiconductor integrated circuit. is there. In FIG.
During the period of D, the external reset terminal is forcibly set to "L". As a result, each circuit in the semiconductor integrated circuit is initialized, and at the same time, the operation start timing of the internal clocks (KAP, KBP) is synchronized in response to the change of the reset signal (RSTX). At this time, in the reset input synchronizing circuit of FIG. 1, the internal reset circuit 2 resets each circuit in the semiconductor integrated circuit to the initial state by the internal reset signal (NRSX) as in the period B. Filter pass circuit 5
Is set so that the change of the reset signal (RSTX) from "H" to "L" is directly input to the pulse forming circuit 3, and the internal register is changed to "L" by the internal reset signal (NRSX). In the pulse forming circuit 3 and the internal clock generating circuit 4, the pulse output ends ("
H ") and then generate the internal clocks (KAP, KBP) synchronized with the reference clock. As described above, by operating in the period of C and D, the reset signal (RST
In response to the change from "H" to "L" in (X), it is possible to take the synchronization timing of the operation start of the internal clocks (KAP, KBP). The period E is the same as the period A based on the synchronous timing of the operation start of the internal clocks (KAP, KBP) in the period D, and the data input, the instruction execution,
It operates a normal semiconductor integrated circuit that outputs data. As described above, in this embodiment, as described above, only the reset signal (RSTX) is used, and the internal clocks (KAP, KB) are matched with the operation dimming of the tester or the like.
The synchronous timing of the operation start of P) can be taken.
Although the reset signal (RSTX) is input in order to synchronize with the tester in the above embodiment, the internal clock (KAP, KAP) is input after the reset signal (RSTX) is input.
Since the time until the generation of BP) is assumed in advance, the synchronization with the tester can be performed relatively accurately. Next, a concrete configuration of each circuit of the reset input synchronizing circuit of FIG. 1 is shown in FIGS. 3, 4 and 5. 3 shows the configuration of the noise filter 1, the internal reset circuit 2, and the filter pass circuit 5, FIG. 4 shows the configuration of the pulse forming circuit 3, and FIG. 5 shows the configuration of the internal clock generation circuit 4. ing. In the figure, 6 to 15 are inverter circuits, 16 to 27 are logic circuits, 28 and 29 are clock buffers, and D1 to D8 are analog delay circuits. As shown in FIG.
A multi-stage delay circuit composed of 0 and a capacitor 41, 30 to 36 are registers, 28 and 29 are clock buffers, and three inverters 40 and P and N channel outputs having large driving capability as shown in FIG. Transistor 42,
It is composed of 43. In FIG. 3, the noise filter 1 includes an analog delay circuit D1 and a NOR logic circuit 1
4, the reset signal (RSTX) shorter than the delay time (for example, 100 ns) of the analog delay circuit D1 is regarded as noise and removed.
The internal reset circuit 2 is composed of an inverter circuit 8 and inverts the output of the noise filter 1 to output an internal reset signal (N
RSX) is generated. The filter pass circuit 5 has a register 30 and is supplied from the external terminal during the period C above.
H "is written, and the internal reset signal (NR
It is cleared to "L" by "L" of SX). Further, the analog delay circuit D6 delays the output of the register 30, and its delay time (for example, 5 ns) prevents racing between the registers and results in NO.
In order that the R logic circuit 14 and the AND logic circuit 17 do not change the input signals at the same time, the analog delay circuit D1
Is smaller than. In the AND logic circuit 17, the register 30 sets “H” to the path through which the reset signal (RSTX) is directly input to the pulse forming circuit 3 via the inverter circuit 9.
It will be cut off when. FIG. 4 shows the pulse forming circuit 3
Therefore, when there is a change in the input signal, a pulse having a predetermined width (reference clock number corresponding to the number of stages of the registers 31 to 34) is generated in response to the change. The registers 31 to 34 are latch circuits that take in data in response to the reference clock (I, IX) and output data in response to the next reference clock (I, IX). The analog delay circuits D2 to D4 have a delay time (for example, 5 ns) in order to prevent racing between the registers 31 to 34. FIG. 5 shows the internal clock generation circuit 4, and since the output of the NAND logic circuit 21 is always "H" when the output of the pulse forming circuit 3 is "L",
The clock (TCLK) is always "H" and the output is "
Since the NAND logic circuit 21 operates in the same manner as the inverter circuit when it is H ″, it has a circuit for generating a clock (TCLK) synchronized with the reference clock by feeding back the output of the register 36. The analog delay circuits D5 and D6 have the same configuration as that of the pulse forming circuit 3. Further, based on the clock (TCLK), two non-overlapping internal clocks (KA) are used.
The analog delay circuits D7 and D7 have internal clocks (KAP, KB).
P) having a delay (for example, 10 ns) for generating a non-overlap,
Reference numeral 29 has a structure as shown in FIG. 8 and 9, C
7 shows signal waveforms of the nodes in FIGS. 3, 4, and 5 in the periods of D and D. In the period C, "H" is written from the external terminal to the register 30 of the filter pass circuit 5 like the waveforms of the register output and the D6 output. After that, when the reset signal (RSTX) falls during the period of D, the internal reset signal (NR
SX) is generated. Therefore, the NOR logic circuit 18 changes as shown in FIG. The pulse forming circuit 3 inputs the output change of the NOR logic circuit 18 to one end of the NAND logic circuit 20 as shown in (b), and is synchronized with the reference clock as shown in (c) to (f). To 34 and analog delay circuits D2 to D4, and input to the other end to generate a pulse (PST). The pulse (PST) is input to the internal clock generation circuit, and the clock (TCLK) is generated based on the waveforms such as (g) to (i). Clock (TC
When LK) becomes "H", the internal clock (KAP) becomes "H".
H ”, the internal clock (KBP) becomes“ L ”, and the generation of the internal clock is started. As described above, the reset signal (RSTX) is generated in the periods C and D according to FIGS. In response to the change from "H" to "L" of No. 3, it is possible to set the synchronization timing of the operation start of the internal clocks (KAP, KBP) to the display tube driver to which the reset input synchronization circuit is applied. Controller IC
The block block diagram of is shown. This display tube driver controller IC is used in, for example, a microwave oven, and is an IC that drives a fluorescent display tube and an LED and outputs a buzzer based on data from an external CPU. In the figure, reference numeral 50 is an oscillation circuit that receives the output of an external crystal oscillator and generates a reference clock (I, IX). Reference numeral 51 is a CPU interface circuit, which is connected to an externally connected CPU and a serial interface. , 52 is an output control circuit for the buzzer, which controls a plurality of types of buzzer sounds, 53 is an LED driver, 54 is a general-purpose output port, 5
Reference numeral 5 is a fluorescent display tube controller driver, which is an R for display.
It has the AM 56 and the register 57 and outputs the data written in the display RAM 56. In the above display tube driver controller IC, the reset input synchronizing circuit is provided in the CPU interface circuit 51, and the data written in the register 30 also serves as the serial input SI that normally uses the CPU serial interface. If the input is made by inputting, it is not necessary to provide a dedicated terminal for writing special data.

As described in detail above, according to the present invention, the external reset signal itself is used to determine the timing of starting the generation of the internal clock, so that an extra terminal other than the external reset signal terminal is unnecessary. It has an excellent effect.

[Brief description of drawings]

FIG. 1 is a reset input synchronization circuit diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram of a reset signal (RSTX) according to the present invention.

FIG. 3 is a partial detailed circuit diagram of FIG.

FIG. 4 is a detailed circuit diagram of a pulse forming circuit.

FIG. 5 is a detailed circuit diagram of an internal clock generation circuit.

FIG. 6 is a detailed circuit diagram of an analog delay circuit.

FIG. 7 is a detailed circuit diagram of a clock buffer.

8 is a waveform chart of each node of the circuits of FIGS. 3, 4, and 5. FIG.

9 is a waveform diagram of each node of the circuits of FIGS. 3, 4, and 5. FIG.

FIG. 10 is a block diagram of a display tube driver controller IC.

[Explanation of symbols]

 1 noise filter 2 internal reset circuit 3 pulse forming circuit 4 internal clock generating circuit 5 filter pass circuit

Claims (2)

[Claims] 1. A terminal, to which an external reset signal is input, means for generating a reference clock, and means for generating an internal clock synchronized with the reference clock, and in response to the input of the external reset signal. A signal synchronization circuit characterized in that the timing of starting generation of an internal clock is determined. 2. A noise removing means connected to a terminal to which the external reset signal is input, and the noise removing means when determining the timing of starting generation of an internal clock in response to the input of the external reset signal. The signal synchronization circuit according to claim 1, further comprising a bypass means for bypassing.