JPH0611026B2 - Molecular beam epitaxy growth method - Google Patents
Molecular beam epitaxy growth methodInfo
- Publication number
- JPH0611026B2 JPH0611026B2 JP59253514A JP25351484A JPH0611026B2 JP H0611026 B2 JPH0611026 B2 JP H0611026B2 JP 59253514 A JP59253514 A JP 59253514A JP 25351484 A JP25351484 A JP 25351484A JP H0611026 B2 JPH0611026 B2 JP H0611026B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- film
- molecular beam
- oxide film
- epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、分子線エピタキシャル法を用いた半導体の選
択エピタキシャル成長に関する。Description: TECHNICAL FIELD The present invention relates to selective epitaxial growth of semiconductors using a molecular beam epitaxial method.
（従来技術とその問題点） シリコンのエピタキシャル層は、高品質のシリコン層が
得られることからバイポーラＩＣ(Integrated Circuit)
及び近年は、MOSIC(Metal-Oxide-Semiconductor IC)で
も用いられている。ＩＣの低消費電力化及び高周波数化
の要求により、素子微細化の必要性が高まっている。そ
うしたバイポーラＩＣ、ＭＯＳＩＣの必要性を満足する
ために、素子分離領域の微細化が有効であり、現在種々
の方法が検討されているが、有力な方法として選択エピ
タキシャル成長法がある。(Prior Art and Its Problems) A silicon epitaxial layer is a bipolar IC (Integrated Circuit) because a high quality silicon layer can be obtained.
Also, in recent years, it is also used in MOSIC (Metal-Oxide-Semiconductor IC). With the demand for lower power consumption and higher frequency of ICs, there is an increasing need for device miniaturization. In order to satisfy the need for such bipolar ICs and MOSICs, miniaturization of the element isolation region is effective, and various methods are being studied at present, but the selective epitaxial growth method is an effective method.
選択エピタキシャル成長法の例を第３図に示す。シリコ
ンウエハ１３の上に酸化シリコン膜１４を１〜２μｍの
厚さだけ形成し、反応性イオンエッチングによって部分
的にシリコンを露出させたものをエピタキシャル成長用
の基板として用いる。場合によっては側壁部を窒化シリ
コン膜１５等でコートする。そのような基板に、原料ガ
スとしてSiH2Cl2とHClとを用いエピタキシャル成長を行
うと、酸化シリコン膜上には全くシリコンが堆積せず、
シリコンが露出していた領域だけにエピタキシャル層が
形成できる。しかしながら選択エピタキシャル膜には、
側壁付近に積層欠陥を初めとする格子欠陥とファセット
１７が存在する。格子欠陥の多くは第３図に示したよう
に側壁と基板表面が交わるあたりから発生し、エピタキ
シャル層の表面まで達する。ＭＯＳデバイスでもバイポ
ーラデバイスでも深さ方向にｐ−ｎ接合が存在するが、
ｐ−ｎ接合をよぎる格子欠陥が多い程接合特性は劣化す
るため格子欠陥は少なければ少ないほど望ましい。一方
ファセットが存在すると、ＭＯＳデバイスを作った場合
には、Ｖ型の部分の先端に電界が集中するためにゲート
耐圧を低下させまたファセットの部分は別のしきい値を
もったトランジスタとして働くためにサブスレッシュホ
ールド特性を悪化させる原因となる。従来法では、格子
欠陥とファセットの両方を抑制することができなかっ
た。An example of the selective epitaxial growth method is shown in FIG. A silicon oxide film 14 having a thickness of 1 to 2 μm is formed on a silicon wafer 13 and silicon partially exposed by reactive ion etching is used as a substrate for epitaxial growth. In some cases, the side wall portion is coated with the silicon nitride film 15 or the like. When epitaxial growth is performed on such a substrate using SiH 2 Cl 2 and HCl as source gases, no silicon is deposited on the silicon oxide film,
The epitaxial layer can be formed only in the region where the silicon was exposed. However, for the selective epitaxial film,
Lattice defects such as stacking faults and facets 17 exist near the side wall. Most of the lattice defects are generated around the intersection of the side wall and the substrate surface as shown in FIG. 3, and reach the surface of the epitaxial layer. Although there are pn junctions in the depth direction in both MOS devices and bipolar devices,
The more lattice defects that cross the pn junction, the more deteriorated the junction characteristics. Therefore, the smaller the lattice defects, the more desirable. On the other hand, if facets are present, when a MOS device is made, the electric field is concentrated at the tip of the V-shaped portion, which lowers the gate breakdown voltage, and the facet portion acts as a transistor having another threshold value. It also causes deterioration of the subthreshold characteristic. Both the lattice defects and the facets cannot be suppressed by the conventional method.
近年、高速素子への応用を目的としてこれまでのシリコ
ン薄膜成長技術に比べ、より低温で成長が行なわれ、従
ってオートドーピングがきわめて少なく、急峻な不純物
プロファイルを実現できることを特徴とする高真空中で
のシリコン分子線成長技術が盛んに研究開発されてい
る。たとえば、アプライドフィジィックスレターズ１９
８２年４１巻７５２ページ(Appl.Phys.Lett.４１(8)７
５２）に掲載のジェー・シー・ビーン（Ｊ．Ｃ．Ｂｅａ
ｎ）による報告においては、第４図に示す様にシリコン
基板１８の上に酸化シリコン膜１９を２〜３μｍの厚さ
だけ形成し、反応性イオンエッチングによって部分的に
シリコンを露出させ（第４図(a)）、その後シリコン分
子線成長法によって酸化シリコン膜上に多結晶シリコン
層２０、シリコン基板露出部にエピタキシャル層２１を
厚さ１μｍ成長させる。（第４図(b)）次に、フッ酸に
よるリフトオフ法により酸化シリコン膜１９及び、その
上の多結晶シリコン層２０を除去する。（第４図(c)）
以上のような方法を用いることによって、急峻な側壁部
ときわめて平坦な上面部をもったエピタキシャル成長領
域を得ており、シリコン分子線成長法では、ファセット
の発生がないことを示している。In recent years, compared to conventional silicon thin film growth technology for the purpose of application to high-speed devices, growth is performed at a lower temperature, therefore auto-doping is extremely small, and a sharp impurity profile can be realized in a high vacuum. The silicon molecular beam growth technology of is being actively researched and developed. For example, Applied Physics Letters 19
1982, Vol. 41, page 752 (Appl. Phys. Lett. 41 (8) 7
52) JC Bean (JC Bea)
In the report by n), as shown in FIG. 4, a silicon oxide film 19 having a thickness of 2 to 3 μm is formed on the silicon substrate 18, and silicon is partially exposed by reactive ion etching (fourth embodiment). After that, a polycrystalline silicon layer 20 is grown on the silicon oxide film and an epitaxial layer 21 is grown to a thickness of 1 μm on the exposed portion of the silicon substrate by a silicon molecular beam growth method. (FIG. 4 (b)) Next, the silicon oxide film 19 and the polycrystalline silicon layer 20 thereon are removed by a lift-off method using hydrofluoric acid. (Fig. 4 (c))
By using the method described above, an epitaxial growth region having a steep side wall portion and an extremely flat upper surface portion was obtained, which shows that the silicon molecular beam growth method does not generate facets.
しかし、この場合では、リフトオフ法を用いて多結晶シ
リコンを除去しているために酸化膜も同時に剥離してい
るので素子分離用の絶縁膜をあとで別に形成しなくては
ならない。また、このような絶縁膜の構造では、ＣＶＤ
法による選択エピタキシャル成長法の場合と同様に絶縁
膜側壁近傍に多数の積層欠陥が入るという欠点がある。However, in this case, since the polycrystalline silicon is removed by the lift-off method, the oxide film is also peeled off at the same time, so that an insulating film for element isolation must be separately formed later. Further, in such an insulating film structure, the CVD
As in the case of the selective epitaxial growth method by the method, there is a drawback that many stacking faults are introduced in the vicinity of the side wall of the insulating film.
（発明の目的） 本発明の目的は、この様な従来の欠点を除去せしめてシ
リコン分子線成長法において、絶縁膜パターン内にエピ
タキシャル領域を埋めこんだ構造を実現し、しかもエピ
タキシャル領域内の絶縁膜側壁近傍での格子欠陥の発生
を抑制する方法を提供することにある。(Object of the Invention) An object of the present invention is to realize a structure in which an epitaxial region is embedded in an insulating film pattern in a silicon molecular beam growth method by eliminating such a conventional defect, and further, insulation in the epitaxial region is realized. It is an object of the present invention to provide a method for suppressing the generation of lattice defects near the side wall of a film.
（発明の構成） 本発明によれば、表面を部分的に絶縁膜で被覆した単結
晶半導体基板で、半導体表面が露出している領域に向っ
て絶縁膜側壁上部からひさし上の絶縁膜をつき出させた
構造をつくった後に分子線エピタキシャル成長を行い、
成長した半導体膜が絶縁膜の側壁との間に間隙を生じる
ようにし、その後酸化してこの間隙を酸化膜で埋め、前
記半導体膜に素子の能動領域を作製することを特徴とす
る分子線エピタキシャル成長法が実現できる。(Structure of the Invention) According to the present invention, in a single crystal semiconductor substrate whose surface is partially covered with an insulating film, the insulating film on the eaves is attached from the upper part of the insulating film sidewall toward the region where the semiconductor surface is exposed. After forming the structure that was made out, perform molecular beam epitaxial growth,
Molecular beam epitaxial growth characterized in that a gap is formed between the grown semiconductor film and the side wall of the insulating film, and then oxidation is performed to fill the gap with an oxide film to form an active region of the device in the semiconductor film. The law can be realized.
（実施例） 以下図面を用いて詳細に説明する。第１図は本発明の第
一の実施例を説明する概略工程図を示しており、図にお
いて、１は、単結晶(100)シリコン基板、２は酸化シリ
コン膜、３は窒化シリコン膜、４はエピタキシャル領
域、５は多結晶層領域をそれぞれ示す。まず、シリコン
ウエハー１の表面に熱酸化等の方法で厚さ１〜２μｍの
酸化シリコン膜２を形成し、その上にＣＶＤ法などによ
り窒化シリコン膜３を形成し、続いて当該膜２，３の一
部を通常の反応性イオンエッチングによって選択除去す
る。（第１図(a)） 次に緩衝フッ酸等によって、開口部の側壁の酸化シリコ
ン膜をエッチングする。このとき、窒化シリコン膜３は
影響を受けず、窒化シリコン膜３が開口部領域に向って
ひさし状につき出した構造をつくることができる。（第
１図(b)）このときのひさしの長さは、２００〜５００
０Åが好ましい。ひさしの長さが５０００Å以上になる
と後に示すような熱酸化による表面の平坦化ができにく
くなる。またシリコン分子線は基板に対して完全に垂直
に入射するとは限らないのでひさしの長さが２００Å以
下になると側壁酸化膜位置まで入射シリコン原子が到達
し格子欠陥が発生する可能性が大きくなる。本実施例で
はひさしの長さは２０００Åとした。(Example) A detailed description will be given below with reference to the drawings. FIG. 1 shows a schematic process chart for explaining a first embodiment of the present invention, in which 1 is a single crystal (100) silicon substrate, 2 is a silicon oxide film, 3 is a silicon nitride film, 4 Indicates an epitaxial region and 5 indicates a polycrystalline layer region, respectively. First, a silicon oxide film 2 having a thickness of 1 to 2 μm is formed on the surface of a silicon wafer 1 by a method such as thermal oxidation, and a silicon nitride film 3 is formed on the silicon oxide film 2 by a CVD method or the like. Are partially removed by normal reactive ion etching. (FIG. 1 (a)) Next, the silicon oxide film on the sidewall of the opening is etched with buffer hydrofluoric acid or the like. At this time, the silicon nitride film 3 is not affected, and it is possible to form a structure in which the silicon nitride film 3 sticks out in the eaves shape toward the opening region. (Fig. 1 (b)) The length of the eaves at this time is 200-500.
0Å is preferred. If the eaves length is 5000 Å or more, it becomes difficult to flatten the surface by thermal oxidation as described later. Further, since the silicon molecular beam is not always incident perpendicularly to the substrate, when the eave length is 200 Å or less, incident silicon atoms reach the side wall oxide film position and there is a high possibility that lattice defects will occur. In this embodiment, the length of the eaves is 2000 Å.
次に、シリコン分子線成長法により、成長温度６５０
℃、成長速度１０Å／Ｓで開口部にエピタキシャル層４
を、窒化膜３上に多結晶シリコン層５を形成する。（第
１図(c)）このとき、エピタキシャル層４は、酸化膜２
と接触しない。次に、Dashエッチングによって、多結晶
層５を除去し、熱リン酸等によって窒化膜３を除去す
る。（第１図(d)）このとき、エピタキシャル領域４と
酸化膜２の間には、間隙が残っている。このウエハーを
水蒸気雰囲気中で９００℃、約５０分の酸化を行なう
と、エピタキシャル領域４と酸化膜２の間の空間を埋め
ることができる。（第１図(e)）かかる方法を用いるこ
とにより、格子欠陥を側壁１μｍ（基板面に平行な方
向）当り0.1個以下に押えることができる。一方、かか
るひさし状構造をつくらなかった場合には、欠陥密度
は、側壁の長さ１μｍ当り８〜１０個と多くなり明らか
に接合耐圧に影響を与える程結晶性が劣化する。しか
も、かかる方法では、シリコン分子線成長法を用いてい
るためにＣＶＤ法の場合のようなファセットの発生がな
いという特長を有している。Next, by a silicon molecular beam growth method, a growth temperature of 650
Epitaxial layer 4 in the opening at ℃ and growth rate of 10Å / S
A polycrystalline silicon layer 5 is formed on the nitride film 3. (FIG. 1 (c)) At this time, the epitaxial layer 4 is formed of the oxide film 2
Do not come in contact with. Next, the polycrystalline layer 5 is removed by Dash etching, and the nitride film 3 is removed by hot phosphoric acid or the like. (FIG. 1 (d)) At this time, a gap remains between the epitaxial region 4 and the oxide film 2. By oxidizing this wafer at 900 ° C. for about 50 minutes in a steam atmosphere, the space between the epitaxial region 4 and the oxide film 2 can be filled. (FIG. 1 (e)) By using such a method, the number of lattice defects can be suppressed to 0.1 or less per side wall 1 μm (direction parallel to the substrate surface). On the other hand, if such an eave-shaped structure is not formed, the defect density becomes as high as 8 to 10 per 1 μm of the side wall length, and the crystallinity deteriorates so that the junction breakdown voltage is obviously affected. Moreover, such a method has a feature that facet generation does not occur unlike the case of the CVD method because the silicon molecular beam growth method is used.
この例では、基板に(100)面を用いたために絶縁膜３上
の多結晶層６をDashエッチで除去したが、基板に(111)
面を用いた場合には、ヒドラジンによってエッチングす
ることによって、多結晶層とエピタキシャル層のエッチ
ングの選択性をさらに向上させることができる。In this example, since the (100) plane was used for the substrate, the polycrystalline layer 6 on the insulating film 3 was removed by Dash etching.
When the surface is used, the etching selectivity between the polycrystalline layer and the epitaxial layer can be further improved by etching with hydrazine.
第２図は、本発明の第二の実施例を説明する概略工程図
を示しており、図において６は、単結晶(100)シリコン
基板、７，９は、酸化シリコン膜、８，１０は窒化シリ
コン膜、１２はエピタキシャル領域、１１は多結晶層領
域をそれぞれ示す。まず、シリコンウエハーの表面に熱
酸化等の方法で厚さ１μｍの酸化シリコン膜７を形成
し、その上にＣＶＤ法等により窒化シリコン膜８を形成
し次いでスパッタリング法等により、厚さ３〜４μｍの
酸化シリコン膜９を形成し、さらに、ＣＶＤ法等により
窒化シリコン膜１０を形成し、続いて当該膜７，８，
９，１０の一部を通常の反応性イオンエッチングによっ
て選択除去する。（第２図(a)） 次に、緩衝フッ酸等によって、開口部の側壁の酸化シリ
コン膜をエッチングする。このとき、窒化シリコン膜
８，１０は影響を受けず、窒化シリコン膜８，１０が開
口部領域に向ってひさし状につき出した構造をつくるこ
とができる（第２図(c)）本実施例ではひさしの長さは
２０００Åとした。次に、シリコン分子線成長法によ
り、成長温度６５０℃、成長速度１０Å／Ｓで開口部に
エピタキシャル層１２を、窒化シリコン膜１０上に多結
晶シリコン層１１を形成する。（第２図(c)）このと
き、エピタキシャル層１２は、酸化シリコン膜７と接触
しない。本実施例では、エピタキシャル層の厚さを１μ
ｍとした。次に、緩衝フッ酸によってエッチングするこ
とによって、酸化シリコン膜９のリフトオフによって、
多結晶シリコン膜１１及び窒化シリコン膜１０を除去す
る。このとき、第１の実施例と同様にエピタキシャル層
１２が、窒化シリコン膜８のひさし部分に接しているた
め、緩衝フッ酸は、エピタキシャル層１２と酸化シリコ
ン膜７との間隙に侵入せず、酸化シリコン膜７は、影響
を受けない。次に熱リン酸等によって、窒化シリコン膜
８を除去する。（第２図(d)）このウエハーを水蒸気雰
囲気中で９００℃約５０分の酸化を行なうと、エピタキ
シャル領域１２と酸化シリコン膜７の間の空間を埋める
ことができる。（第２図(e)）かかる方法を用いること
により、エピタキシャル層１２にまったく影響を与える
ことなく、多結晶膜１１を除去することができる。FIG. 2 shows a schematic process diagram for explaining the second embodiment of the present invention. In FIG. 2, 6 is a single crystal (100) silicon substrate, 7 and 9 are silicon oxide films, and 8 and 10 are. A silicon nitride film, 12 is an epitaxial region, and 11 is a polycrystalline layer region. First, a silicon oxide film 7 having a thickness of 1 μm is formed on the surface of a silicon wafer by a method such as thermal oxidation, a silicon nitride film 8 is formed on the silicon oxide film 7 by a CVD method or the like, and then a silicon nitride film 8 having a thickness of 3 to 4 μm is formed by a sputtering method or the like. A silicon oxide film 9 is formed, and a silicon nitride film 10 is further formed by a CVD method or the like.
Part of 9 and 10 is selectively removed by ordinary reactive ion etching. (FIG. 2 (a)) Next, the silicon oxide film on the sidewall of the opening is etched with buffer hydrofluoric acid or the like. At this time, the silicon nitride films 8 and 10 are not affected, and it is possible to form a structure in which the silicon nitride films 8 and 10 stick out in an eaves shape toward the opening region (FIG. 2 (c)). Then, the length of the eaves was 2000 Å. Next, the epitaxial layer 12 is formed in the opening and the polycrystalline silicon layer 11 is formed on the silicon nitride film 10 at the growth temperature of 650 ° C. and the growth rate of 10Å / S by the silicon molecular beam growth method. (FIG. 2 (c)) At this time, the epitaxial layer 12 does not contact the silicon oxide film 7. In this embodiment, the thickness of the epitaxial layer is 1 μm.
m. Next, by etching with buffered hydrofluoric acid, the silicon oxide film 9 is lifted off,
The polycrystalline silicon film 11 and the silicon nitride film 10 are removed. At this time, since the epitaxial layer 12 is in contact with the eaves portion of the silicon nitride film 8 as in the first embodiment, the buffer hydrofluoric acid does not enter the gap between the epitaxial layer 12 and the silicon oxide film 7, The silicon oxide film 7 is not affected. Next, the silicon nitride film 8 is removed by hot phosphoric acid or the like. (FIG. 2 (d)) By oxidizing this wafer in a water vapor atmosphere at 900 ° C. for about 50 minutes, the space between the epitaxial region 12 and the silicon oxide film 7 can be filled. (FIG. 2 (e)) By using such a method, the polycrystalline film 11 can be removed without affecting the epitaxial layer 12 at all.
（発明の効果） 本発明を用いることによって、シリコン分子線成長法に
おいて、絶縁膜パターン内にエピタキシャル領域を埋め
こんだ構造を実現できしかも、エピタキシャル領域内の
絶縁膜側壁近傍での格子欠陥の発生を抑制することがで
きた。(Effect of the Invention) By using the present invention, in the silicon molecular beam growth method, it is possible to realize a structure in which an epitaxial region is buried in an insulating film pattern, and further, a lattice defect occurs near the insulating film sidewall in the epitaxial region. Could be suppressed.
第１図(a)〜(e)及び、第２図(a)〜(e)は、本発明の一実
施例を説明するための模式的断面図で、第３図は従来用
いられている選択エピタキシャル法を説明するための断
面概略図を示す。第４図(a)〜(c)は、現在までに報告さ
れた、シリコン分子線成長法をもちいたパターンエピタ
キシャル成長を説明するための断面概略図を示す。 図に於いて、 １……シリコン基板、２……酸化シリコン膜、 ３……窒化シリコン膜、４……エピタキシャル層、 ５……多結晶層、６……シリコン基板、 ７……酸化シリコン膜、８……窒化シリコン膜、 ９……酸化シリコン膜、10……窒化シリコン膜、 11……多結晶シリコン膜、12……エピタキシャル膜、 13……シリコン基板、14……酸化シリコン膜、 15……窒化シリコン膜、16……エピタキシャル膜、 17……ファセット、18……シリコン基板、 19……酸化シリコン膜、20……多結晶膜、 21……エピタキシャル膜、FIGS. 1 (a) to (e) and FIGS. 2 (a) to (e) are schematic cross-sectional views for explaining an embodiment of the present invention, and FIG. 3 is conventionally used. The schematic sectional drawing for demonstrating a selective epitaxial method is shown. FIGS. 4 (a) to 4 (c) are schematic cross-sectional views for explaining the patterned epitaxial growth using the silicon molecular beam growth method, which has been reported so far. In the figure, 1 ... Silicon substrate, 2 ... Silicon oxide film, 3 ... Silicon nitride film, 4 ... Epitaxial layer, 5 ... Polycrystalline layer, 6 ... Silicon substrate, 7 ... Silicon oxide film , 8 ... Silicon nitride film, 9 ... Silicon oxide film, 10 ... Silicon nitride film, 11 ... Polycrystalline silicon film, 12 ... Epitaxial film, 13 ... Silicon substrate, 14 ... Silicon oxide film, 15 ...... Silicon nitride film, 16 …… Epitaxial film, 17 …… Facet, 18 …… Silicon substrate, 19 …… Silicon oxide film, 20 …… Polycrystalline film, 21 …… Epitaxial film,
Claims (1)
ターンとその上にひさし状に端部がつき出た第２の絶縁
膜パターンとが積層された構造を少なくとも一層形成
し、次に基板表面に半導体膜を分子線エピタキシャル成
長させて、成長した半導体膜が絶縁膜の側壁との間に間
隙を生じるようにし、その後酸化してこの間隙を酸化膜
で埋め、前記半導体膜に素子の能動領域を作製すること
を特徴とする分子線エピタキシャル成長法。1. At least one layer of a structure in which a pattern of a first insulating film and a second insulating film pattern having an eave-shaped end portion are laminated on the surface of a single crystal semiconductor substrate is formed. Then, a semiconductor film is epitaxially grown on the surface of the substrate by molecular beam epitaxy so that a gap is formed between the grown semiconductor film and the side wall of the insulating film, and then oxidation is performed to fill the gap with an oxide film, and the semiconductor film of the device is formed. A molecular beam epitaxial growth method characterized in that an active region is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59253514A JPH0611026B2 (en) | 1984-11-30 | 1984-11-30 | Molecular beam epitaxy growth method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59253514A JPH0611026B2 (en) | 1984-11-30 | 1984-11-30 | Molecular beam epitaxy growth method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61131525A JPS61131525A (en) | 1986-06-19 |
| JPH0611026B2 true JPH0611026B2 (en) | 1994-02-09 |
Family
ID=17252430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59253514A Expired - Lifetime JPH0611026B2 (en) | 1984-11-30 | 1984-11-30 | Molecular beam epitaxy growth method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0611026B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2767676B2 (en) * | 1993-03-19 | 1998-06-18 | 松下電器産業株式会社 | Method for forming fine structure of compound semiconductor |
| CN103632940B (en) * | 2012-08-23 | 2016-04-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5421283A (en) * | 1977-07-19 | 1979-02-17 | Mitsubishi Electric Corp | Manufacture for semiconductor device |
-
1984
- 1984-11-30 JP JP59253514A patent/JPH0611026B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61131525A (en) | 1986-06-19 |
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