JPH06104915A - Buffer priority control method - Google Patents

Abstract

PURPOSE:To simplify FIFO buffer priority control in ATM communication. CONSTITUTION:The method is provided with plural stages of FIFO buffers 1, 2 including primary and secondary buffers, a selector 4, and path selection and control means 3, 5 detecting the priority of reception input cells, monitoring stored information quantity of the primary buffer and controlling the buffer and selector in the unit of cells. When the storage quantity of the primary buffer exceeds a preset threshold level and the priority of the input cell is high, the cell is written in the buffer 1 and when the priority is low, the cell is a high-order (over 2nd) buffer 2. Moreover, when the storage quantity is lens than the threshold value, the cell stored in the high-order buffer is transferred to the lower-order buffer. Since number of buffers is to be provided corresponding to the number of priority classes, the extension of the priority class is easily coped with.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer priority control method in ATM cell communication. The output buffer of the exchange is used to perform priority transmission control of "information unit of the information sequence transmitted for each unit" (hereinafter referred to as "cell"), and to perform service quality control for calls of various information speeds. It is being appreciated.

[0002]

2. Description of the Related Art Conventionally, as one method, a plurality of first-in first-out buffers (hereinafter referred to as "FIFO type buffers") are used in parallel for each priority and priority control is performed by selecting which buffer is to be used for output. A method is known (for example, JP-A-3-1014443: packet priority control method).

[0003]

According to such a parallel buffer system, the cell delay of each priority can be controlled independently of other priorities, but the control is complicated and it is possible to add a priority class. There is a problem of lack of sex. Therefore, it is an object of the present invention to allow the control to be simple and facilitate the addition of priority classes while allowing a certain degree of influence of the high rank.

[0004]

According to the present invention, a plurality of stages of FIFO type buffers including a primary buffer and a secondary buffer, an output of the secondary buffer and a new reception input cell are input, and one of them is input to the next stage. And a path selection control means for detecting or judging the priority of the received input cells and monitoring the accumulated information amount of the primary buffer to control the buffer and the selector on a cell-by-cell basis. There is. Further, according to the present invention, when the accumulated information amount of the primary buffer exceeds the preset threshold value by the route selection control means, if the priority order of the input cell is the first order, the primary buffer is set. Write, if lower rank, write to higher or higher order buffers, and transfer cells stored in higher order buffer to lower order buffer while no new input cells of higher order arrive. It is what makes me.

[0005]

The threshold value is determined in consideration of the average fluctuation of the short period which does not cause the fluctuation of the cell arrival rate to be a problem. 1
If the amount of information stored in the next buffer is less than or equal to the threshold value, priority control is not performed and cells are sent to the outgoing line via only the primary buffer. When the threshold value is exceeded, the first-ranked input cells are written to the primary buffer, and the lower-ranked input cells are written to the secondary buffer or higher buffers. Sent via the primary buffer. According to this method, since the priority control is restricted to be performed only when the cell is congested, the control is relatively simple, and the expansion of the priority class can be easily coped with by adding the buffer. .

[0006]

EXAMPLES Next, examples of the present invention will be described. FIG. 1 is a block diagram showing a first embodiment of the present invention. Figure 1
, 1 is a FIFO type primary buffer, 2 is a FIFO
O-type secondary buffer, 3 is a route selection switch having a function of detecting the priority of cells, 4 is a route R0,
A selector 5, which outputs one of an input cell given through R1 and an output of the secondary buffer 2 given through a route R3, monitors the amount of information stored in the primary buffer 1 and selects a route selection switch 3 and a selector 4. Is a controller that controls the selection of. In addition, in this example, two types of priorities of 1st and 2nd are handled, and when a cell having many priority labels is received, the route selection switch 3 sets this to 1st and 2nd It is detected as two types of priority order.

The priority of the cell coming from the route R0 which is the input terminal is detected by the route selection switch 3, and the route R1 is selected if it is the first cell. At this time, the selector 4 also selects the route R1 and is sent to and written in the primary buffer 1. When the priority of the cell coming from the route RO is the second, the controller 5 determines that the primary buffer 1
And the amount of information stored in the secondary buffer 2 is monitored, and the amount of information stored in the primary buffer 1 is less than or equal to the threshold value X
If is empty, path 1 is selected and sent to the primary buffer 1 and written. In this state, the priority of the cell is ignored, and the route R is used rather than the speed at which the cell exits the route 4.
If the velocity coming in from O is faster, the cell accumulates in the primary buffer 1.

When the amount of cells accumulated in the primary buffer 1 exceeds the threshold value X, or when the cells remain in the secondary buffer 2, the controller 5 selects the route 2 and the route RO The second cell having the second highest priority is sent to the secondary buffer 2 and is written therein.

The controller 5 monitors the capacity of the primary buffer 1 while the new cell having the first priority is not present on the route R0. If the threshold X is not exceeded, the controller 5 routes the selector 4 to the route. 2 by switching to R3
The cells accumulated in the next buffer 2 are sent to the primary buffer 1 through the route R3. Even during that time, if the cell of the primary buffer 1 exceeds the threshold value X, the controller 5 switches the selector 4 to the path 1 and stops the cell transfer.

FIG. 2 is a block diagram showing a second embodiment of the present invention, in which 11, 12, 13, and 14 are primary and secondary in sequence.
Next, third and fourth buffers, 31, 32 and 33 are path selection switches, 41, 42 and 43 are selectors, 51 and 52,
53 is a controller. In this embodiment, three path selection switches 31 to 33 are used to provide four buffers 11.
It is a system for allocating cells to 14 cells. The cell coming in from the route R0 is routed to the route R1 by the route selection switch 31.
Or assigned to R2. The cell that has proceeded along the route R2 is distributed to the route R5 or R6 by the route selection switch 32, and the cell that has proceeded along the route R6 is selected by the route selection switch 33.
Then, it is distributed to the route R7 or R8. The cells passing through the route R1 are sent to the primary buffer 11 and leave the route R4. The cells passing through the route R5 accumulate in the secondary buffer 12,
It flows through the route R3 to the primary buffer 11. Similarly, cells passing through the route R7 are accumulated in the tertiary buffer 13 and cells passing through the route R8 are accumulated in the quaternary buffer 14, and then flow to the next buffer.

The controller 5 uses the path of such a cell.
1 to 53 monitor the cell capacities of the buffers 11 to 14,
Control by comparing with a threshold X. If the storage capacity of the low-order buffer exceeds the threshold value X, the new input cells given from the route R0 are sorted according to the priority order, and the first-order one is sent to the primary buffer 11 and the second order cell.
The ones in the rank are in the secondary buffer 12, and those in the third rank are 3
To the next buffer, the third or lower rank is the quaternary buffer 14
Sort to. When there are no cells accumulated in the low-order buffer or when the threshold value is less than or equal to the threshold value X, the controller selects a route corresponding to the buffer and accumulates it. When the value is less than or equal to the X value, a new input cell coming from the path 0 is sent to the primary buffer 11 via the path 1 and stored therein regardless of the priority.

During a period in which a new input cell does not arrive on the route R0, the controllers 51 to 53 monitor the buffers 11 to 14 and when the threshold value X is below,
The cells of the high-order buffer of the previous stage are transferred to the low-order buffer of the next stage. Control by monitoring and comparing to threshold X. For example, the cell of the primary buffer 11 has a threshold value X
Controller 51, the controller 51 switches the selector 41 toward the route R3, and the secondary buffer 12
The accumulated cells are sent to the primary buffer 11 via the route R3 until a new cell arrives on the route R1. Even during that time, if the amount of cells in the primary buffer 11 exceeds the threshold value X, the controller 51 switches the selector 11 to the route R1, and the flow of cells from the secondary buffer 12 is switched. stop.

FIG. 3 is a block diagram showing a third embodiment of the present invention. 10 is a high-order buffer, 40 is a selector,
Reference numeral 50 is a controller, 60 is a clock, and R11 to R14 are paths, and an information discarding function is added in order to suppress a delay in a secondary or higher order buffer. In FIG. 3, when the cell enters the high-order buffer 10 from the route R12, the controller 50 reads the time from the clock 60 and stores it. Then, when the cell comes to the output area at the bottom of the buffer 10, the time is compared with the time when the cell is written in the buffer 10. If a certain time has passed, the selector is selected. To route R
The color is obtained by outputting the cell without outputting through R13.
Discard from. If it has not passed, it waits until a cell does not come from the route R11 until it can be output to the selector 10, but during that time, if a certain period of time comes, the cell is discarded. By adding such an information discarding function, the delay in the high-order buffer can be suppressed within a certain amount. This reduces the load on the system by discarding cells that have been left too long and are meaningless.

In the above embodiment, the priority control is performed based on the cell label. For example, the primary buffer has cell loss priority and the higher buffer has payload type. Priority control can be performed based on the attribute. In the above-described embodiment, priority control is performed based on the priority order detected from the cell label, but various attributes of the cell are detected and the priority order is set based on the instruction from the network. Alternatively, the priority control may be performed based on the determined priority.

[0015]

As is apparent from the above description, according to the present invention, control is performed so that cells stored in a high-order buffer are transferred to a low-order buffer during a period when an input cell having a high priority has not arrived. In addition, since it has a multi-stage buffer configuration in which it is transmitted from the primary buffer, it is easy to control,
In addition, when the number of priority classes increases, it is possible to easily deal with the problem by combining modules including a selector, a controller, a buffer, a route selection switch, etc. in multiple stages.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a buffer priority control method of the present invention.

FIG. 2 is a block diagram showing another embodiment of the buffer priority control method of the present invention.

FIG. 3 is a block diagram showing another embodiment of the buffer priority control method of the present invention.

[Explanation of symbols]

 1 Primary buffer of FIFO type 2 Secondary buffer of FIFO type 3 Path selection switch 4 Selector 5 Controller

Claims (1)

[Claims] 1. A plurality of stages of FIFO type buffers including a primary buffer and a secondary buffer, and an output of the secondary buffer and a newly received input cell, which are input to one of the primary buffers of the next stage. A selector for outputting and detecting or judging the priority of the received input cell, monitoring the amount of information stored in the primary buffer, and selecting a route and control means for controlling the buffer and the selector in cell units, By the route selection and control means, the input cells of the first rank are written in the primary buffer, and the input cells of the second rank or lower are equal to or less than a certain threshold value of the accumulated information amount of the primary buffer. Write to the primary buffer only when the secondary buffer is empty, otherwise write to the secondary buffer or a buffer higher than secondary. And when the accumulated data amount of the primary buffer falls below the threshold value, the buffer priority control method, characterized in that the cells of the secondary buffer was set to be transferred to the primary buffer.