JPH09149051A - Packet transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cell multiplex device conducting priority control between classes easily realized even when the number of input ports is large. SOLUTION: The device is provided with plural input buffers 10, a class management section 12 controlling the input buffers 10, and at least one output port 11 used to transfer packets outputted from the input buffers 10. The input buffers 10 have storage means 13a-13c for each class storing the received packet tentatively for each class and an output means 14 outputting the packet of the class commanded by the class management section 12 to the output port 11 from the storage means 13a-13c, and the class management section 12 grasps the storage state of the entire plural input buffers for each class and decides a class from which a packet is to be outputted based on the storage state and sends a command including designation of the decided class to the plural input buffers 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell multiplexing device and a cell buffer device in an ATM communication network, for example.

Since a plurality of cell multiplexers are superposed on each other in the cell switch, the structure of the cell multiplexer of the present invention should be applied to the cell switch as a structure corresponding to one output port of the cell switch. Is possible.

The cell buffer device of the present invention is applicable not only to cells but also to general buffer devices.

Further, the present invention can be applied not only to the ATM communication network but also to the packet switching network.

[0005]

2. Description of the Related Art Currently, ATM (Asyncronou)
Researchers in communication technology around the world are energetically carrying out research on s Transfer Mode communication systems. In the ATM communication system, information is transferred and exchanged in fixed length packets called cells. In the ATM communication system, a high-speed cell exchange can be performed by a cell switch by hardware in a switch node, and an information transfer capacity per unit time which exceeds that of an existing communication network can be realized.

The ATM communication system uses the VPI of the cell header.
(Virtual Path Identifier) and VCI (Virtual Channel Identifier)
By using identification information called “filer”, a plurality of connections (Virtual) are logically connected to one physical transmission line.
Connection: VC) can be set. In each switch node in the network, a route is set in advance for each VC, and the switch node obtains the output route to output the cell from the cell connection identifiers VPI and VCI. Since the VPI and VCI are uniquely assigned on the physical transmission path between the switch nodes, the switch node has the ability to rewrite the VPI and VCI values of the passing cell.

Up to now, VCs whose quality has been guaranteed in the ATM network are CBR (Constant Bit R).
ate: fixed bit rate) connection or VBR (V
A variable bit rate (variable bit rate) connection was the center. The CBR connection has a cell transmission rate (also referred to as cell rate or band).
It is a VC that transmits a known traffic with a constant number of cells transmitted per unit time. The VBR connection does not have a constant cell transmission rate, but its maximum value (peak rate) and average value (average rate). It is a VC whose traffic properties such as are known in advance.

Basically, a plurality of Vs are provided on one physical transmission line.
When C is multiplexed while maintaining sufficient quality, the sum of the peak rates of all VCs should be below the band of the physical transmission line. This method is called peak rate allocation. When only the CBR connection is assigned the peak rate, a sufficiently high utilization efficiency of the physical transmission line can be achieved. In the case of the VBR connection, peak rate allocation cannot increase the utilization efficiency of the physical transmission path. Therefore, a technique for improving the utilization efficiency while maintaining the quality by using the statistical multiplexing effect has been intensively studied from the nature of the traffic known in advance.

However, considering ATM communication between computers, the nature of the traffic such as the average rate cannot be predicted in advance, and a large number of cells are momentarily transmitted, but when they are not transmitted, no cells are transmitted at all. There is a property called burst property. Therefore, it is difficult to improve the utilization efficiency of the network while guaranteeing the quality like CBR and VBR. In other words, the data transferred between computers has a significant decrease in network utilization efficiency when trying to guarantee the quality by peak rate allocation, etc. When statistical multiplexing effect like VBR is used, the traffic burstiness causes a cell loss. A large number of cells arrive at an output port with a switch at the same time,
If the buffer amount of the cell switch is not sufficient, cell discard will occur due to buffer overflow. Further, when cell discard occurs, retransmission is performed in packet units composed of a plurality of cells, which reduces the effective throughput.

Therefore, in recent years, the flow control between the terminal and the switch node is performed to guarantee the transfer quality of the cell (particularly the quality regarding cell discard) and to improve the utilization efficiency of the network.
A service class called R (Available Bit Rate) has been proposed and studied. The ABR connection requests the transmitting terminal to send the cell to the transmitting terminal before the occurrence of the cell congestion when the passing switch node is about to become congested with the cell congestion. The traffic control information to the terminal is mainly performed using cells called RM cells (resource management cells).
There is a delay time that cannot be ignored in the traffic control from the switch node to the transmitting terminal in ABR. Therefore, the cell switch must be equipped with a large capacity buffer so that the cell is not discarded until the traffic control works effectively.

As another service class of CBR, VBR and ABR, UBR (Unspecified Bit) is used.
There is a service class called Rate). This class does not require detailed reporting of traffic characteristics output by the terminal to the network. Instead, the network is a class of so-called Best Effort services, which does not guarantee any transfer quality.

As described above, since data between computers has a burst property, it is necessary to mount a large capacity cell buffer in the cell switch in order to satisfy the cell loss rate of the UBR connection. It is believed that.

Fortunately, traffic between computers is required to have a delay time for transfer and a demand for delay fluctuation in CBR and VB.
It is often less severe than R. The transmission delay time and delay fluctuation of a cell increase by mounting a buffer with a large capacity in the cell switch, but there are many applications that can tolerate it.

Particularly in the case of ABR and UBR services, it is considered necessary to have means for avoiding network congestion. As one of the congestion avoidance means, EFCI (ExplicitFit)
orward Congestion Indicat
Ion). There is an EFCI bit in the header of the cell that writes the congestion experience for that cell, and the cell switches in the network mark the EFCI according to the congestion situation. The terminal can avoid the congestion by using the information.

Next, inter-VC fair queuing will be described.

First, the inter-VC fair queuing required for fault tolerance in the ABR service will be described.

The ABR service is established by the transmitting terminal controlling the transmission of cells according to the traffic control information from the network. If a terminal fails (or intentionally) and ignores the traffic control information from the network, it may be difficult to escape from the congestion of the network.

Such a problem is caused by fair queuing among VCs in the cell multiplexer or cell switch, and fair cell multiplexing scheduling between Vs and Vs.
This can be solved by realizing fair buffer allocation among Cs. If the fair queuing between VCs is performed, the interaction between VCs can be minimized, and even if there is a VC that ignores traffic control information, only that VC can be affected by congestion and the influence on other VCs can be reduced. Because.

Fairness in the UBR service requires fair queuing between VCs.

FIG. 48 shows an example of unfair bandwidth allocation in the UBR service. In this example, the terminal A,
There are four terminals B, C and D and one file server, each of which is a cell switch (or cell multiplexer) X, Y and Z and links 1, 2, 3, 4, 5, 6, 7 Connected by.

If cells are multiplexed regardless of the number of VCs set in the input link, the cell switches treat the input ports equally. For example, when the cell switch X multiplexes cells from the link 2 and the link 3 to the link 1, since both links are treated equally, if the band of the link 1 is 1.0, the link 2
And link 3 are each given a bandwidth of 0.5.

Considering the same way, the bandwidth finally given to each terminal is the largest at terminal A, 0.5, and terminals C and D.
Is the smallest 0.125. Given that it is ideal that all terminals access the file server equally, this is far from ideal.

Furthermore, when the network is congested, the network sends EFCI information to the terminal so as to reduce the bandwidth. At this time, if there are terminals that faithfully follow the EFCI information and terminals that ignore the EFCI information in the network, only the terminals that adhere to the EFCI suppress the transmission of cells. There is also the problem that it will be secured.

These problems are due to the fact that the cell switch treats each input link equally, ignoring the number of VCs multiplexed on the input link. Since the cell switch performs fair queuing between VCs and distributes the band according to the number of VCs, each terminal can access the file server fairly.

Next, a cell multiplexer for performing priority control between classes will be described.

FIG. 49 shows the configuration of a conventional cell multiplexing apparatus for performing priority control between classes.

FIG. 49 shows a cell multiplexer for multiplexing cells input from N input ports into one output port.

The output buffer stores cells for each class in the internal cell storage unit for each class, and the cell selection unit selects and outputs the cells to the output port according to the priority of the class.

A back pressure signal is generated by comparing the number of cells stored in each storage section of the output buffer with a threshold value. The input buffer is also provided with a cell storage section for each class, and transfers cells to the output buffer according to the priority of the class among the classes whose output is permitted by the back pressure signal.

In this configuration, since it is necessary to provide a plurality of cell storage units for each class in the output buffer, there is a drawback that it becomes difficult to realize the output buffer when the number of classes increases. In particular, the input speed of the output buffer must be N times the speed of the input port (N is the number of input ports). When the number of classes and the number of input ports are large, it is impossible to realize such a complicated function. It was difficult.

Considering FIG. 49 as a portion related to each output port of the cell switch, the same problem exists in the cell switch having the buffer at the input port.

Next, the cell multiplexer will be described.

Problems of the cell multiplexer having the input buffer as shown in FIG. 50 will be described.

FIG. 50 shows a cell multiplexer which multiplexes cells input from N input ports into one output port.

The output buffer temporarily stores cells from the input port and outputs the cells according to the speed of the output port.

A back pressure signal is generated by comparing the number of cells stored in the output buffer with a threshold value. The input buffer has one queue corresponding to the output port, and transfers cells to the output buffer only when output is permitted by the back pressure signal.

Since such a cell multiplexer treats each input buffer fairly regardless of the number of set VCs, there is a problem in the fault tolerance in the ABR service and the fairness in the UBR service.

Considering FIG. 50 as a portion related to each output port of the cell switch, the same problem exists in the cell switch having the buffer at the input port.

Next, inter-VC fair queuing will be described.

FIG. 51 shows the structure of the FIFO for each VC, which is a method for realizing fair queuing between VCs.

In FIG. 51, the connection identification information of the cell input from the input link is notified to the buffer pointer management unit, the write pointer indicating the write position of the cell is obtained from the buffer pointer management unit, and the cell is temporarily stored in the cell buffer. A cell buffer device for accumulating and reading a cell from a cell buffer based on a read pointer indicating a read cell from a buffer pointer management unit and outputting the cell to an output link. The buffer pointer management unit manages a buffer pointer indicating the position of the accumulated cell on the cell buffer.

The buffer pointer management unit manages the buffer pointer for each VC based on the VC table. FIG. 51 shows a widely known management method using a pointer chain.

When the cell is input, one buffer pointer is taken out from the head of the empty chain as a write pointer and attached to the end of the VC chain corresponding to the input cell. When outputting a cell, the VC accumulating the cell is fairly selected, and the buffer pointer at the head of the VC is read out and taken out as a pointer. Round robin is known as a method for selecting VCs fairly when outputting cells.

In order to select a VC by round robin, it is necessary to sequentially search the VC table for the cells accumulated in the buffer after the previously output VC. When there are many searches, almost all V
It is necessary to perform C in one cell cycle, but VC to be set
The number could be in the thousands or more, which was difficult to achieve.
Next, the queue length monitoring will be described.

FIG. 52 shows an example of changes in the queue length of the input buffer in the cell multiplexer having the input buffer as shown in FIG.

The horizontal axis represents time, the vertical axis represents the queue length of the input buffer, and the lower axis represents the back pressure signal. When the back pressure signal indicates the prohibition of output (Tup), the output throughput from the input buffer is zero, so the queue length increases at the buffer input rate (Ri). When the backpressure signal indicates that output is possible, the output throughput from the input buffer is maximum and the queue length is usually reduced.

Thus, the queue length oscillates in synchronization with the back pressure signal. Conventionally, when a cell arrives at a buffer, if the queue length exceeds a threshold value, the input cell is not accepted and discarded, and if it does not exceed the threshold value, it is widely accepted. This method is not a problem in a normal buffer, but it becomes a problem when the output of the buffer is controlled by the back pressure signal in this way. The maximum value of the queue length is determined by the input rate (Ri) and the time (Tup) during which the back pressure signal instructs the output inhibition, and particularly the output inhibition time (Tup) of the back pressure signal.
Is greatly affected by input traffic to other input buffers.

In the case of the buffer device controlled by the back pressure signal, the method of simply comparing the queue length with the threshold value to determine the cell discard determines that the cell discard is sensitively affected by the external condition and the stable cell is discarded. It was difficult to discard. There was the same problem when judging congestion from the queue length.

Next, a cell buffer device for performing priority control will be described.

FIG. 53 shows the configuration of a cell buffer device for performing priority control.

With respect to delay, there are a class 1 cell accumulating section for temporarily accumulating low priority cells and a class 2 cell accumulating section for temporarily accumulating high priority cells, each output of which is a class multiplexing FIFO. Are multiplexed by. The class management unit inputs the number Na of class 2 cell storage units and the number Nb of class multiplexing FIFO cells, and gives a transfer instruction to either class. The cell storage unit of the class that has received the transfer instruction transfers only one cell to the class multiplexing FIFO.

In order to improve the performance of the priority control of this cell buffer device, it is necessary to reduce the number of cells stored in the class multiplexing FIFO. However, in order to prevent the throughput from decreasing, the class multiplexing FIFO should be used. It is necessary to instruct the transfer not to empty (= not underflow). Furthermore, if one of the cell storage units is empty and a transfer instruction is issued to the empty cell storage unit (called an empty instruction), underflow may occur. Therefore, it is necessary to give a transfer instruction to the cell storage unit in which the storage cell exists.

According to the above policy, the class management section is classified into class 2
The condition for instructing the transfer to the cell storage unit is given by (Nb ≤ 1) and (Na > 1). The transfer instruction to the class 1 cell storage unit is (Nb ≤1) and (Na == 0).

Here, transmission of cell number information from the cell storage unit for each class or class multiplexing FIFO to the class management unit, transmission of transfer instruction information from the class management unit to the class-specific cell storage unit, and Consider a case where there is a delay time in the cell transfer from the cell storage unit to the cell multiplexing FIFO. At this time, conventionally, the following problems existed.

Due to these delay times, the class multiplexing F
The class manager could not accurately determine whether the IFO would underflow. Therefore, the number of cells in the class multiplexing FIFO is compared with a large threshold value corresponding to the delay time to set a condition for preventing underflow. As a result, the average queue length of the class multiplexing FIFO becomes large and the performance of the priority control deteriorates.

Further, it is not possible to accurately determine that the class 2 cell storage unit has become empty due to the delay in transmission of the high priority class 2 cell storage unit information. Therefore, if it is empty but it is not empty, you will give an empty instruction or
If it is not empty, it is erroneous if it is empty, and an instruction has been given to preferentially output cells of low priority class 1 over cells of high priority class 2. As a result, there are problems that the throughput of the cell buffer device is reduced and the performance of the priority control function is reduced.

The problems with the cell buffer device for performing the priority control shown in FIG. 53 have been described above. This problem can occur not only in the cell buffer device that performs such priority control, but also in various cell buffer devices.

That is, in the cell buffer device in which the management unit instructs the transfer of cells between a plurality of buffers, the buffer information is transmitted to the management unit, the transfer instruction information is transmitted from the management unit to the buffer, and the cells between the buffers are transferred. If there is a delay time in the transmission, there is a problem that the performance and throughput of the cell buffer device deteriorate.

[0059]

As described above, the conventional cell multiplexer has the following two problems, first and second.

First, since it is necessary to provide a plurality of cell storage units for each class in the output buffer, there is a drawback that it becomes difficult to realize the output buffer when the number of classes increases.
In particular, the input speed of the output buffer is N times the speed of the input port.
Must be double (N is the number of input ports), the number of classes,
When the number of input ports is large, it is difficult to realize such a complicated function.

Next, since each input buffer is treated fairly regardless of the number of set VCs, there is a problem in the fault tolerance in the ABR service and the fairness in the UBR service.

Further, the conventional cell buffer device has the following two problems, third and fourth.

First, in order to select a VC by round robin, it is necessary to sequentially search the VC table, starting from the VC output last time, to see if there are any cells accumulated in the buffer. In the case of a large number of searches, it is necessary to perform almost all VCs in one cell cycle, but the number of VCs to be set may reach several thousands or more, which is difficult to realize.

On the other hand, in recent years, "Efficient"
Fair Queue Defending Rou
nd Robin ”(pp.231-242, ACM
An algorithm as described in SIGCOMM '95, August 1995) has been proposed. Since the algorithm called DRR proposed in this document manages the VC storing the cells by using the concept of the active list, it is not necessary to search the VC table when outputting the cells. Therefore, even if the number of VCs to be set increases, V
Selection of cells to be output can be realized for fair queuing between Cs. However, in this DRR algorithm, packets are classified for each VC and stored, so that each VC is stored.
The number of packets corresponding to the value of the weight set to is output at one time, and the burstiness of the output traffic becomes very high.

Next, in the case of the buffer device controlled by the back pressure signal, the method of simply comparing the queue length with the threshold value to determine the cell discard is sensitive to the cell discard due to external conditions and is stable. It was difficult to dispose of the cells. There was the same problem when judging congestion from the queue length.

Further, in the cell buffer device in which the management unit instructs the transfer of cells between a plurality of buffers, there is the following fifth problem. That is, if there is a delay time in the transmission of the buffer information to the management unit, the transmission of the transfer instruction information from the management unit to the buffer, and the transmission of the cells between the buffers, the performance and throughput of the cell buffer device will be reduced. There was a problem.

The present invention has been made in view of the above points, and an object of the present invention is to provide a cell multiplexing device that performs priority control between classes that is easy to implement even when the number of input ports is large. To do.

Another object of the present invention is to provide a cell multiplexer capable of performing per-VC fair queuing which realizes fault tolerance in an ABR service and fairness in a UBR service.

Another object of the present invention is V which can be easily realized without depending on the upper limit of the number of VCs that can be set.
It is to provide a cell multiplexing device that performs fair queuing between Cs.

Still another object of the present invention is to provide a cell multiplexer in which the result of queue length monitoring is not easily affected by external conditions, and stable queue length monitoring is easy.

Another object of the present invention is to transmit buffer information to the management unit and transmission of transfer instruction information from the management unit to the buffer when the management unit instructs the transfer of cells between a plurality of buffers. It is an object of the present invention to provide a cell multiplexing device in which performance and throughput do not deteriorate as in the conventional case even when there is a delay time in cell transmission between buffers.

[0072]

A packet transfer apparatus (claims 1 to 4) of the present invention comprises a plurality of input buffers for temporarily storing input packets, and a control means for controlling these input buffers. A packet transfer device comprising at least one output port for transferring a packet output from each input buffer, wherein each input buffer temporarily stores the input packet for each class. And output means for outputting a packet of a class instructed by the control means from the storage means to the output port, the control means indicating the storage status in the entire input buffers of the storage means. Grasp for each class, decide the class to output the packet based on this accumulation status, and give the instruction including the designation of the decided class. By transmitting to a plurality of input buffers, the control unit grasps the statuses of the plurality of input buffers (at least the statuses of the entire input buffers are sufficient, but it is also possible to know the statuses of individual input buffers). Since no instruction is issued, the priority relationship between classes does not collapse due to the difference in the accumulation status of each input buffer class, and even if the number of input ports, that is, the number of input buffers, increases easily. Priority control between classes can be realized.

Further, the packet transfer apparatus of the present invention (claims 5 and 6) comprises a plurality of input buffers, a control means for controlling these input buffers, and at least one for transferring the packets output from each of the input buffers. A packet transfer device having two output ports, wherein each of the input buffers receives an instruction from the storage means for temporarily storing an input packet, and the control means, and then receives from the storage means in the next phase. The control unit includes a selecting unit that selects a packet to be output to the output port, and an output unit that outputs the packet selected by the selecting unit to the output port. Before grasping the output status of the packet selected by the selecting means in the entire buffer and selecting a new packet based on this output status Introducing the concept of a packet set (car) that should be output in a certain phase (its time length is indefinite) by instructing multiple input buffers, selecting packets to be included in this packet set, and Each input buffer shares the processing of outputting only the packets contained in the set (output of other packets is not allowed), and the control unit (cargo management unit) processes the process of instructing the timing of inserting a new packet into the packet set. ), It is possible to easily realize fair queuing between VCs in an input buffer type cell switch, for example.

Further, the packet transfer device of the present invention (claims 7 and 8) transfers a packet which temporarily stores an input packet, a control means which controls this buffer, and a packet which is output from the buffer. In the packet transfer apparatus, the control unit divides the packets accumulated in the buffer into a plurality of sets and manages the packets, and the packets input to the buffer are evenly distributed among the flows to which the packets belong. And a command for instructing the buffer to output a packet belonging to one of the plurality of sets managed by the management unit Means for distributing packets to a plurality of sets when a packet is input by the control means (buffer pointer management unit). Since only the pointers belonging to one set need to be output when outputting packets, even if the number of VCs to be set increases, the packets to be output can be selected at high speed for inter-VC fair queuing. realizable. Further, the operation of the selecting means of claim 5 can be realized by the instructing means of the present invention. further,
The present invention can be used as an output buffer when performing fair queuing between VCs in an output buffer type cell switch.

Further, the packet transfer apparatus of the present invention (claims 9 to 11) is constituted by connecting a plurality of buffers for temporarily accumulating the input packet in series, and the buffer connected to the front stage is to the rear stage. Towards the connected buffer,
A packet transfer device that outputs a packet according to a packet output enable / disable state determined according to a packet accumulation state inside the latter-stage buffer, wherein the former-stage buffer is capable of outputting the packet to the latter-stage buffer. From the output prohibition state to the output-disabled state, the accumulation status (packet amount) in each buffer can be monitored by monitoring the accumulation status of the buffer connected to the preceding stage when the packet is first input to the preceding buffer. It is not easily affected by external conditions, and it is easy to monitor the stable queue length.For example, when the monitored accumulated packet amount exceeds a predetermined threshold value, the congestion status is determined, and the monitored accumulated packet amount is When the threshold is exceeded, it is safe to discard the input packet according to the exceeded threshold without being affected by external conditions. And it can be performed by.

Further, the packet transfer device (claims 12 to 14) of the present invention comprises at least one buffer for temporarily accumulating the input packet, and transfer of the packet of this buffer (input to the buffer or the buffer). (Which may be any of the output from the above), and the control means for controlling the packet transfer instruction based on the history of packet transfer instructions to the buffer and the packet accumulation status of the buffer. By issuing a packet transfer instruction to the buffer, the transfer instruction history is used when determining the transfer instruction, and the accumulated number of packets notified from the buffer is calculated at the time when the transfer instruction acts on the buffer. As a result, the deterioration in performance due to the delay time is reduced.

[0077]

Embodiments of the present invention will be described below with reference to the drawings.

0. Definition of Terms The terms used in describing the embodiments of the present invention will be defined below.

(1) A packet is a concept including a fixed-length cell and can be understood as a superordinate concept of the cell. Further, in the following description, when referring to a packet, a variable length or a fixed length does not matter. Further, even when the description is limited to cells, it is merely for the sake of simplification of description, and is not particularly limited to this.

(2) Difference between packet (cell) multiplexer and packet (cell) buffer device: Packet buffer device: One or more input ports, one or more output ports and one or more buffers, A device that temporarily stores the packet input from the input port in the buffer as needed and outputs it to the output port. Particularly, a packet buffer device that outputs a packet to an output port according to a destination is called a packet switch.

Packet multiplexer: Among packet buffer devices, one having a single packet output port is called a packet multiplexer (considering the packet buffer devices for each output port, a plurality of common input ports will be used). It can be seen as a superposition of packet multiplexers). What is described about the packet multiplexer in the following description can be easily applied to the packet buffer device.

(3) Packet transfer device: Includes both a packet buffer device and a type of packet multiplexer. Further, in the following description, even when the multiplexer or the buffer device is described as an example, the invention is not particularly limited to this, and can be widely applied as a packet transfer device.

1. Inter-class Priority Control (First and Second Embodiments) First, an embodiment of a cell multiplexing apparatus that performs inter-class priority control according to the present invention will be described.

1.1 First Embodiment FIG. 1 shows an example of the configuration of a cell multiplexing device that performs priority control between classes according to the first embodiment.

The cell multiplexer of FIG. 1 has an input port # 1.
~ #N provided for each input port #
A plurality of input buffers 10 for temporarily accumulating cells input from 1 to #N, an output buffer 11 for multiplexing the cells output from the input buffer 10 and outputting them to an output port, and class management for managing all the input buffers And a section 12.

The input buffer 10 stores a cell storage unit 13 (class 1 cell storage unit 13a, class 2 cell storage unit 13b, class 3 cell storage unit) for storing the input cells for each class (class 1 to class 3). 13c) and a class multiplexing FIFO 14 that multiplexes the cells output from the cell storage unit 13 and outputs the multiplexed cells to the output buffer 11.

The class management unit 12 includes the number of cells in each cell of the cell storage unit 13 and the class multiplexing FIFO 14
The number of class-multiplexed FIFO cells is obtained, the transfer class instruction is determined by a predetermined algorithm, and broadcast to all the input buffers 10.

The cell storage unit 13 of the class designated by the transfer class instruction broadcast to the input buffer 10 transfers the cell to the class multiplexing FIFO 14 and the class multiplexing FIFO.
O14 outputs a cell to the output buffer 11 according to the control of the back pressure signal according to the congestion state in the output buffer 11.

The cell storage unit for each class 13 is normally a FIFO.
(First In First Out) Composed of memory.

Although FIG. 1 shows the case of three classes (class 1 to class 3), the first embodiment works effectively regardless of the number of classes.

Further, considering FIG. 1 as a portion of the cell switch relating to each output port, the first embodiment can be applied to the cell switch.

The output buffer 11 of FIG. 1 is a single-stage FIF.
Although it is composed of O15, any form may be used as long as it can guarantee that the cells of the class multiplexing FIFO 14 can be output to the output port within a limited time in any situation.

For example, the configuration may be such that the cells of the class multiplexing FIFO 14 are arbitrated and output to the output port without having any buffer. Further, for example, the configuration shown in FIG. 3 or 4 described later may be used.

The output buffer 16 shown in FIG.
The O is configured in a plurality of stages (two stages in FIG. 3), and the back pressure signal is connected to the FIFO in the preceding stage.

That is, the output buffer 16 of FIG. 3 has a plurality of FIFOs 18 on the input side (preceding stage), and the input buffer 1
Input links # 1 to #N provided for each output of 0
Are connected, and the outputs of the FIFOs 18 are connected to the output-side (post-stage) FIFO 19 to configure the post-stage FI.
The back pressure signal output from the FO 19 according to the congestion state is connected to each of the plurality of FIFOs 18 in the preceding stage, and the back pressure signal output from each of the FIFOs 18 in the preceding stage according to the congestion state is , Is connected to each of the plurality of class multiplexing FIFOs 14.

The output buffer 17 shown in FIG. 4 has a plurality of FIFOs (two stages in FIG. 4) as in FIG. The difference from FIG. 3 is that a plurality of FIFOs 18 on the input side are provided.
Of the queue length information (or may be the queue length information of all FIFOs) to the back pressure generation unit 20, and the back pressure generation unit 20 generates a back pressure signal from the queue length information and broadcasts it to all input links. It is to be.

For example, the queue lengths are all summed and compared with a threshold value, and if the queue length is exceeded, the input to the output buffer is prohibited by the back pressure signal. The back pressure generation unit 20 may exist in the class management unit 12.

According to the cell multiplexing apparatus for performing priority control between classes according to the first embodiment, it is not necessary to identify the class in the output buffer that requires high throughput, so that it can be realized easily. Become. The input buffer needs to manage cells for each class, but the throughput required for the input buffer is low, which facilitates implementation.

The configuration of the cell multiplexer of FIG. 1 will be described in more detail.

The number of cells in each class cell storage unit input to the class management unit 12 is equal to that of all input buffers 1 for each class.
The total number of cell storage cells per class of 0 may be used. In addition, the number of class multiplexing FIFO cells is also the same for all input buffers 10.
The sum of

The total calculation may be performed inside the class management unit 12 or may be performed outside the class management unit 12.

The cell number information is judged by the class management unit 12 to be a relatively small threshold value and the size. Whether the threshold value is a fixed value or a dynamically changing value is determined by the class management unit 1
Depending on the algorithm of No. 2, if the threshold value is a fixed value, the comparison result may be input to the class management unit instead of the number of cells. Alternatively, if any value greater than or equal to a certain value does not affect the processing of the class management unit 12, it may be used to encode and input the value greater than or equal to one code. For example, with 4 bits, the number of cells is (00
00) = 0, (0001) = 1, (0010) = 2,
(0011) = 3, ..., (1101) = 13, (111
The encoding may be performed in 16 steps of 0) = 14 and (1111) = 15 or more. This has the advantage that the input information to the class management unit 12 can be compressed and the mounting becomes easy.

By handling the total number of cells, the implementation of the class management unit 12 can be simplified. Since the transfer class instruction also broadcasts the same information to all input buffers, the class management unit does not need to recognize each input buffer individually. Therefore, even if the number of input ports increases, there is an advantage that the essential difficulty of implementation does not change.

The algorithm for the class management unit 12 to determine the transfer instruction is as follows, for example.

1. Based on the number of class-multiplexed FIFO cells, it is determined whether or not the class-multiplexed FIFO does not underflow, and a transfer instruction is issued so as not to underflow only when it is determined that there is a possibility of underflow. Underflow refers to a state in which the number of class-multiplexed FIFO cells becomes zero, and the cells in the cell storage unit for each class, which should have been output, cannot be output effectively.

2. Based on the number of cells in each cell storage unit, the class in which cells are stored in the input buffer 10 is set as a transfer instruction candidate.

3. When the transfer instruction can be given, the class having the highest priority among the classes which are candidates for the transfer instruction is obtained, and the transfer of the class is instructed.

The class management unit 12 gives a transfer class instruction without directly considering the state of the output buffer and the back pressure signal. Therefore, the cell transfer throughput according to the transfer class instruction may exceed the cell output throughput from the input buffer 10, and the class multiplexing FIFO 14 is provided to temporarily absorb the difference. By knowing the number of class multiplexing FIFO cells, the class management unit 12 controls so that the cell transfer throughput according to the transfer class instruction does not exceed the cell output throughput from the input buffer 10 for a long time.

More detailed information can be obtained by the class management unit 12 knowing the total number of cells (the number of transferred cells for each class) of the cells actually transferred from the cell storage unit for each class 13 to the class multiplexing FIFO 14 in all input buffers 10. Priority control between various classes can be performed.

In this case, the algorithm for the class management unit 12 to determine the transfer instruction is as follows, for example.

[0111] 1. From the number of cells in the class multiplexing FIFO,
It is determined whether or not the class multiplexing FIFO does not underflow, and a transfer instruction is issued so as not to underflow only when it is determined that there is a possibility of underflow. Underflow refers to a state in which the number of class-multiplexed FIFO cells becomes zero, and the cells in the class-by-class cell storage unit 13 that could originally be output cannot be output effectively.

[0112] 2. Cell storage unit for each class Based on the number of cells, the class in which cells are stored in the input buffer is a transfer instruction candidate.

3. For a class that obtains a throughput equal to or higher than the throughput predetermined for each class from the number of transfer cells for each class, the priority of the transfer instruction is lowered according to the degree. Or it is not a candidate for transfer instruction.

4. For a class that obtains a throughput equal to or lower than a predetermined throughput for each class based on the number of transfer cells for each class, the priority of the transfer instruction is increased according to the degree.

[0115] 5. When the transfer instruction can be given, the class having the highest priority among the classes which are candidates for the transfer instruction is obtained, and the transfer of the class is instructed.

1.2 Second Embodiment Next, a second embodiment will be described.

FIG. 2 shows another example of the configuration of the cell multiplexing apparatus for performing priority control between classes according to the second embodiment.

The cell multiplexer of FIG. 2 has an input port # 1.
~ #N provided for each input port #
A plurality of input buffers 100 for temporarily accumulating cells input from 1 to #N, and an output buffer 111 for multiplexing the cells output from the input buffer 100 and outputting them to an output port.
And a class management unit 112 that manages all the input buffers 100.

The input buffer 100 stores the input cells for each class (class 1 to class 3). The cell storage section 113 for each class (class 1 cell storage section 113a, class 2 cell storage section 113b, class 3 cell storage). Part 113c)
And a class multiplexing FIFO 114 that multiplexes the cells output from the cell storage unit 113 and outputs the multiplexed cells to the output buffer 111.
It has.

The class management unit 112 has a cell storage unit 113.
The number of cells in each class cell storage section and the number of cells in the output buffer are obtained, a transfer class instruction is determined from a predetermined algorithm, and broadcast to all input buffers 100.

The cell storage unit 113 of the class designated by the transfer class instruction broadcast to the input buffer 100 transfers the cell to the class multiplexing FIFO 114, and the class multiplexing FIFO 114 sets the congestion state in the output buffer 111. The cell is output to the output buffer 111 according to the control of the corresponding back pressure signal.

The cell storage unit 113 for each class is normally FIF.
Composed of O.

FIG. 2 shows the case of three classes (class 1 to class 3), but the second embodiment works effectively regardless of the number of classes.

Considering FIG. 2 as a portion of the cell switch relating to each output port, the second embodiment can be applied to the cell switch.

The output buffer 111 of FIG. 2 may take any form as long as it can guarantee that the cells of the class multiplexing FIFO can be output to the output port within a limited time under any circumstances.

For example, the configuration shown in FIG. 4 may be used.

In this case, the back pressure generator 20 may be present in the class manager 112. The number of cells Nm in the output buffer is added by the back pressure generation unit 20 and output to the class management unit 112 in FIG.

According to the cell multiplexer of the second embodiment for performing priority control between classes, it is not necessary to identify the class in the output buffer that requires high throughput, so that it can be easily realized. is there. The input buffer 100 needs to manage cells for each class, but the throughput required for the input buffer 100 is low, which facilitates implementation.

The configuration of the cell multiplexer of FIG. 2 will be described in more detail.

The number of cell storage cells for each class input to the class management unit 112 may be the total number of cell storage cells for each class of all input buffers 100 for each class.

The total calculation may be performed inside the class management unit 112 or outside the class management unit 112.

The class management unit 112 determines the relatively small threshold value and the size of the cell number information. Whether the threshold value is a fixed value or a dynamically changing value depends on the algorithm of the class management unit 112. If the threshold value is a fixed value, the comparison result is used instead of the number of cells. You may input into the class management part 112. Alternatively, if any value greater than a certain value does not affect the processing of the class management unit 112, it may be used to encode and input the value greater than that value into one code. For example, with 4 bits, the number of cells is (0000) = 0, (0001) = 1, (001
0) = 2, (0011) = 3, ..., (1101) = 1
The encoding may be performed in 16 stages of 3, (1110) = 14, (1111) = 15 or more. This has the advantage that the input information to the class management unit can be compressed and the implementation becomes easier.

By handling the total number of cells, the implementation of the class management section 112 can be simplified. Since the transfer class instruction also broadcasts the same information to all the input buffers 100, the class management unit 112 determines that the input buffers 100
Need not be individually recognized. Therefore, even if the number of input ports increases, there is an advantage that the essential difficulty of implementation does not change.

The algorithm for the class management unit 112 to determine the transfer instruction is as follows, for example.

[0135] 1. Based on the number of cells in the output buffer 111, it is determined whether or not the output buffer 111 underflows, and only when it is determined that there is a possibility of underflow, a transfer instruction is given so as not to underflow. The underflow is a state in which the number of output buffer cells becomes zero and the cells of the class-by-class cell storage unit 113, which should be able to be output, cannot be output effectively.

[0136] 2. Based on the number of cells in each cell storage unit, the class in which cells are stored in the input buffer 100 is set as a transfer instruction candidate.

3. When the transfer instruction can be given, the class having the highest priority among the classes which are candidates for the transfer instruction is obtained, and the transfer of the class is instructed.

The class management unit 112 uses the output buffer 111.
The transfer class is instructed by directly considering the state of. Therefore, if a sufficient buffer amount of the output buffer 111 is prepared,
Since the back pressure signal does not suppress the cell output from the input buffer, the class multiplexing FIFO 114 is basically unnecessary. By knowing the number of cells in the output buffer, the class management unit 112 controls so that the cell transfer throughput according to the transfer class instruction does not exceed the cell output throughput from the output buffer 111 continuously for a long time.

As described above, the back pressure signal to the input buffer 100 and the class multiplexing FIFO 114 are basically unnecessary, but they work effectively when the buffer amount of the output buffer 111 is not sufficient. If these are not provided, the buffer amount of the output buffer 111 can be reduced as compared with the case without them.

More detailed information can be obtained by the class management unit 112 by knowing the number of cells (the number of cells transferred for each class) obtained by summing the cells actually transferred from the cell storage unit for each class 113 to the class multiplexing FIFO 114 in all input buffers. Priority control between classes can be performed.

In this case, the algorithm for the class management unit 112 to determine the transfer instruction is, for example, as follows.

1. Based on the number of cells in the output buffer 111, it is determined whether or not the output buffer 111 underflows, and only when it is determined that there is a possibility of underflow, a transfer instruction is given so as not to underflow. The underflow is a state in which the number of output buffer cells becomes zero and the cells of the class-by-class cell storage unit 113, which should be able to be output, cannot be output effectively.

[0143] 2. Based on the number of cells in each cell storage unit, the class in which cells are stored in the input buffer 100 is set as a transfer instruction candidate.

[0144] 3. For a class that obtains a throughput equal to or higher than the throughput predetermined for each class from the number of transfer cells for each class, the priority of the transfer instruction is lowered according to the degree. Or it is not a candidate for transfer instruction.

4. For a class that obtains a throughput equal to or lower than a predetermined throughput for each class based on the number of transfer cells for each class, the priority of the transfer instruction is increased according to the degree.

5. When the transfer instruction can be given, the class having the highest priority among the classes which are candidates for the transfer instruction is obtained, and the transfer of the class is instructed.

1.3 Advantages of Cell Multiplexing Apparatus According to First and Second Embodiments As described above, the cell multiplexing apparatus that performs priority control between classes according to the first and second embodiments. According to this, since it is not necessary to identify the class in the output buffer that requires high throughput, there is an advantage that it is easy to realize even when the number of input ports is large.

[0148] 2. Fair Queuing (Third to Seventh Embodiments) Next, an embodiment of a cell multiplexer for performing fair queuing between VCs according to the present invention will be described.

2.1 Third Embodiment (Output Buffer Type Cell Multiplexer) FIG. 5 shows an example of the configuration of a cell multiplexer which performs inter-VC fair queuing according to the third embodiment.

The cell multiplexer of FIG. 5 is called an output buffer type and is provided corresponding to each of the input ports # 1 to #N, and the cells input from the input ports # 1 to #N are
A plurality of speed conversion circuits 200 that convert the speed to a speed that is N times as many as the number of input ports, and an output buffer 201 that temporarily accumulates the cells output from the speed conversion circuit 200 and outputs them to the output ports.
And

The output buffer 201 outputs the input cell to V
A VC separation unit 201a that separates each C, a plurality of VC FIFOs 201b that are provided for each VC, and a cell selection unit 201c that selects a cell output from each of the plurality of VC FIFOs 201b and outputs the selected cell to an output port. I have it.

The FIFO 201b for each VC must have a large capacity to obtain a sufficiently good cell loss rate. Due to the non-blocking condition, the input speed of the FIFO 201b for each VC must be N times the input port. When the input port speed is high or the number of input ports is large, a high-speed and large-capacity memory that satisfies such throughput is not inexpensive, and a complex queue for each VC while satisfying such throughput. It is also difficult to manage.

2.2 Fourth Embodiment (Cell Multiplexer Using Concept of "Cage") Next, a fourth embodiment will be described.

FIG. 6 shows an example of the configuration of a cell multiplexing device using the concept of a basket according to the fourth embodiment.

The cell multiplexer shown in FIG. 6 is provided corresponding to each of the input ports # 1 to #N, and has a plurality of inputs for temporarily accumulating cells input from the input ports # 1 to #N. A buffer 210 and an output buffer 211 that multiplexes the cells output from each input buffer 210 and outputs the multiplexed cells to an output port are provided, and each input buffer 210 receives a back pressure signal according to a congestion state in the output buffer 211.
Control the cell output of.

This cell multiplexing device is provided with a basket management unit 212 for managing the output-permitted cell set.

Of the cells stored in the input buffer 210, the set of cells permitted to output (output permitted cell set) is called a basket. The cell output from the input buffer 210 is selected from the basket 213.

The car management unit 212 inputs the number of cells contained in the car 213, determines a cell transfer instruction to the car 213 by a predetermined algorithm, and broadcasts it to all the input buffers 210.

The input buffer 210 is a cell accumulated in the input buffer 210 other than the cell determined as the basket 213 by the cell transfer instruction, and adds to the basket 213 a set 214 of cells to be output by the same time. .

Considering FIG. 6 as a portion of the cell switch relating to each output port, the fourth embodiment can be applied to the cell switch.

The output buffer 211 of FIG. 6 may take any form as long as it can guarantee that the cells of the basket can be output to the output port within a limited time in any situation.

For example, the basket 21 without any buffer
A configuration in which the cell No. 3 is arbitrated and output to the output port may be used. Further, for example, the configuration shown in FIG. 3 or 4 may be used.

Note that, in FIG. 4, the back pressure generating unit 20 may exist in the car management unit 212.

According to the cell multiplexer for performing fair queuing between VCs of the fourth embodiment, the output buffer which requires a high throughput has a simple structure and can be easily realized. . Although it is necessary for the input buffer to manage cells by a basket, the throughput required for the input buffer is low, so that it is easy to realize.

The configuration of the cell multiplexer of FIG. 6 will be described in more detail.

The number of cells in the basket input to the basket management unit 212 may be the total number of cells in the basket of all the input buffers 210.

The calculation of the total may be performed inside the car management unit 212 or outside the car management unit 212.

With respect to the cell number information, the car management unit 212 determines a relatively small threshold value and a size. Whether the threshold value is a fixed value or a dynamically changing value is determined by the car management unit 21.
Depending on the algorithm of No. 2, if the threshold value is a fixed value, the comparison result may be input to the car management unit 212 instead of the number of cells. Alternatively, if any value greater than or equal to a certain value does not affect the processing of the car management unit 212, it may be used to encode and input the value greater than or equal to one code. For example, with 4 bits, the number of cells is (0000) = 0, (0001) = 1, (0010) =
2, (0011) = 3, ..., (1101) = 13, (1
16) 110) = 14, (1111) = 15 or more
It may be encoded in stages. This has the advantage that the input information to the basket management unit 212 can be compressed and the mounting becomes easy.

By handling the total number of cells, the implementation of the basket management unit 212 can be simplified. Since the same information is broadcast to all the input buffers 210 in the cell transfer instruction to the car, the car management unit 212 is
There is no need to recognize 0 individually. Therefore, even if the number of input ports increases, there is an advantage that the essential difficulty of implementation does not change.

The algorithm for the car management unit 212 to determine the cell transfer instruction to the car 213 is as follows, for example.

That is, from the number of cells in the car Nk, the car 2
It is determined whether or not the number of cells in 13 does not underflow, and a transfer instruction is given so as not to underflow only when it is determined that there is a possibility of underflow. Underflow refers to a state in which the number of cells in the basket Nk becomes zero and the cells of the input buffer 210 that should be able to be output cannot be effectively output.

The input buffer 210 adds a set of cells 214 to be output by the same time to the basket 213 in response to a cell transfer instruction to the basket 213. For example, in the case of performing fair queuing between VCs weighted with a value Nx set for each VC, the cells to be output by the same time are cells not in the basket 213 in each input buffer 210 and each VC. Is a collection of the oldest Nx cells.

Since the transfer instruction is broadcast to all the input buffers 210, the basket 213 has a plurality of input buffers 21.
The cells enter evenly between VCs through 0. By transferring the cells of the basket 213 to the output buffer 211 with priority over the cells outside the basket 213, a plurality of input buffers 21
It is possible to evenly transfer cells to the output buffer 211 between VCs through 0.

If the output buffer 211 is configured to be able to output the cell input from the car 213 within a certain time in any case, the cells evenly transferred between the VCs to the car 213 have delay fluctuations of that time. It is output from the output port.

FIG. 6 shows, by way of example, input ports # 1 and #.
2 and 1 in the #N input buffer 210,
It shows a state in which three VCs are queued. When the weights of all VCs are the same, if the fair queuing between VCs is performed, the output from each input buffer 210 needs to be in a ratio of 2: 1: 1. The cell multiplexer of the present embodiment is configured such that all the input buffers 2 from the basket management unit 212 are input.
By the cell transfer instruction to the basket 213 that is broadcast to 10, the number of cells in the basket 213 becomes a ratio of 2 to 1 to 3 in each input buffer, and as a result, the output from the output buffer also becomes 2
The ratio is 1 to 3.

There are two methods for inputting cells to the basket 213. Here, when transfer is instructed, each V
An example will be described in which the oldest Nx cells (values set for each VC) of each C are put in the basket.

One method is such that even if the cell input to the input buffer 210 satisfies the condition to be put in the basket 213, it is not initially put in the basket 213. The cell is transferred to the car 213 only when the car management unit 212 instructs the cell transfer. As a result, the number of cells in the car is reduced except when the car management unit 212 instructs the cell transfer.

Another method is to insert cells into the basket 213 from the beginning when the cells input to the input buffer 210 satisfy the conditions for being inserted into the basket 213. That is, the VC that has transferred Nx cells to the basket 213 at the time of the transfer instruction cannot insert the cell into the basket 213 until the next transfer instruction is issued, but does not transfer the cells to the basket 213 at the time of the transfer instruction. In addition, a VC whose number of transferred cells is less than Nx can put 213 input cells in the basket without a transfer instruction until Nx.
As a result, the number of cells in the basket may increase between transfer instructions, but it decreases when almost all active VCs transfer Nx cells. It should be noted that this embodiment works effectively by either method.

The determination of the congestion state of the cell multiplexer of the fourth embodiment may be performed by monitoring the information that varies depending on the traffic for each VC by a predetermined method. And
Based on this congestion determination, the traffic control information may be notified to the terminal for each VC.

The variable information to be monitored is, for example, the relationship between the number of accumulated cells, the number of input cells per fixed time and its target value, and the relationship between the time when a fixed number of cells are input and its target value. VC with a large number of accumulated cells, VC with a large number of input cells per fixed time far from the target value, and V with a fixed number of cells input far from the target value and short V
Judge C as a congested VC.

E in header of cell of congested VC
It is possible to notify the terminal of the traffic control information by marking the FCI or rewriting the RM cell passing through.

2.3 Fifth Embodiment (Other Embodiment of Cell Multiplexing Device Using Concept of "Cage") Next, a fifth embodiment will be described.

FIG. 7 shows another example of the configuration of the cell multiplexing apparatus using the concept called a basket according to the fifth embodiment.

The cell multiplexer shown in FIG. 7 is provided corresponding to each of the input ports # 1 to #N, and has a plurality of cells for temporarily accumulating cells input from the input ports # 1 to #N. An input buffer 220 and an output buffer 221 that multiplexes cells output from the input buffer 220 and outputs the multiplexed cells to an output port are provided, and a cell output of the input buffer 220 is controlled by a back pressure signal according to a congestion state in the output buffer 221. .

This cell multiplexing device comprises a basket management unit 222 for managing the output permitted cell set.

Of the cells stored in the input buffer 220, the set of cells permitted to output (output permitted cell set) is called a basket. The cell output from the input buffer is selected from the basket 223.

The car management unit 222 inputs the number of cells in the output buffer, and uses the predetermined algorithm to carry out the car 22 operation.
3 to determine the cell transfer instruction to all input buffers 22
Broadcast to 0.

According to the cell transfer instruction, the input buffer 220 is a set 22 of cells to be output by the same time among the cells stored in the input buffer 220 other than the basket 223.
Add 4 to the basket 223.

Considering FIG. 7 as a portion of the cell switch relating to each output port, this embodiment can be applied to the cell switch.

The output buffer 221 of FIG. 7 may take any form as long as it can guarantee that the cells of the basket 223 can be output to the output port within a limited time in any situation.

For example, the configuration shown in FIG. 4 may be used.
In this case, the back pressure generation unit 20 is the car management unit 2
22 may exist. The number of cells in the output buffer is added by the back pressure generation unit 20 and output to the car management unit 222.

According to the cell multiplexer for performing fair queuing between VCs according to the fifth embodiment, the output buffer which requires high throughput has a simple structure, and therefore can be easily realized. is there. Although it is necessary for the input buffer to manage cells by a basket, the throughput required for the input buffer is low, so that it is easy to realize.

The configuration of the cell multiplexer of FIG. 7 will be described in more detail.

For the cell number information, the car management unit 222 determines a relatively small threshold value and size. Whether the threshold value is a fixed value or a dynamically changing value is determined by the car management unit 22.
Depending on the algorithm of No. 2, if the threshold value is a fixed value, the comparison result may be input to the car management unit 222 instead of the number of cells. Alternatively, if any value greater than a certain value does not affect the processing of the car management unit 222, it may be used to encode and input the value greater than that value into one code. For example, with 4 bits, the number of cells is (0000) = 0, (0001) = 1, (0010) =
2, (0011) = 3, ..., (1101) = 13, (1
16) 110) = 14, (1111) = 15 or more
It may be encoded in stages. This has the advantage that the input information to the car management unit 222 can be compressed and mounting becomes easy.

The algorithm by which the car management unit 222 determines the cell transfer instruction to the car 223 is as follows, for example.

That is, it is determined from the number of cells in the output buffer whether the number of cells in the output buffer 221 does not underflow, and a transfer instruction is issued so as not to underflow only when it is determined that there is a possibility of underflow. . Underflow refers to a state in which the number of cells in the output buffer becomes zero and the cells of the input buffer 220, which should have been able to output, cannot be output effectively.

The input buffer 220 adds to the basket 223 a set 224 of cells to be output by the same time in response to a cell transfer instruction to the basket 223. For example, when performing fair queuing between VCs weighted by a value Nx set for each VC, the set of cells to be output by the same time is a cell that is not in the basket 223 in each input buffer. It is the collection of the oldest Nx cells for each.

Since the transfer instruction is broadcast to all the input buffers, the basket 223 has V input through a plurality of input buffers.
Cells are evenly entered between Cs. By transferring the cells of the basket 223 to the output buffer 221 with priority over the cells outside the basket, it is possible to transfer the cells to the output buffer 221 fairly among the VCs through the plurality of input buffers 220. If the output buffer 221 is configured to be able to output the cell input from the basket 223 within a certain time in any case, the cells evenly transferred to the basket 223 between the VCs have a delay fluctuation of that time, It is output from the output port.

FIG. 7 shows, by way of example, input ports # 1 and #.
2, 2 in the #N input buffer 220, 1 in the #N input buffer 220,
It shows a state in which three VCs are queued. When the weights of all VCs are the same, if fair queuing between VCs is performed, the output from each input buffer 220 needs to be in a ratio of 2: 1: 1.

The cell multiplexing device of FIG.
Basket 22 broadcast from 2 to all input buffers 220
By the cell transfer instruction to 3, the number of cells in the car becomes 2: 1: 1 in each input buffer, and as a result, the output from the output buffer 221 also becomes 2: 1: 1.

There are two methods for inputting cells to the basket 223. Here, when transfer is instructed, each V
An example will be described in which the oldest Nx cells (values set for each VC) of each C are put in the basket.

One method is such that even if the cell input to the input buffer 220 satisfies the condition of being put in the basket 223, it is not put in the basket at first. The cell 22 is used only when the cell management unit 222 instructs the cell transfer.
3 is transferred. As a result, the number of cells in the car is reduced except when the car management unit 222 instructs the cell transfer.

As another method, when the cell input to the input buffer 220 satisfies the condition to be put in the basket 223, the cell is put in the basket 223 from the beginning. That is, the VC that has transferred Nx cells to the basket 223 at the time of the transfer instruction cannot insert the cell into the basket 223 until the next transfer instruction is issued, but does not transfer the cells to the basket 223 at the time of the transfer instruction. In addition, a VC whose number of transfer cells is less than Nx can put the input cells in the basket 223 until the number of input cells reaches Nx, even if there is no transfer instruction.
As a result, the number of cells in the basket may increase between transfer instructions, but it decreases when almost all active VCs transfer Nx cells. It should be noted that this embodiment works effectively by either method.

The determination of the congestion state of the cell multiplexer of the fifth embodiment may be carried out by monitoring the information, which varies depending on the traffic, for each VC by a predetermined method. And
The cell multiplexer may notify the terminal of the traffic control information for each VC based on the congestion judgment.

The variable information to be monitored is, for example, the relationship between the number of accumulated cells, the number of input cells per fixed time and its target value, and the relationship between the time when a fixed number of cells are input and its target value. VC with a large number of accumulated cells, VC with a large number of input cells per fixed time far from the target value, and V with a fixed number of cells input far from the target value and short V
Judge C as a congested VC.

E in the header of the cell of the congested VC
It is possible to notify the terminal of the traffic control information by marking the FCI or rewriting the RM cell passing through.

2.4 Advantages of Cell Multiplexing Apparatus According to Fourth and Fifth Embodiments As described above, the concept of the output-permitted cell set (basket) according to the fourth to fifth embodiments is explained. According to the cell multiplexing device used, since the output throughput of each input buffer is adjusted by controlling the cells that are put into the output-permitted cell set, fair queuing between VCs can be performed, and fault tolerance in ABR service is achieved. It is also possible to achieve fairness in UBR services.

2.5 Sixth Embodiment (Cell Group F
Cell Buffer Device Using IFO) Next, an embodiment of a cell buffer device for performing inter-VC fair queuing according to the present invention will be described.

FIG. 8 shows a configuration example of a cell buffer device using a cell group FIFO according to the sixth embodiment.

In FIG. 8, the connection identification information of the cell input from the input link is notified to the buffer pointer management unit 230, the write pointer indicating the write position of the cell is obtained from the buffer pointer management unit 230, and the cell is temporarily changed to the cell. It is a cell buffer device that stores the cells in the buffer 231 and reads cells from the cell buffer 231 based on the read pointer indicating the read cells from the buffer pointer management unit 230 and outputs the cells to the output link.

The buffer pointer management unit 230 manages a buffer pointer indicating the position of the accumulated cell on the cell buffer 231.

The buffer pointer management unit 230 uses a FIFO to store a plurality of cell groups, which are a set of buffer pointers.
A cell group FIFO 232a to be managed, an output waiting cell group FIFO 232b, and a cell group selection unit 2
33 and an empty buffer pointer management unit 234.

At the time of cell input, the buffer pointer management unit 230 obtains an empty buffer pointer from the empty buffer pointer management unit 234 and sets it as the write pointer, and the cell group selection unit 233 sets the write pointer to the cell group based on the connection identification information. FIFO2
The cell group is instructed so that a number determined in accordance with a predetermined weight for each VC is sequentially entered from the head cell group of 32a, and the cell group FIFO 232a inputs the write pointer to the instructed cell group in accordance with the cell group instruction. .

When outputting cells, the cell group FIFO2
A cell group is output from the head of 32a, a buffer pointer is further output from the cell group to be the read pointer, and the read pointer is returned to the empty buffer pointer management unit 234.

In FIG. 8, the cell group FIFO 232a is used.
It shows the configuration in the case where there is a possibility that there are multiple cell groups that are output from, and are waiting for output. The cell group output from these cell group FIFO 232a is input to the output wait cell group FIFO 232b.

The cell group of the output waiting cell group FIFO 232b is a cell group whose output is permitted by some management unit outside the cell buffer 231. For example, it corresponds to the basket 231 in FIG.

The read pointer is a buffer pointer output from the head cell group of the output wait cell group FIFO 232b.

For example, all VCs have the same weight. The cell of the head cell group of the cell group FIFO 232a is the head cell of the queue (excluding the cells in the output waiting cell group FIFO 232b) considering the queue of each VC. The cell of the second cell group from the head of the cell group FIFO 232a is the second cell of the queue of each VC. The same applies to cells in the third and subsequent cell groups. When outputting these cells, the cells are output in order from the first cell group of the cell group FIFO 232a, so that the VCs are output fairly.

When a VC cell that has not arrived at all until now arrives at this buffer device, it is input to the head cell group of the cell group FIFO 232a, and the cells from the second and subsequent cells of the queue of another VC are transmitted. Is also output with priority.

As described above, according to the cell buffer device of the sixth embodiment, it is possible to perform fair queuing among VCs, but FIG.
There is an advantage that the search operation is unnecessary unlike the conventional example shown in FIG.

As a method of realizing the cell group FIFO 232a of the cell buffer device according to the sixth embodiment, for example, a method using a pointer chain or a method using a ring buffer can be considered.

2.6 Seventh Embodiment (Cell Group F
Other Embodiments of Cell Buffer Device Using IFO) Next, a seventh embodiment will be described.

FIG. 9 shows another example of the configuration of the cell buffer device using the cell group FIFO according to the seventh embodiment.

In FIG. 9, the connection identification information of the cell input from the input link is notified to the buffer pointer management unit 240, and the buffer pointer management unit 240 obtains the write pointer indicating the write position of the cell to temporarily set the cell as the cell. It is a cell buffer device that stores the cells in the buffer 241 and reads cells from the cell buffer 241 based on the read pointer indicating the read cells from the buffer pointer management unit 240 and outputs the cells to the output link.

The buffer pointer management unit 240 manages the buffer pointer indicating the position of the accumulated cell on the cell buffer 241.

The buffer pointer management unit 240 is composed of a cell group FIFO 242 that performs FIFO management of a cell group that is a set of buffer pointers, a cell group selection unit 243, and an empty buffer pointer management unit 244.

At the time of cell input, the buffer pointer management unit 240 obtains an empty buffer pointer from the empty buffer pointer management unit 244 and sets it as the write pointer, and the cell group selection unit 243 uses the connection identification information as the write pointer. FIFO2
The cell group is instructed so that a number determined in accordance with a predetermined weight for each VC is sequentially entered from the head cell group of 42, and the cell group FIFO 242 inputs the write pointer to the instructed cell group in accordance with the cell group instruction. .

At the time of cell output, the cell group FIFO2
A buffer pointer is output from the head cell group 42 to be the read pointer, and the read pointer is returned to the empty buffer pointer management unit 244.

In FIG. 9, a cell group waiting for output in the cell group FIFO 242 is shown as an output waiting cell group FIFO 242b.

The cell group of the output waiting cell group FIFO 242b is a cell group whose output is permitted by some management unit outside the cell buffer 241. For example, it corresponds to the basket of FIG.

The read pointer is a buffer pointer output from the head cell group of the output waiting cell group FIFO 242b.

For example, all VCs have the same weight. The cell of the head cell group of the cell group FIFO 242 (that is, the cell group in the output waiting cell group FIFO 242b) is the head cell of the queue when considering the queue of each VC. The cell of the second cell group from the head of the cell group FIFO 242 is the second cell of the queue of each VC. The same applies to cells in the third and subsequent cell groups. When outputting these cells, the cells are output in order from the head cell group of the cell group FIFO 242, so that the VCs are output fairly.

When a VC cell that has not arrived at all until now arrives at this buffer device, it is input to the head cell group of the cell group FIFO 242,
It is output with priority over the second and subsequent cells in the queues of other VCs.

As described above, according to the cell buffer device of the seventh embodiment, it is possible to perform fair queuing among VCs, while FIG.
There is an advantage that the search operation is unnecessary unlike the conventional example shown in FIG.

As a method of realizing the cell group FIFO 242 of the cell buffer device according to the seventh embodiment, for example, a method using a pointer chain or a method using a ring buffer can be considered.

2.7 Data Structure Used in Cell Buffer Device According to Sixth Embodiment Next, the data structure used in the cell buffer device according to the sixth embodiment (see FIG. 8) will be described.

FIG. 10 and FIG. 11 show an example of the data structure when the buffer device described in FIG. 8 is realized by the pointer chain method.

Broadly divided, as shown in FIG.
The table 250, the cell group FIFO 232a, the output waiting cell group FIFO 232b, the empty buffer pointer chain 251, and the empty cell group chain 252 as shown in FIG.

The cell group FIFO 232a has cell group FIFO management data 253 for managing it, and the output waiting cell group FIFO 232b has output waiting cell group FIFO management data 254 for managing it.

The cell group and empty buffer pointer chain 251 is a chain of buffer pointers, and the cell group FIFO 232a and empty cell group chain 252 are chains of cell group management data 255.

Output waiting cell group FIFO 232b
Is a list of pointers (Ptr1, Ptr) pointing to cell groups in the output waiting cell group FIFO management data 254.
2, Ptr3, ...).

The cell group FIFO 232a and the output waiting cell group FIFO 232b may be ring buffer type.

When a cell is input, it is necessary to determine to which cell group the write pointer extracted from the free buffer pointer chain 251 is input. Therefore, first, the corresponding area of the VC table 250 is read. In the VC table 250, Nx is a weight of the VC, Nc is a work variable, Qlen is the number of accumulated cells of the VC,
Ptr is a pointer to the end of the cell group in which the cells of that VC are accumulated.

First, Qlen is checked and its V
Check if the C cell is currently stored in the buffer device. If Qlen is zero, it is placed in the first cell group of the cell group FIFO 232a. Qle
Even if n is 1 or more, Ptr is the output waiting cell group F
When referring to the cell group in the IFO 232b,
It is placed in the first cell group of the cell group FIFO 232a.

In other cases, 1.0 is added to Nc and compared with Nx, and if Nx is larger, it is put in the cell group pointed to by Ptr. Otherwise, it is placed next to the cell group pointed to by Ptr. Put in cell group.

Now, the procedure for updating Nc when a cell is input will be described. As described above, when the buffer pointer is input to the head cell group of the cell group FIFO 232a for the VC for the first time, Nc: =
1.0. In other cases, Nc is Nc: = Nc +
Update to 1.0. As a result, if Nx > Nc,
Put the buffer pointer in the cell group. vice versa,
If Nx <Nc, cell group FIFO 232a
At the same time when the buffer pointer is put in the cell group next to, Nc: = Nc-Nx is rewritten (that is, 0 <N
c < Nx).

If it is necessary to insert a buffer pointer into the cell group next to the last cell group of the cell group FIFO 232a, the empty cell group chain 2
It suffices to take out the cell group management data 255 from the beginning of 52, put it at the end of the cell group FIFO 232a, and put the buffer pointer in that cell group. In the output wait cell group FIFO management data 254, pointers Ptr1, Ptr2, Ptr3, ... Pointing to the cell groups are shift registers. The cell group indicated by Ptr1 is the head of the FIFO, and the buffer interface output from this cell group serves as a read pointer. The read pointer is input to the end of the empty buffer pointer chain 251. When the buffer pointer of the cell group indicated by Ptr1 becomes empty, the cell group is input to the end of the empty cell group chain 252. And n > 2
Pointers Ptr (n) for all n of
Shift to 1) and output the buffer pointer from the cell group pointed to by the new Ptr1.

As described above, it is necessary to judge whether Ptr of the VC table 250 points to a cell group waiting for output when a cell is input. Therefore, the output-waiting cell group FIFO management data 254 needs to have a configuration that allows easy retrieval.

When a new cell group is transferred from the cell group FIFO 232a to the output waiting cell group FIFO 232b, the number of cell groups in the output waiting cell group FIFO management data 254 is incremented (set to m), and Ptr (m) Cell group FIFO23
Point to the cell group output from 2a.

The cell buffer device according to the sixth embodiment can be easily applied to an input buffer using the concept of a basket as shown in FIGS. 6 and 7. In that case,
The output waiting cell group FIFO 232b corresponds to a basket. It can also be applied to the output buffer of FIG.

2.8 Data Structure Used in Cell Buffer Device According to Seventh Embodiment Next, a data structure used in the cell buffer device according to the seventh embodiment (see FIG. 9) will be described.

12 and 13 show an example of the data structure when the buffer device described in FIG. 9 is realized by the pointer chain method.

As shown in FIG. 12, VC is roughly divided into
The table 260, the cell group FIFO 242, the empty buffer pointer chain 261, and the empty cell group chain 262 as shown in FIG.

Inside the cell group FIFO 242,
A cell group FIFO that has an output waiting cell group FIFO 242b and manages the cell group FIFO 242.
O management data 263, output waiting cell group FIFO2
There is output waiting cell group FIFO management data 264 for managing 42b.

The cell group and empty buffer pointer chain 261 is a buffer pointer chain, and the cell group FIFO 242 and empty cell group chain 262 are cell group management data 265 chains.

Output wait cell group FIFO 242b
Are some cell groups at the head of the cell group FIFO 242. That is, in FIG. 12, the output wait cell group FIFO 242 is from the cell group pointed by the head pointer of the cell group FIFO management data 263 to the cell group pointed by the end pointer of the output wait cell group FIFO management data 264.

The cell group FIFO 242 and the output waiting cell group FIFO 242b may be ring buffer type.

When a cell is input, it is necessary to determine to which cell group the write pointer fetched from the free buffer pointer chain 261 is input. Therefore, first, the corresponding area of the VC table 260 is read. In the VC table 260, Nx is the weight of the VC, Nc is the work variable, Qlen is the number of accumulated cells of the VC,
Ptr is a pointer to the end of the cell group in which the cells of that VC are accumulated.

First, Qlen is checked and its V
Check if the C cell is currently stored in the buffer device. If Qlen is zero, it is put in the first cell group of the cell group FIFO 242.

In other cases, 1.0 is added to Nc and compared with Nx, and if Nx is larger, it is put in the cell group pointed to by Ptr. Put in cell group.

Here, the procedure for updating Nc when a cell is input will be described. As described above, when the buffer pointer is input to the head cell group of the cell group FIFO 242 for the VC for the first time, Nc: = 1.
Set to 0. Otherwise, replace Nc with Nc: = Nc + 1.
Update to 0. As a result, if Nx > Nc, put a buffer pointer in the cell group. On the contrary, if Nx <Nc, the buffer pointer is put in the next cell group of the cell group FIFO 242, and at the same time N
Rewrite as c: = Nc-Nx (that is, 0 <Nc < N
x).

If the cell group is not in the cell group FIFO 242 when the cell is input, if there is a need to put a buffer pointer in the cell group next to the last cell group in the cell group FIFO 242, the empty cell group chain 262 Cell group management data 265 from the beginning of the
It is sufficient to put it at the end of 2 and put a buffer pointer in the cell group.

The output waiting cell group FIFO management data 264 has a pointer indicating the end of the output waiting cell group FIFO 242b. Cell group F at the beginning
It is the same as the first cell group of the IFO management data 263.

The buffer pointer is output from the head cell group of the output waiting cell group FIFO 242b (the same cell group as the head of the cell group FIFO), and this buffer pointer serves as a read pointer. The read pointer is input to the end of the empty buffer pointer chain 261.

When the buffer pointer of the head cell group of the cell group FIFO 242 becomes empty, the cell group management data 265 is read from the cell group FIFO 242.
Is output and is input to the end of the empty cell group chain 262.

When a cell group is newly transferred to the output waiting cell group FIFO 242b, the pointer indicating the end of the output waiting cell group FIFO management data 264 is changed to point to the next cell group on the cell group FIFO 242.

The cell buffer device according to the seventh embodiment can be easily applied to an input buffer using the concept of a basket as shown in FIGS. 6 and 7. In that case,
The output waiting cell group FIFO 242b corresponds to a basket. It can also be applied to the output buffer of FIG.

2.9 Advantages of Cell Buffer Devices According to Sixth and Seventh Embodiments As described above, according to the cell buffer devices for performing inter-VC fair queuing according to the sixth to seventh embodiments. For example, the processing for searching the VC table is not necessary, and therefore, it can be easily realized without depending on the upper limit of the number of VCs that can be set.

2.10 Inter-Flow Weighted Fair Queuing The cell buffer device for performing inter-VC fair queuing described above has dealt with the case of handling cells that are fixed-length packets. Even in a packet buffer device capable of simultaneously handling packets of different lengths, the input packet can be fairly output based on the weight determined for each flow as described below.

The flow here is a set of packets identified by a certain criterion as shown in the following example.

A so-called flow of an IP network (identified by a combination of a source address, a source report, a destination address and a destination port), or a VCC or VPC of an ATM network.

IP network service class (guaran)
teded, controlled-load, best
-Effort, etc.) or the service category of the ATM network (CBR, VBR, ABR, etc.).

Difference in protocol (TCP / IP, DE
Cnet, SNA, AppleTalk, etc.)-Application differences (ftp, telnet, etc.)-Different organizations that share the same bucket buffer device (such as by company) Traffic is handled by treating these as different flows in the packet buffer device of the present invention. Can be separated from each other.

First, the general inter-flow weighted fair queuing will be described with reference to FIG. The purpose of this packet buffer device is to fairly output the packets accumulated in the device according to the weight of the flow. The operation is easy to understand by considering a FIFO for each flow as shown in FIG. In the figure, there are queues (FIFOs) of three flows of flow 1, flow 2 and flow 3, and packets of various lengths are accumulated in each queue. The number attached to the packet in the figure is the length of the packet in bytes.

When a packet is input to this packet buffer device, the processing is to determine the flow to which the input packet belongs and accumulate it in the queue for each flow.

On the other hand, it is necessary to fairly output the packets among the flows, and it is important to output the packets of which queue and in which order. One method will be described according to the situation of FIG. In order to simplify the explanation, the weight of each flow is the same here. The unit of fairness is provisionally set to 500 bytes here.

First, a packet of 500 bytes, which is a total of a packet having a length of 300 bytes and a packet having a length of 200 bytes, is output from the head of the queue of the flow 1. Next, two packets having a length of 250 bytes from the head of the queue of flow 2 are continuously output. Then, one packet with a length of 500 bytes from the head of the queue of flow 3 is output. With this output, at this point, one packet with the length of each flow byte is output. With such an output, at this point, the packets of 500 bytes are equally output from each flow, so it can be said that the packets are output fairly. Then, it is sufficient to repeat outputting the packet from each flow in order from the flow 1 again by 500 bytes. In this way, packets are output fairly among the flows.

In the above method, the unit is fair in units of 500 bytes, but the unit smaller than 500 is not necessarily fair. However, it is known that the strict realization of fairness requires a very large processing capacity of the packet buffer device, and in reality, it is often judged that the above-mentioned fairness is sufficient.

Although the number of flows is three in the above description, when the packet buffer device handles an enormous number of flows, how to search for a flow accumulating packets in the queue, The issue is whether to output packets to. The present invention solves this problem using the concept of packet groups.

The present invention is based on Z, A, B, and FIG.
The queues of all flows are divided into fixed lengths like C and D. At this time, pay attention to the fact that a fair packet output can be realized by outputting a packet with each section as a unit. The present invention manages packets by grouping them for each of these delimiters. Each group is called a packet group. Packets of multiple flows are mixed in one packet group. As for the output of the packet, first the packet of the packet group Z closest to the output side is output, and then the packet of the packet group A is output. Further B, C, D
By thus outputting the packets of the packet groups in order, the packet buffer device of the present invention can output the packets fairly among the flows.

By the way, looking at the flow 3 of the section B in FIG. 14, a packet of 350 bytes is accumulated next to a packet of 400 bytes. In the figure, the total number of packets belonging to the same segment is 500 bytes, so it is not possible to segment both the 400-byte packet and the 350-byte packet that are not divided in the packet buffer device into B. That being said, 35 arrived later at the packet buffer device.
If you do not put a 0-byte packet in delimiter B, delimiter B
A gap of 100 bytes will be generated. The handling of such a case will be described later.

The concept of the packet group of the present invention has been described above.

Next, an example of the packet buffer device of the present invention will be described more specifically with reference to FIG.

As the constituent elements of the present invention, there are a packet group, a packet group FIFO, a flow table, and an output waiting packet group.

The packet group is a group of the accumulated packets as described above. In FIG. 15, A, B, C, and D are packet groups. The packets belonging to each packet group are ordered, and the packet groups have a so-called FIFO structure.

According to the present invention, as shown in FIG.
The packet group that is the FO is further managed by the FIFO. The FIFO of this packet group is called a packet group FIFO.

The flow table stores information for each flow. In the flow table, Nx is a set value of the weight of the flow, Nc is a work variable, the accumulated amount is the total amount of accumulated packets of the flow, and Ptr is a pointer to the packet group to which the packet arrived at the end of the flow belongs. The accumulated amount has the purpose of indicating whether or not the packet buffer device is accumulating packets of that flow. For example, by accumulating the input packet length at the time of packet input and subtracting the output packet length at the time of packet output, accumulation for each flow is performed. Holds the total number of bytes in the packet.

The output waiting packet group is a packet group output from the packet group FIFO (packet group Z in the figure). When outputting a packet from the packet buffer device, a packet belonging to the output waiting packet group is output.

When a packet is input, it has to be decided which packet group the packet should be put into.

First, it is checked whether the packet of the flow is currently stored in the buffer device. The accumulated amount of the flow in the flow table is referred to from the flow identification information, and it can be determined whether it is zero. If not currently stored, the input packet is put in the first packet group (packet group A in FIG. 15) of the packet group FIFO.

Even if the accumulated amount is larger than zero, if Ptr points to the output waiting packet group (packet group Z in FIG. 15), the packet group FI is still used.
The input packet is put in the packet group A at the head of the FO.

In other cases, the input packet length and Nx
, Nc, Ptr.

Nx for each flow is:
It shows the average amount of packets managed by one packet group. Nx is set to a value larger than the maximum packet length of the flow.

Nc indicates the remaining amount that the flow can put in the packet group indicated by Ptr in the future by calculating Nx-Nc. If Nx −
If Nc ≥ (input packet length), put the input packet in the packet group pointed to by Ptr, and conversely Nx-Nc
<(Input packet length), packet group FIF
On O, put the incoming packet into the packet group next to the packet group Ptr is aiming for.

When the packet group is determined, next Nc
And Ptr values are updated. If the first packet for that flow is placed in the first packet group of the packet group FIFO, Nc: = (input packet length)
And In other cases, first, Nc: = Nc + (input packet length), and if Nx <Nc, then rewrite as Nc: = Nc-Nx (that is, 0 <Nc≤
Nx). Ptr writes a pointer to the packet group containing the input packet.

In the present invention, one packet is not managed by two packet groups. Therefore, if the length of the input packet exceeds Nx-Nc, the input packet is put in the next packet group instead of being put in the packet group pointed to by Ptr. However, in calculating Nc, one packet is divided into two packet groups and inserted. That is, Nc: = Nc + (input packet length), and if there is a portion exceeding Nx, the Nc-Nx is set as Nc of the next packet group. With this algorithm, on average, Nx packets belong to one packet group.

The packet input operation will be specifically described with reference to FIG. FIG. 15 shows a scene in which a packet having a length of 250 bytes arrives at the packet buffer device in flow 1.
At this time, Ptr of the flow 1 points to the packet group B. In order to update the flow table, Nc is changed to Nc: = Nc + (input packet length) = 200 + according to the above procedure.
250 = 450. Since this value is less than Nx, this input packet is the packet group B pointed to by Ptr.
Put in.

If the input packet length of flow 1 is 2
If 350 instead of 50, Nc: = 200 + 3
50 = 550, which exceeds Nx. Therefore, further
Nc: = Nc-Nx = 550-500 = 50 is updated,
This input packet is put into the packet group C next to the packet group B. Ptr is changed to the packet group C.

The packet group FIFO is a first-in, first-out queue, and the number of queued packet groups can be increased as necessary. For example, FIG.
Assuming that a packet having a packet length of 400 has arrived in the flow 2 in, a free packet group (packet group E) is added next to the packet group D,
The input packet will be put into the packet group E.

As described above, the processing at the time of packet input is to change the corresponding part of the flow table, put the packet in the packet group, and add an empty packet group to the packet group FIFO if necessary. Good. The processing at the time of input can be performed without searching the flow table for a plurality of flows, and the complexity of the processing does not change even if the number of flows increases.

On the other hand, the processing required when outputting a packet is simpler. That is, the packet may be output from the output waiting packet group. Before that, a packet group is output from the packet group FIFO if necessary. These processes are also possible without searching the flow table for a plurality of flows, and the complexity of the processes does not change even if the number of flows increases.

As described above, the weight Nx of each flow indicates the average amount of packets per packet group for that flow. Since the packet buffer device of the present invention outputs packets in units of packet groups, the output sleep count of each flow is N.
proportional to x

According to this packet buffer device, there is no need to perform a process for searching the flow table, and therefore a variable length packet is easily handled without depending on the upper limit of the number of flows that can be set, and a weighted and fair packet buffer device is realized. can do.

Each packet group of the present invention manages packets in the order of arrival. That is, the output order of the packets belonging to the same packet group is the arrival order through all the flows. This property has the effect of reducing packet delay fluctuations.

Also, the packet buffer device of the present invention is
Compared with the algorithm called DRR described in the related art, even if the number of VCs increases, the selection of output cells for fair queuing between VCs can be realized at high speed, and even if the weight value increases, bursts of output traffic can occur. Sex does not increase. The reason why the burst property does not increase in the present invention is that when an input packet is distributed and managed in a plurality of sets (packet groups), the packet is managed within one set independently of the flow (VC), and Flow (VC) when outputting from a set (packet group)
This is because it is output regardless of.

3. Queue Monitoring Considering Back Pressure (Eighth Embodiment) Next, a cell buffer device for performing queue monitoring considering back pressure according to an eighth embodiment of the present invention will be described.

FIG. 16 shows an example of changes in the queue length in the input buffer as described in the first, second, fourth and fifth embodiments, for example.

The cell buffer device according to the eighth embodiment is a cell buffer device in which an output is controlled by a back pressure signal to two states, that is, output is possible and output is prohibited. It is characterized in that only the number of accumulated cells at the time of the first cell input is monitored from the time when the cell is changed to the time when the output is changed to the output prohibited.

The purpose of monitoring is to judge congestion and to judge input cell discard to prevent monopolization of the buffer area when one queue is shared by a plurality of queues.

FIG. 17 shows an example of the configuration of a cell buffer device having a queue monitoring unit considering back pressure. In FIG. 17, the cell buffer device has a plurality of queues Qi (i =
1 to N), a queue table storage unit 280, a back pressure identifier (BPID) storage unit 281, and a queue monitoring unit 2
It is composed of 82.

Qlen i of the queue table stored in the queue table storage unit 280 is the number of accumulated cells of the queue,
Cnti is a congestion judgment variable (initial value is zero), and BPIDt i is a back pressure identifier (BPI) at the time of the last cell input.
D).

When a cell enters the queue, the input cell information is transferred to the queue monitoring unit 282. Further, the BPID is incremented as shown in FIG. 16 when the back pressure signal is changed from being outputable to being output prohibited. The queue monitoring unit 282 monitors the queue length based on the algorithm shown in FIG.

FIG. 18 shows an example of a buffer queue length monitoring algorithm in consideration of back pressure. This shows an example in which the queue length is monitored to determine the presence or absence of congestion.

When a cell is input to the queue Qi and cell input processing is started, Qleni is first incremented (step S1).

Next, by comparing BPID and BPIDt i, it is determined whether the queue length should be monitored or not (step S2). That is, it is monitored when the queue length that fluctuates due to the back pressure signal becomes short.

If BPID ≠ BPIDt i, the queue length should be monitored. First, it is determined whether Cnti > 1 (step S3). At this time, if Cnti > 1, it is determined that the congestion state has occurred until immediately before, and Qlen i is compared with a threshold value Qth (Qth-H) having a hysteresis for determining whether or not the congestion state is present (step. S4).

On the other hand, when Cnti > 1 is not satisfied, Qlen i
> Qth is determined (step S5). Step S4,
In step S5, the queue length Qlen i is set to Qth-H or Q
As a result of comparison with th, when these threshold values are exceeded (that is, Qlen i> Qth−H, or Qlen i
> Qth), Cnti: = Qlen i −Qth + H is performed (step S6, step S7), otherwise Cnti: = 0 (step S8, step S8).
9). Furthermore, it progresses to step S10.

At step S2, BPID == BPIDt
In the case of i, the queue length should not be monitored, and the process proceeds directly to step S10.

In step S10, it is determined whether Cnti > 1. If so, it is a congestion state, and step S1
1 and subtract “1” from Cnti (Cnti: = Cnt
i -1), if the input cell is discarded (step S12)
Subtract "1" from Qlen i (Qlen i: = Qlen
i-1). If Cnti > 1 is not satisfied (step S10), it is not in a congestion state.

Finally, the value of BPID is substituted into BPIDt i, and BPIDt i is updated (step S13).

As described above, according to the flowchart shown in FIG. 18, the first cell input from the time when the back pressure signal changes from the output enable to the output prohibition to the time when the output pressure changes from the output enable to the output prohibition next time. It means that only the accumulated number at time is monitored.

Note that H indicates a parameter relating to hysteresis. Hysteresis has the effect of reducing the vibration of determination results such as cell discard and congestion state, which is performed by monitoring the queue length. If 0 < H <Qth and no hysteresis is required, set to zero.

Although FIG. 18 shows the case where the threshold value Qth and the hysteresis parameter H use the same value for all the queues, different values may be set for each queue.

Here, a method of determining the threshold value Qth will be described. First, consider a buffer that is not controlled by the backpressure signal. This buffer has a constant rate Ri
, And output at a constant rate R0. Ri> R
When it is 0, the buffer amount Qth required to prevent the discarding of tT time even if the load (Ri-RO) is applied is Qth.
It is determined by th = (Ri-RO) * tT.

On the other hand, in the eighth embodiment, as shown in FIG. 16, the input rate is constant at Ri,
The output rate from the input buffer is zero for the Tup time (the output inhibition time from the input buffer) and Re for the Tdn time (the output possible time from the input buffer). Assuming that the changes in Tup and Tdn are small, the buffer amount Qth required for not causing the tT time discard even when this load is applied is

(Equation 1)

It becomes: Here, the average output rate R'0 from the output port is

(Equation 2)

Therefore, Qth = (Ri-R'O) × t
T, and the cell buffer device of the eighth embodiment is
It is considered that almost the same effect can be obtained by setting the same threshold value as that of a simple buffer device without back pressure.

The exact same algorithm can be applied to the case of making a cell discard decision instead of the congestion decision.

As described above, according to the cell buffer device considering the back pressure signal according to the eighth embodiment, the queue length monitoring result is not easily influenced by the external condition, and the stable queue length monitoring is performed. Is easy.

4. Modification of Cell Number Information Considering Delay (Ninth Embodiment) Next, an embodiment of a cell buffer device for modifying the cell number information according to the present invention will be described.

4.1 Ninth Embodiment (Cell Buffer Device Considering Delay) FIG. 19 shows the configuration of a cell buffer device considering delay according to the ninth embodiment.

The cell buffer device shown in FIG. 19 is roughly divided into one or more cell buffers B (Ba, Bb,
..) are connected in a plurality of stages (two stages in FIG. 19), and a management unit 301 for inputting the number of cells in each cell buffer B and issuing a transfer instruction to the cell buffer B.

The management section 301 is characterized by holding a transfer instruction history 302 and using this transfer instruction history 302 when deciding a new transfer instruction.

The management unit 301 operates on the cell buffer B from the time when the cell buffer B transmits the number of cells to the management unit 301 to the time when the transfer instruction determined by the management unit operates on the cell buffer B. The number of transfer instructions to be performed is obtained from the transfer instruction history 302, and the transfer instruction is determined from the number of transfer instructions and the number of cells.

FIG. 20 is a diagram for explaining the principle of correcting the cell number information in the cell buffer device in consideration of the delay of the present invention.

The cells input from the input links # 1 and # 2 are temporarily stored in the cell buffers Ba1 and Ba2 at the preceding stages, respectively. The cell is transferred to the cell buffer Bb according to the transfer instruction of the management unit 301, and the cell buffer Bb outputs the cell to the output link.

The management unit 301 stores in the cell number Na2 of Ba2,
The cell number Nb of Bb is transmitted, and a transfer instruction is output to Ba1 and Ba2.

Now, the cell number information from Ba2 arrives at the management section 301, the transfer instruction is determined from the information, the transfer instruction is issued to Ba2, and the delay time until the cell number of Ba2 is changed by this transfer instruction. Is the D cell cycle. Also, the cell number information arrives at the management unit from Bb, the transfer instruction is determined from the information, the transfer is instructed to Ba1 and Ba2, and the cell is transferred from Ba1 or Ba2 to Bb by this transfer instruction, and the cell of Bb is transferred. The delay time until the number changes is also assumed to be the same D cell cycle for the sake of simplicity.

FIG. 20 shows cell buffers Ba1 and B1.
It is assumed that a2 corresponds to the class 1 cell accumulating section and the class 2 cell accumulating section in FIG. 53, and the cell buffer Bb corresponds to the cell multiplexing FIFO and performs the priority control. B
The policy of cell transfer between the cell buffers a1, Ba2 and Bb is the same as in FIG. In other words, it is necessary to reduce the number of Bb storage cells, but a transfer instruction is given so that Bb is not emptied (= underflow). Further, the transfer instruction is made so as not to give an empty instruction (the transfer instruction is given to Ba2 only when the storage cell exists in Ba2).

The cell number information Na2 output from Ba2 at time t2 arrives at the management unit 301, the management unit 301 issues a transfer instruction at time t3, and the cell is output from Ba2 by the transfer instruction at time t4. And The information that the management unit 301 wants to know is the time t when the transfer instruction actually affects Ba2.
It is the number of cells of Ba2 in 4. This time point is shown by a white circle in FIG.

If Ba2 accepts a transfer instruction Ma2 times during the time period from time t2 to time t4 (= D cell period), Ba2 outputs Ma2 cells during this time, and the number of cells Ba2 at time t4 is Na2−. Ma2 (when no cell is input to Ba2).

Normally, since the transmission delay of the transfer instruction from the management unit 301 to Ba2 is constant, the number of transfer instructions Ma2 received by Ba2 is t4 such that t4−t2 = D = t3−t1.
It is equal to the number of transfer instructions output by the management unit 301 between 1 and t3. Therefore, by knowing the transfer instruction count Ma2 from the transfer instruction history 302, Ba2 from time t2 to t4
It is possible to accurately obtain the number of reduced cells of.

The same can be considered for Bb,
The amount of increase in the number of cells of Bb from time t2 to t4 (Ba2
Can be accurately obtained.

The management section 301 cannot know the number of input cells to Ba2 from time t2 to time t4. In order not to give an empty instruction to Ba2, the number of cells of Ba2 may be underestimated. Therefore, assume that the cell input to Ba2 from the input link was not from time t2 to t4.

Further, the cell output from Bb from time t2 to t4 cannot be known by the management section 301. In order to prevent Bb from underflowing, it is necessary to underestimate the number of Bb cells. Therefore, it is assumed that the cell output from Bb is continuously output from the time t2 to t4 (D cell period, so it is assumed to be D cell). Further assume that the input cell from Ba1 is also zero.

In summary, when the corrected Na2 and Nb are N'a2 and N'b, respectively, N'a2 = Na2 + 0-Ma2 N'b = Nb + Ma2-D. Therefore, the condition for the management unit 301 to give a transfer instruction to Ba2 is given by (N'b ≤ Th) and (N'a> 0). The transfer instruction to Ba1 is performed under the condition of (N'b ≤ Th) and (N'a ≤ 0). Th is usually "1". By correcting the number of cells as described above, it is possible to instruct the transfer while trying to reduce the underflow or empty instruction.

4.2 Method of Correcting Number of Cells in General Buffer Network Next, a method of correcting the number of cells in a general buffer network will be described.

FIG. 21 is used to explain the basic principle. FIG.
1 has the cell buffer network 300 and the management unit 301 as already described. The cell buffer network 300 includes a cell buffer Bx of interest. The cell buffer Bx may physically be a plurality of buffers. The management unit obtains cell number information from the cell buffer Bx and gives a transfer instruction. First, terms used in describing the present invention will be defined.

4.2.1. Definition of terms Time is a relative time with the current time being zero unless otherwise specified, and is incremented by 1 each time a cell cycle elapses.
Such a definition of time is general because it can be converted into another expression method. Also, the period from a certain time t1 to a certain time t2 may be expressed as p, and this is expressed as p = [t
1, t2). This period p includes time t1 and t2
Is not included.

The number of cells stored in the cell buffer Bx is represented by Nx. Nx is the number of accumulated cells that have arrived at the management unit 301 at the current time (t = 0).

The transfer instruction output from the management unit 301 to the cell buffer Bx at time t (t < 0) is represented by Ix (t). When the transfer is instructed, Ix (t) = 1, and when the transfer is not instructed, Ix (t) = 0.

The number of HOL cells in the cell buffer Bx that has arrived at the management section 301 at time t (t < 0) is represented by Hx (t).

The number of HOL cells is the number of cells that may be transferred from the cell buffer at one time by one transfer instruction. In particular, the HOL cell number information Hx that has arrived at the management unit 301 at the current time is represented as Hx (0).

The management unit 301 of the present invention determines the time t (t<
0) HOL cell number Hx of cell buffer Bx obtained in 0)
(T) and the transfer instruction output to the cell buffer Bx by itself.
The indication Ix (t) is stored as a history.

The number of times the management unit has instructed the cell buffer Bx to transfer during a certain period p is represented by Smx (p). p = [t
In the case of 1, t2), it is also expressed as Mx [t1, t2). That is,

(Equation 3)

FIG. 23 shows the cell buffer Bx to the management unit 3.
11 is a time chart showing a flow of cell number information to 01 and a flow of a transfer instruction from the management unit 301 to the cell buffer Bx.

As shown in this figure, the times tf, tt, th are determined. The number Nx of accumulated cells in the cell buffer Bx at time tf and the HOL of the cell buffer Bx at time th
It is assumed that the cell number Hx is the latest information that the management unit 301 can directly know about the cell buffer Bx at the current time. At this time, the management unit 301 wants to predict the number of cells stored in the cell buffer Bx at time tt.

For times tf, tt, and th, time t
1, t3, t2 are defined. The time at which the transfer instruction output by the management unit 301 reaches the cell buffer Bx at time t1 is tf, and the time at which the transfer instruction output by the management unit 301 reaches the cell buffer Bx at time t2 is tt. Similarly, time t3
The transfer instruction output by the management unit 301 is transmitted to the cell buffer Bx.
Let th be the time to arrive at.

Times t1, t2, and t3 are assumed to be times past the present time. That is, t1 <t2 < 0, t3 <
Set to 0.

4.2.2. Basic Principle Here, the basic principle of the present invention will be described. Management unit 3 of the present invention
01 predicts a change in the number of accumulated cells from the history of transfer instructions. When it is desired to obtain the number of accumulated cells at the time tt in the cell buffer Bx described above, the number of accumulated cells at the time tf in the past is transferred by the transfer instruction during this period using the history of the transfer instruction. Predict and correct the number of cells. The correction is based on the fact that the number of cells transferred by one transfer instruction is 1 or more. Especially, regarding the number of cells transferred by the first transfer instruction after time th, HO
It is based on the fact that the number of L cells is Hx or more.

4.2.3. Three functions Three functions used for modification based on the above basic principle, f
(), G () and Sc () are defined. These functions determine how much the cell buffer Bx changes from the time tf to the time tt due to the transfer of the cell according to the transfer instruction. It can be classified into three cases depending on the value of th as compared with tf and tt, and the applied function is different.

(1) Function f () The function f () is used when th = tf <tt.
The time chart at this time is shown in FIG. p1 [t1,
t2). When Hx ≠ 0 and Smx (p1) ≠ 0, Hx cells are transferred by the first transfer instruction in the period p1,
Subsequent transfer instructions are considered to be transferred cell by cell. The function f () that calculates the number of cells in the cell buffer Bx that changes from the time tf to the time tt can be obtained as follows using Hx and the transfer instruction count Smx (p1) in the period p1 as arguments.

[0363]

(Equation 4)

(2) Function g () The function g () is used when th <tf <tt.
The time chart at this time is shown in FIG. p1 = [t
1, t2) and p2 = [t3, t1).

In this case, it is necessary to classify cases depending on whether or not the first transfer instruction arriving after the time th is output from the management section 301 in the period p2. The management unit 301 in the period p2
Since the transfer instruction is not output from, the value of Hx can be used in the period p1. From time tf to time t
The function g () for calculating the number of cells of the cell buffer Bx that changes at t can be obtained as follows using Hx and the transfer instruction counts Smx (p1) and Smx (p2) of the periods p1 and p2 as arguments. .

[0366]

(Equation 5)

(3) Function Sc () The function Sc () is used when tf <tt = th. The time chart at this time is shown in FIG. p1 =
Let [t1, t2). The latest number of accumulated cells that the management unit 301 can know is the value at time tf. In this case, regarding the number of HOL cells, the information in all the periods from time tf to time tt has already arrived at the management unit 301. ing.

If the number of HOL cells at the time when the transfer instruction arrives at the cell buffer Bx is known, the number of cells to be transferred is also known. Therefore, the function Sc (which calculates the number of cells in the cell buffer changing from time tf to time tt) ) Is Ix
Using (t) and Hx (t), the period p1 can be obtained as an argument as follows.

[0369]

(Equation 6)

It is easy to apply the method of correcting the number of cells as described above to, for example, the cell multiplexer for performing priority control between classes as shown in FIG.

Further, for example, a VC as shown in FIG.
It is also easy to apply the method of correcting the number of cells to a cell multiplexer that performs fair queuing.

4.3 Advantages of Cell Buffer Device According to Ninth Embodiment As described above, according to the ninth embodiment, there is no delay between the cell buffer and the management unit that manages the cell buffer. A cell buffer device uses a history of transfer instructions when determining a transfer instruction, and corrects the number of cells transmitted from the cell buffer to the number of cells at the time when the transfer instruction acts on the cell buffer. Little deterioration of performance due to time.

5. Cell Switch (Tenth Embodiment) 5.1 Tenth Embodiment (Cell Switch) Next, as a tenth embodiment, the cell multiplexing device and the cell buffer device according to the present invention described so far are combined. The cell switch will be described.

FIG. 25 shows a plurality of input ports #i (i = 1.
-N), a plurality of input buffers IB that temporarily store the cells input from (n) and output according to back pressure, a cell switch 400 with a back pressure that outputs a back pressure signal according to an internal congestion state, and an input It comprises a basket management unit KM that transfers information to and from the buffer IB.

The cells handled in this configuration example have two priorities, that is, a high priority cell and a low priority cell, and the low priority class is divided into a plurality of classes. Usually C
A cell that transmits real-time information such as BR and VBR is a high-priority cell, and a cell that transmits non-real-time information such as ABR and UBR is a low-priority cell.

First, the cell switch with back pressure will be described.

The features of the car switch are the input buffer IB and the car management unit KM. The cell switch 400 with back pressure only needs to be able to output an input cell within a predetermined time, and its architecture is not limited to that shown below. For example, IEICE technical report SS
E93-6 "ATM switch with expandable buffer capacity:
An ATM switch shown by "XATOM" may be used.

The cell switch with back pressure 400 shown in FIG. 25 will be described as an example. First stage unit switch SE1, second stage unit switch SE2, output buffer O
B is connected, and SE1 and SE2 are connected in a two-stage delta network by a parallel link, and the cell output from SE2 is transferred to OB and output to the output port. Between SE1 and OB, it operates at k times speed. The value of k is set so that the cell switch is non-blocking. For example, if SE1 and SE2 have 8 inputs and 8 outputs, and 16 inputs and 16 outputs as a whole, k = 2 may be set.

The cell switch 400 with back pressure shown in FIG. 25 has a structure for handling two levels of priority, that is, a high priority cell and a low priority cell.

Focusing only on the exchange of low-priority cells, the basic configuration is the 1995 IEICE General Conference B-589.
This is almost the same as that shown in the "buffer capacity expansion method for ATM two-stage switch network". The low priority cell is SE1,
Exchanged and copied in SE2.

When the low-priority cell is congested with OB, the low-priority cell backpressure signal is used to suppress the cell output to the output port of the IB. This back pressure signal can basically prevent the OB and SE2 buffers from overflowing. However, there is a case where these buffers are likely to overflow due to the influence of the multicast cell, and in preparation for this, the overflow back pressure signal for low priority cells is output from OB to SE2, and the back pressure signal for low priority cells emergency is SE2.
To IB. Since the IB stores the low priority cells, they are not discarded in SE2 and OB.

The OB may output the overflow back pressure signal for low priority cells to SE2 as a low priority cell emergency back pressure signal instead of outputting it to SE2. In this case, SE2 does not need to output the low priority cell emergency back pressure signal. However, as described above, outputting the low-priority cell emergency backpressure signal from SE2 has an advantage that the buffer sharing effect in SE2 can be effectively utilized.

The high-priority cell has the same SE as the low-priority cell.
Exchanged and copied at 1, SE2. For high priority cells, there is no backpressure signal from the cell switch with backpressure to the IB. The OB uses the backpressure signal for the high-priority cell, which reflects the congestion of the high-priority cell, to send S
Control the cell output of E2. The IB does not store high priority cells. If there is no empty buffer in SE2, it may be discarded.

Next, the output buffer will be described.

FIG. 26 shows the output buffer O of the basket switch.
The structural example of B is shown.

The cell transferred from SE2 to OB has its priority identified by the identification unit 410 and is placed in a queue corresponding to each priority. The cell of each queue is selected by the selection unit 411 according to the priority and output to the output port. OB
When the queue length of the low priority cell exceeds a certain threshold, the low priority cell back pressure signal is used to stop the output of the low priority cell of the IB to the OB. When the queue length of the high-priority cell exceeds a certain threshold, the back-pressure signal for the high-priority cell is used to
Stop the output for that OB. In case the queue length of the low-priority cell continues to grow due to the influence of the multicast cell of the low-priority cell, the overflow back pressure signal for the low-priority cell is used to stop the output of the low-priority cell of SE2 to the OB.

Next, the unit switch will be described.

FIG. 27 shows an example of the structure of the first-stage unit switch SE1 used for the car switch. SE1 is a generally well-known switch LSI. The cell header input to the cell input from the input link is identified by the identification unit 415, a predetermined exchange process is performed, and the cell is output to the output link.
Since the entire switch operates at k times speed, the number of cells stored in the internal cell buffer does not increase. This is known in the 1994 Autumn Meeting of the Institute of Electronics, Information and Communication Engineers B-439 "Study on Switch Networks with Parallel Links".

FIG. 28 shows a structural example of the second-stage unit switch SE2 used for the car switch. In SE2, the internal queue is a queue for each priority for each output link. The output of the queue for each priority is selected by the selection unit 421. When a high-priority cell exists, the high-priority cell is output to the output link regardless of the presence or absence of the low-priority cell. However, when the high-priority cell back pressure signal input to the selection unit 421 indicates that the output of the high-priority cell is prohibited, the high-priority cell may not be output, and the low-priority cell may be output. . Output of the low-priority cells may be prohibited by the low-priority cell overflow backpressure signal.

SE2 shares the physical buffer area among a plurality of priorities and a plurality of output links, so that SE2
It is possible to efficiently use the buffer inside the E2. The buffer status management unit 422 monitors the queue length of each queue and the result of summing the queue lengths for all output links for each priority.

For example, the high priority cell queue has a threshold value for each queue, and when the threshold value is exceeded, the input cell of the queue is discarded. The low priority cell queue monitors the total of all queue lengths, and when the threshold value is exceeded, the low priority cell emergency back pressure signal notifies the IB to prohibit the input of the low priority cell.

SE1 may use the same unit switch as SE2.

The cell switch 400 with a backbrusher of FIG. 25 exchanges cells by the two-stage unit switches SE1 and SE2, but the internal path is defined only for each pair of input port and output port. Therefore, each unit switch does not need a complicated route selection algorithm when exchanging while copying cells by looking at the cell header. If the number of output ports is about 32 or less, it is possible to easily add the bitmap information of the output ports to the cell header. SE1 and SE2 exchange cells based on the bitmap information.

Next, the input buffer IB will be described.

FIG. 29 shows the input buffer I of the basket switch.
The structural example of B is shown.

The high priority cell input to the IB is preferentially output to SE1 for both unicast and multicast. Therefore, the cell delay fluctuation of the high priority cell is very small. Also, there is no buffer for high priority cells in the IB.

A feature of the present invention is a method of processing a low priority cell. Hereinafter, only low priority cells will be described.

In FIG. 29, the input buffer IB is mainly composed of a plurality of unicast cell management units 430 for each output port for temporarily storing the input unicast cell for each output port of the cell, and the input multicast cell. Has a multicast cell management unit 431 for temporarily accumulating data, and an output port selection scheduler 432 for selecting cells of these management units and outputting them from an input buffer.

Unicast cell management unit 43 for each output port
0 is a plurality of unicast cell management units 433 for each class that temporarily stores the input cell for each class of the cell.
And a class multiplexing FIFO 434 for multiplexing the cells output from the unicast cell management unit 433 for each class.

The multicast cell management unit 431 multiplexes a plurality of class-based multicast cell management units 435 for temporarily accumulating the input cells for each class of the cells and the cells output from the class-based multicast cell management unit 435. It has a class multiplexing FIFO 436 for converting into a class.

Unicast cell management unit 43 for each output port
0, cells output from the class multiplexing FIFOs 434 and 436 of the multicast cell management unit 431 are selected by the output port selection scheduler 432 and output from the input buffer IB.

The output port selection scheduler 432 selects a cell in consideration of the low-priority cell backpressure signal and the low-priority cell emergency backpressure signal from the outside.

Unicast cell management unit 433 for each class
Among the accumulated cells, a queue (cargo 440) called a basket that manages a set of cells permitted to be output by the car management unit KM, and a queue called a pre-cargo that manages other cells (previous It has a basket 441).

The cells that have entered the front basket 441 are managed in units called unit baskets. In FIG. 29, the vertical rows in the front basket 441 and the basket 440 represent unit baskets. The input cells are managed fairly among VCs (CGs) for each unit basket. The cell of the front car 441 is transferred to the car 440 in units of a unit car according to an instruction from the car management unit KM.

The cells of the basket 440 are transferred in units of cells according to an instruction from the basket management unit KM, and the class multiplexing FIFO is transferred.
It is multiplexed in O434.

Class-wise multicast cell management unit 435
The operation of will be described later.

By sharing the cell buffer among all the output ports of the IB and the queues of all classes, it is possible to effectively utilize a finite buffer amount.

In order for a cell arriving at the IB to be output from the IB, it is necessary for the IB to notify the KM that the cell has arrived, and for the KM to instruct output from the IB. Therefore, when there is a delay in the information transmission between the IB and the KM, the cell output from the IB is delayed by the delay time.
However, since the size of the delay time is considered to be about several cell cycles, it is considered that the effect on the traffic characteristics is small.

In order to give priority control to the unicast cell for each output port, the IB has a unicast cell management unit 433 for each class and a class multiplexing FIFO 43 for each output port.
There are four. Basically, the same method as the priority control described in the cell multiplexer of FIG. 1 is used.

Although FIG. 1 shows a cell multiplexer, a car switch is a cell switch and an IB is an input buffer of the cell switch. Therefore, a plurality of class multiplexing FIFOs exist in one IB corresponding to all output ports, and the cells are selected by the output port selection scheduler 434 and output to SE1.

The class-by-class cell storage unit 13 of the cell multiplexer of FIG. 1 corresponds to the class-by-class unicast cell management unit 433 of FIG. 29, and the class multiplexing FIFO 14 of the cell multiplexer of FIG. IB class multiplexing FI of FIG. 29
Corresponds to FO434.

Class management unit 12 of the cell multiplexer of FIG.
Corresponds to KM in FIG. Priority control can be performed by the basket management unit KM instructing transfer of cells from the unicast cell management unit 433 for each class to the class multiplexing FIFO 434.

Priority control of the multicast cell will be described later.

In order to perform fair queuing between VCs of unicast cells for each class, the unicast cell management unit 433 for each class has a front basket 441 and a basket 440. The same method as the inter-VC fair queuing described in the cell multiplexer of FIG. 6 is basically used.

FIG. 6 shows a cell multiplexer and no class, but IB is an input buffer of a cell switch and has a class. For each IB, the front car 441 and the car 440 exist corresponding to all output ports and all classes, and after the cells are multiplexed by the class multiplexing FIFO 434, the output port selection scheduler 43
It is selected by 2 and output to SE1.

The cell multiplexer 213 of FIG. 6 corresponds to the IB basket 440 of FIG. 29, and the cell set 214 to be output by the same time of the cell multiplexer of FIG. It corresponds to the unit basket of IB. The car management unit 12 of the cell multiplexer of FIG. 6 corresponds to the car management unit KM of FIG. Fair queuing between VCs can be performed by the car management unit KM instructing the transfer of the unit car from the front car 441 to the car 440 in FIG.

Inter-VC fair queuing of multicast cells will be described later.

In order to perform fair queuing of unicast cells between VCs in the IB, the unicast cell management unit 433 for each class has a front basket 441 and a basket 440. The same method as the method described in the example of the data structure by the pointer chain of the cell group FIFO 232a in FIG. 10 is basically used.

The cell group FIFO 232a of FIG.
Corresponds to the front basket 441 of the IB of FIG. 29, and the output waiting cell group FIFO 232b of FIG.
It is equivalent to the basket 440 of. The cell group of FIG. 10 corresponds to the unit basket of IB of FIG.

Next, referring to FIG. 30, the input buffer I
The queuing process of B will be described.

The cells are first accumulated in the front car 441 and then transferred to the car 440 in units of unit car. The cells of the basket 440 are output from the basket 440 in units of cells. For each of the triggers, the basket management department KM
Gives instructions.

In this configuration example, all VCs belong to a certain connection group (CG). By having the concept of a connection group, it becomes possible for a plurality of VCs to share one resource (bandwidth or cell buffer). For example, when only one VC is charged for communication between two remote users, it is possible to give the two users the flexibility to set a plurality of VCs. Alternatively, in a network in which fair bandwidth allocation is performed according to the number of VCs, it is possible to prevent two users from setting a large number of VCs and trying to obtain an unreasonably large bandwidth.

The VC table and the CG table are used to determine in which unit basket the cell is placed in the front basket 441.

The connection group identifier (eg CG5) can be known from the cell connection identifier (eg VC4) input using the VC table. CG
CG from connection group identifier using table
It is possible to know the value set for each. The values for each CG in this configuration example are Nx, Nc, Ptr, Qlen, Cnt1,
Cnt2, Cnt3 and BPIDt.

Nx, Nc, Ptr, and Qlen have been described in the data structure example by the pointer chain of the cell group FIFO in FIG. Nx is a weight of the CG, Nc is a work variable, Qlen is the number of accumulated cells of the CG, and Ptr is a pointer to the end of the unit basket in which the cells of the CG are accumulated.

On the other hand, Qlen, Cnt1, Cnt2, Cnt3,
BPIDt has been described in the cell buffer device having the back pressure consideration queue monitoring unit in FIGS. 15 and 16.

Qlen is the number of cells stored in the CG, Cnt1 is the number of cells to be discarded, and BPIDt is the backpressure identifier at the time of the last cell input. A variable Cnt2, which has the same function as Cnt1 in order to perform finer queue monitoring,
Cnt3 is present. The thresholds for queue length monitoring differ. Cnt2 is a CLP (Cell
Loss Priority (cell discard priority) The number of cells to discard for cells with low priority (CLP = 1) bit, Cnt3 is a value used to determine whether there is congestion in this queue length monitoring. The congestion information is used to determine, for example, whether to mark the EFCI in the cell header and whether to mark the congestion indicator bit of the RM cell.

It is possible to set not to perform fair queuing between VCs in a certain class. In that case, Nx of the CG to which the VC belongs may be set to a sufficiently large value.

The cell switch with backpressure shown in FIG. 25 has a cycle in which the low-priority cell backpressure signal is output enabled and output is repeatedly disabled due to the large delay time of cell transmission from IB to OB. Is relatively large. Therefore, when the queue length Qlen of each IB CG is observed, the oscillation is repeated as shown in FIG. 14 mainly in synchronization with the low-priority cell back pressure signal. As described above, the back pressure consideration queue length monitoring algorithm described in FIGS. 15 and 16 is suitable for monitoring the queue length that vibrates due to the back pressure signal.

Also regarding the total number of cells in the entire class of cells accumulated in the front car 441 and the car 440, the back pressure is taken into consideration and the input cell is discarded or the EF is detected by the queue length monitoring.
It is possible to mark some CIs and prevent some classes from monopolizing most of the IB buffer area.

FIG. 31 shows an example of an interface with the car management unit KM of the input buffer IB used for the car switch.

For each output port from KM,
The following information for each output port is input.

-Number of ABR input cells-Instruction class-Instruction transfer from previous basket to basket (transfer instruction T1 in FIG. 31) -Transfer instruction from car to class multiplexing FIFO (transfer instruction T2 in FIG. 31) The number of ABR input cells is transferred to the ABR processing unit 450.
By knowing the number of ABR input cells, the ABR processing unit 450 can monitor the traffic flowing into the output port of the IB and the pair. The information is used to rewrite the payload of the RM cell passing through the IB.

[0434] The class multiplexing FIFO 43 from the basket 440
4 is instructed by the KM to transfer a cell, the IB takes out one cell from the unicast basket 440 of the instructed class and transfers it to the class multiplexing FIFO 434. Further, when there is an instruction to transfer a unit car from the front car 441 to the car 440, the IB takes out one unit car from the front car 441 of the unicast of the instruction class and transfers it to the car 440, and also takes out one cell from the car 440 and performs the class multiplexing. Transfer to the FIFO 434.

By limiting the transfer instruction of the unit basket only when the transfer instruction of the cell of the class is given, the information amount of the transfer instruction can be reduced and the mounting can be implemented more easily.

The number of cells in the front car 441, the car 440, and the class multiplexing FIFO 434 in the IB changes depending on the IB.
When a cell is input to KM, when KM issues a transfer instruction, I
It is when the cell is output from B. Therefore, the cell number information is output to the KM accordingly. The information output from one IB to the KM is as follows.

Regarding input cells for each output port (in the case of unicast, only one output port is output):-Presence or absence of input cell and class For each output port, regarding transfer instruction class,-(transfer Previous number of cargo cells (after) (CE1 in FIG. 31) -Number of cargo cells (after transfer) (CE2 in FIG. 31) -Number of transfer cells to class multiplexing FIFO (CE in FIG. 31)
3) Only unicast for each output port-Number of class multiplexed FIFO cells (CE4 in FIG. 31) Explanation will be given using FIG. The input cell information is transmitted from the IB to the KM as the presence / absence of an input cell and the class. In addition, the number of previous cargocells for unicast and multicast is added, and the one selected in the transfer instruction class by the class selection unit L5 is transmitted as the number of previous cargocells. Further, the unicast and multicast cargo cell numbers are added, and the one selected in the instruction class in the class selection unit L6 becomes the cargo cell number and is transmitted. Then, the number of cells moved from the basket to the class multiplexing FIFO 434 by the transfer instruction is added by unicast and multicast,
The class selection unit L7 selects and transmits the selected class. The number of class multiplexed FIFO cells is transmitted to the KM only for unicast. The number of multicast class multiplexing FIFO cells is used as a back pressure signal for controlling the cell output from the class-based multicast cell management unit 435.

Multicast Class Multiplexing FIFO4
Since the output of 36 is controlled by back pressure signals from a plurality of output buffers OB, the output port of the cell switch may underflow even if the number of class multiplexing FIFO cells is not zero. In order to prevent the unicast cell from underflowing under the influence of this, the unicast class multiplexing FIF is used in this configuration example.
It is not added to the number of O cells.

Now, priority control of multicast cells and fair queuing between VCs will be described.

Consider the multicast VC from the viewpoint of throughput. In general, considering the state of the cell switch at a certain point in time, some of the plurality of output ports are congested and some are lightly loaded. That is, the throughput that the VC can use differs depending on the output port. Since the same throughput is simultaneously output from one input port to a plurality of output ports in the multicast VC, the throughput that the multicast VC can obtain is the throughput of the most congested output port among the output destinations. Is good. Therefore, when outputting a multicast cell from the IB, it is desirable to output at the throughput of the most congested output port.

The throughput per VC (CG) given to a class with a certain output port is calculated by the IB as the front basket 4.
It can be known from the frequency of the instruction to transfer the unit basket from 41 to the basket 440. The IB can know the throughput given to a certain class of a certain output port from the frequency of cell transfer instruction from the basket 440 to the class multiplexing FIFO 434. Furthermore, the IB can know the throughput given to a certain output port from the frequency of the back pressure signal for low priority cells. These transfer instructions and back pressure signals are given to each output port.

In order to output at the throughput of the most congested output port, the multicast cell may be transferred at the time when these signals indicate or permit all of the output ports of the cell. Instructions or permits to multiple output ports need not be simultaneous.

In IB, low priority multicast VC
It is desirable to manage each class and each output port pattern, but in general, the number of combinations is large, and the number of output ports may increase or decrease during communication. Therefore, such an implementation is not realistic. In the cage switch as shown in FIG. 25, all multicast connections are managed only for each class, and not for each output port pattern. A certain amount of HOL (Head Of Line) blocking will occur.

FIG. 32 is a diagram for explaining the multicast cell management unit 435 for each class. This management department
It holds and manages the output port table, the VC fair queue, the number of unit cells, the number of cells, and the number of output-permitted cells.

The class-specific unicast cell management unit 433 manages cells by the previous car and the car, whereas the class-based multicast cell management unit 435 manages cells only by the inter-VC fair queue 460 corresponding to the previous car. to manage. However, the class-based multicast cell management unit 435 of the present invention
Performs the same cell management as unicast by using the concept of the front cage and the cage in the calculation of management.

Multicast cell management unit 435 for each class
Inputs the following information for each output port.

Instruction for transferring unit car from previous car to instruction for cell transfer from car to class multiplexing FIFO Also output the following information for each output port.

-Number of previous basket cells-Number of basket cells-Number of transfer cells The inter-VC fair queue 460 is a FIFO of a unit basket.
The cell input to the inter-VC fair queue 460 is assigned to each VC (C
Regarding G), only a predetermined number can be entered in one unit basket. This configuration is the same as the configuration of the unicast front basket described in FIG. Class multiplexing FI
The back pressure signal is input from FO436,
Depending on the situation, the cell output from the inter-VC fair queue 460 is prohibited.

The output port table stores the number of previous car cells and a pointer to the head unit car for each output port. The number of front car cells is the total number of unit car cells, and the head unit car is a pointer to the head unit car of the calculated front car.

[0450] The unit basket number is the VC fair queue 460.
The data for each output port is stored corresponding to the unit basket of. Basically, the number of cells for each output port of the multicast cells stored in the corresponding unit basket is stored. For example, 5 cells are stored in the head unit basket of the VC fair queue 460 of FIG. Among them, there are 3 cells that output to port # 1 and port #N, and 2 cells that output to port # 1 and port # 2, so 5 for port # 1 and 5 for port # 2 of the unit cargo cell number. 2 and 3 are stored in port #N.

The number of basket cells is the number of basket cells in calculation. The number of output-permitted cells is the number of cells whose output is calculated.

When the unit car transfer is instructed to a certain output port, the unit car cell number of the head unit car of the output port is added to the car cell number, and the unit car cell number is set to zero. Further, 1 is subtracted from the number of cage cells of the output port and 1 is added to the number of output-permitted cells. Then, the pointer of the head unit car of the output port table is advanced to the next unit car of the inter-VC fair queue 460. The number of transfer cells at this time is one cell.

By advancing the pointer of the head unit car, the pointer moves away from the head unit car of the inter-VC fair queue 460. An upper limit is set for this distance, and at a certain distance, the unit basket transfer instruction is ignored and the pointer is controlled so as not to advance. This has the effect of not increasing the difference between the time when the transfer of the unit basket is instructed and the time when the cell is actually output.

When a cell transfer is instructed from a KM to an output port, 1 from the number of cage cells of the output port.
Is subtracted and 1 is added to the number of output-permitted cells. The number of transfer cells at this time is one cell.

When the back pressure signal from the class multiplexing FIFO 436 permits the output, the cell can be output from the inter-VC fair queue 460. that time,
The number of output-permitted cells is subtracted by 1 for all output ports of the cell. If there is an output port with the number of output-permitted cells of zero, it cannot be subtracted, so that cell cannot be output yet.

The number of output-permitted cells is increased by the unit basket transfer instruction and the cell transfer instruction. If the number of output-permitted cells of a certain output port exceeds a certain value, the number of previous cage cells and the number of cage cells output from the class-based multicast cell management unit 435 is set to zero for that output port, and a unit cage transfer instruction is issued. Ignore cell transfer instructions. This has the effect of ignoring transfer instructions above the actual cell transfer throughput.

Next, the operation of the class-specific multicast cell management section will be described with reference to FIGS.

FIG. 33 shows the operation when the KM instructs the output port # 1 to transfer the unit basket from the state shown in FIG. The number of unit cargo cells of the first unit cargo of port # 1 is added to the number of cargo cells to make the unit cargo cell number zero.
Further, 1 is subtracted from the number of cage cells of port # 1 and 1 is added to the number of output-permitted cells. The number of cells transferred to the KM is 1 cell for the output port # 1.

The pointer of the head unit car of the output port table is advanced to the next unit car of the inter-VC fair queue 460.

Further, FIG. 34 shows the operation when the cell transfer is instructed to the output port # 1 by the KM. Subtract 1 from the number of cage cells of port # 1 and add 1 to the number of output-permitted cells. The number of cells transferred to the KM is 1 cell for the output port # 1.

The output ports of the head cell of the inter-VC fair queue 460 of FIG. 34 are # 1 and #N. The number of output permitted cells is not zero for output port # 1 (= 2)
However, since the output port #N is zero, the cell cannot be output yet.

FIG. 35 shows the operation when a cell arrives.
The output ports of the arriving cells are # 1 and #N. It is also assumed that this cell is a VC cell that has not been stored in the inter-VC fair queue 460 so far. In this case, the cell is VC
It is input to the first unit basket of the fair fair queue 460.

When a cell is input, the unit cage cell numbers of all output ports of the cell are incremented by one. The unit basket to be added is determined for each output port. Basically, 1 is added to the unit basket where the cell is input, but if the head unit basket of the output port table is after the unit basket where the cell is input, the unit basket cell pointed to by the head unit basket of the output port table Add 1 to the number. Therefore, in FIG. 35, the output port #
As for 1, 1 is added to the number of unit car cells of the second unit car pointed to by the head unit car. For the output port #N, 1 is added to the number of unit car cells of the first unit car which is the unit car into which the cell is input.

Furthermore, FIG. 36 shows the operation when a cell arrives again. The output ports of the newly arrived cells are # 1 and # 2. Also, this cell is currently the fair queue between VCs 46
It is assumed that the cell is a cell of VC in which the cell is stored in 0. FIG.
In the case of 6, a new unit basket is newly provided at the end of the inter-VC fair queue 460, and the cell is input to the unit basket.

Further, FIG. 37 shows the operation when the KM instructs the output port #N to transfer the unit basket. The unit car cell number of the head unit car of port #N is added to the car cell number to make the unit car cell number zero. Further, 1 is subtracted from the number of cage cells of port #N and 1 is added to the number of output-permitted cells. The number of cells transferred to KM is 1 for output port #N. The pointer of the head unit car of the output port table is advanced to the next unit car of the VC fair queue 460.

The output ports of the first cell of the inter-VC fair queue 460 are # 1 and #N, and the number of output-permitted cells of # 1 and #N is 1 or more (specifically, 2 and 1). Therefore, if the class multiplexing FIFO 436 permits, the cell can be output.

FIG. 38 shows a state in which a cell is output. The number of output-permitted cells corresponding to the output port of the output cell is subtracted by one.

FIG. 39 shows a state in which the unit basket and the basket transfer are successively instructed as described above, and a total of 6 cells are output. The unit car at the head of the inter-VC fair queue 460 becomes empty at this point, and the unit car and the number of unit car cells disappear. Inevitably, the head unit basket of the output port table does not point to this lost unit basket. Next, referring to FIG. 40, the output port selection scheduler 4
32 will be described.

The cell selection unit 470 selects a unicast output waiting cell and a multicast output waiting cell for each output port, which are input to the output port selection scheduler 432, and output from the output port selection scheduler 432. A cell that is a candidate for selection by the cell selection unit 470 is a permitted cell among output waiting cells.

The output of the unicast cell is permitted by the unicast cell output permission signal output from the unicast cell output permission signal generating section 471.

Unicast cell output permission signal generation section 47
A back pressure signal and an emergency back pressure signal are input to 1.

The back pressure signal is output port by output port. The back pressure signal corresponding to the emergency back pressure signal is predetermined. In the case of FIG. 25,
The emergency back pressure signal is output from SE2, and the output buffer O connected to the output link of SE2.
It corresponds to the back pressure signal from B.

When the back pressure signal indicates that output is prohibited, the unicast cell output enable signal does not allow output of the cell of the output port. When the emergency back pressure signal indicates that the output is prohibited, it is considered that all the back pressure signals corresponding to the emergency back pressure signal indicate that the output is prohibited, and the output is not permitted.

The output of the multicast cell is permitted by the multicast cell output permission signal output from the multicast cell output permission signal generation unit 472.

Multicast cell output permission signal generation unit 4
A unicast cell output permission signal and output port information of the head cell of the class multiplexing FIFO 436 for multicast cells are input to 72.

Multicast cell output permission signal generation unit 4
72 monitors if all output ports of the multicast cell have been granted (not necessarily at the same time). If any of the output ports is not permitted, the output of the multicast cell output permission signal is prohibited. When all the output ports of the multicast cell are permitted, the output of the multicast cell is permitted during the time when the unicast cell output permission signal of the last permitted output port indicates that the output is possible. When the multicast cell is not selected by the cell selection unit 470 within that time, and when the multicast cell is selected and output by the cell selection unit 470 and the output port information of a new multicast cell arrives, it is output again from the beginning. Monitor if all ports are allowed.

The cell selection unit 470 fairly selects the output waiting cells for which the output is permitted in this way.

As described above, the multicast cell is output even if all the back pressure signals of the output port do not permit the output at the same time. That is, at the time of outputting the multicast cell, it is possible that some of the backpressure signals at the output ports of the cell indicate output inhibition. Even in such a situation, the low-priority cell emergency back pressure signal effectively acts so that the SE2 buffer does not overflow.

In the above configuration, when the low-priority cell emergency backpressure signal indicates that output is prohibited, output of both the unicast cell and the multicast cell to the corresponding output port is prohibited. Other configurations include
Even if a certain output port is once permitted, the multicast cell output permission signal generation unit 472 may cancel the permission when the low-priority cell emergency backpressure signal instructs the output inhibition. Further, simply, when the low-priority emergency back pressure signal indicates that the output is prohibited, the configuration may be such that the output of all the low-priority multicast cells is prohibited.

The input buffer IB of the present invention performs the back pressure consideration queue monitoring described with reference to FIG. This monitoring updates the back pressure identifier with the back pressure signal and operates based on the value. The back pressure identifier for each output port of the unicast cell is updated by the unicast cell output permission signal of the output port selection scheduler 432, and the back pressure identifier of the multicast cell is output port selection scheduler 432.
It is updated by the multicast cell output permission signal of.

Next, with reference to FIG. 41, the car management unit KM used in the car switch shown in FIG. 25 will be described.

FIG. 41 shows an example of the structure of the car management unit KM.

KM is, for each output port, the total number of ABR input cells.

The total number of previous cargo cells, the total number of cargo cells, and the number of transfer cells for each class.

Total number of class multiplexed FIFO cells.

Information such as the above is held, and a transfer instruction history management unit 480 and a class selection scheduler 481 are provided for each output port.

The total number of ABR input cells is the total number of input cells of all IBs to each output port for the ABR class. It is integrated within a fixed time, and is transmitted to the IB paired with the output port for each cycle. When the total number of ABR input cells exceeds a certain threshold value before the predetermined fixed time is reached, the IB may be notified of that fact by an interrupt.

For the total number of cells in the front car, the total number of cells input in the front car is added based on the presence / absence of cells input to the IB and the class information. In addition, the number of previous cage cells of the class that the KM has instructed to transfer is updated with the total for all IBs. The class is stored in the transfer instruction history management unit 480 of KM.

The total number of cargo cells is updated with the total number of cargo cells of the class to which the KM has instructed the transfer for all IBs. The class for which transfer is instructed is stored in the transfer instruction history management unit 480 of KM.

As the number of transfer cells, the number of transfer cells to the class multiplexing FIFO of the class for which the KM has instructed transfer is set for all IBs.
Will be updated with the total. The class for which transfer is instructed is stored in the transfer instruction history management unit 480 of KM.

The total number of class multiplexed FIFO cells is updated with the total number of class multiplexed FIFO cells for all IBs.

The class selection scheduler 381 gives a transfer instruction to the IB based on information such as the total number of previous car cells, the total number of car cells, the total number of transfer cells, and the total number of class multiplexing FIFO cells. A history of transfer instructions in the past is stored in the transfer instruction history management unit 480, and the class selection scheduler 481
Uses the history to correct the cell number information.

42, 43, and 44, the basket management unit K
An example of a scheduling algorithm executed by the M class selection scheduler 481 is shown. This algorithm limits the maximum bandwidth of the class and guarantees the minimum bandwidth, while performing priority control by priority.

As a global variable, there is a variable now indicating the current time. For each class i, the minimum bandwidth 1 /
Di, output mandatory time Tdi, parameter Dxi giving the upper limit of Tdi, maximum bandwidth 1 / Ui, output prohibition time T
A parameter Uxi that gives the lower limit of ui and Tui is set (step S100 in FIG. 42).

For each class i, the output is to be performed when the current time now is Tdi < now, and the output is prohibited to be output when the current time is now <Tui. Further, the case where the output is performed according to the priority order is when the current time now is Tui < now <Tdi. The upper limit of Tdi is set, and Tdi < n
ow + Dxi. The lower limit of Tui is set, and now-Uxi < Tui. However Ux
i > 0 and Dxi > Di.

Initially, now is set to zero, Tdi is set to Di-Ui, and Tui is set to no for each class i.
w, that is, zero (step S101 in FIG. 42).

This algorithm performs the following processing for each cell cycle.

First, the processing when the class becomes active is performed. Specifically, when a cell arrives in class i where there is no cell, Tdi is updated to the larger of now and Tdi, and Tui is updated to the larger of now and Tui (step S102 in FIG. 43).

Next, it is determined whether or not the cell can be transferred (step S103 in FIG. 43), and if so, transfer class selection and transfer class instruction are performed (FIG. 43).
Step S104).

Transfer class selection is the following processing.

In each class i in which there is a cell to be transferred, 1. If there is a class in which Tdi < now, the class having the highest now-Tdi is selected from the classes (if the values are the same, the priority is determined).

2. Without tdi <class has become now selects the highest class of priority among the classes that satisfy Tui <now <Tdi.

If the selected class is j, the flow advances to step S105 in FIG. 44 to perform the following transfer class instruction processing.

1. Instruct transfer of class j.

2. Tuj to max (Tuj, now-U
xj) and updated.

3. Updated Tdj to Tdj + Dj.

[0507] 4. Updated Tuj to Tuj + Uj.

5. Tdj is min (Tdj, now + D
xj) and updated.

Finally, after the transfer cell flow rate monitor process is performed (step S106 in FIG. 44), now is incremented (step S107 in FIG. 44) and the process for each cell cycle is ended.

In the transfer cell flow rate monitor process of step S106 of FIG. 44, the following process is performed for class j when the number of transfer cells of class j is xj.

1. Tuj to max (Tuj, now-U
xj) and updated.

2. Update Tdj to Tdj + (xj -1) Dj.

3. Update Tuj to Tuj + (xj -1) Uj.

[0514] Tdj is min (Tdj, now + D
xj) and updated.

[0515] In step S103 of FIG. 43, it is determined whether the cell transfer instruction may be given or not.
It is determined whether the total number of cells is below a certain threshold. The certain threshold is usually "1". The total number of class multiplexing FIFO cells is a value corrected by the transfer instruction history of the transfer instruction history management unit 480.

The determination in step S104 of FIG. 43 as to whether or not there is a cell to be transferred to the class is made by determining that either one of the total number of previous cage cells or the total number of cage cells is not zero. The total number of previous cargo cells and the total number of cargo cells are values corrected by the transfer instruction history of the transfer instruction history management unit 480.

[0517] The transfer instruction is sent from the basket 440 to the class multiplexing F
A cell transfer instruction to the IFO 434 (transfer instruction T in FIG. 31)
2). At that time, whether or not to instruct the transfer of the unit car from the previous car to the car at the same time is determined by judging whether the total number of previous car cells is not zero and whether the total number of car cells is less than a certain threshold value. . A certain threshold is usually 1. The total number of previous cargo cells and the total number of cargo cells are values corrected by the transfer instruction history of the transfer instruction history management unit 480.

The present algorithm can bring the minimum guaranteed bandwidth close to zero by setting Di to a large number. For example, if Di of all classes is set to a large number, all classes can be priority-controlled with full priority.

Also, by using one of the classes as an IC (Idle Cell) class having the lowest priority but the minimum guaranteed bandwidth, the usage rate of the output port can be controlled. The IB inserts an idle cell into the class multiplexing FIFO when there is an IC class transfer instruction (only one IB is required).

Idle cells, like any other cell, are exchanged towards the output port of the cell switch, where the Unass
Replaced by ignition Cell. KM is IC
The class should always perform scheduling considering that there is a cell to be transferred.

By the way, in the algorithms shown in FIGS. 42 to 44, in order to simplify the explanation, variables now, Td
Variables indicating time, such as i and Tui, have no upper limit in representable value. At the time of implementation, these variables are represented by registers with a finite bit length, so that the same time appears in cycles after a long time. In order to make the algorithm operate normally, the following may be done. Let these cycles be Max. Max needs to be large enough.

At this time, calculations such as x: = f (x) are replaced with x: = f (x) mod Max. In other words, take modulo with Max. Also, y
The comparison operation of < z is (z < y-Max / 2) or ((y < z) and (z < y
+ Max / 2)) and compare.

For example, the calculation now: = now + 1 is replaced with now: = (now + 1) mod Max. The comparison operation of Tdi < now is (now < Tdi −Max / 2) or ((Tdi < now) and (now < Td
i + Max / 2)) and compare.

It is necessary to monitor the time variable periodically and adjust it so that it is not too far from Max / 2 or more from now if necessary. However, by increasing Max, the monitoring cycle is extended. It is possible and easy to implement.

Furthermore, the following is effective as another class selection scheduling.

As described above, each CG (each VC)
The cell buffer device that has performed the fair queuing between VCs according to the weight set in step S1 writes the weight to the CG table (FIG. 30) of the input buffer IB or Nx of the VC table.

Here, by using the class selection scheduling together, the V
It will be described that the weight for each C can be multiplied by a coefficient.

There are classes A and B, and a weight of a certain VC set in the class A is Nxa, and a weight of a certain VC set in the class B is Nxb. At this time, when output waiting cells exist in both classes, the number of transfer instructions of the unit car is scheduled by the class selection scheduling so that the ratio of Ra to Rb in class X and class Y becomes Nxa. × Ra
, Nxb × Rb. The same applies to cases of three or more classes. To get the desired ratio
As an algorithm for scheduling, for example, S
CFQ (Self-Clocked Fair Que)
ueing) and the like are known.

A concrete example will be described. For example, seven VCs from VC1 to VC7 are weighted 1.24, 3.
72, 2.18, 934, 562, 1370, 4360
I want to set to. Set VC1,2 in class A,
Let Nx be 1.24 and 3.72, respectively. Set VC3 in class B and set Nx to 2.18. Class C to V
C4 and 5 are set, and Nx is 9.34 and 5.62, respectively.
And Set VC6 and 7 in class D and set Nx to 1.37 and 4.36, respectively. If the class selection scheduling is performed so that the number of transfer instructions of the unit basket becomes a ratio of class A: class B: class C: class D = 1: 1: 100: 1000 among the classes in which output waiting cells exist,
Objective weight 1.24: 3.72: 2.18: 934: 5
The cells are multiplexed to the output ports at 62: 1370: 4360. This method has the effect of avoiding the phenomenon that the cell delay fluctuation of fair queuing between VCs increases if a large value is set as the value of Nx.

In the class selection scheduling algorithm as shown in FIGS. 42 to 44, the transfer cell flow rate of each class is monitored. By utilizing this, it is possible to perform hierarchical class selection scheduling.

When there is a class group Ga consisting of classes A1, A2, A3, ... And another class group Gb consisting of other classes B1, B2, B3 ,. Class selection scheduling is performed by setting the flow rate ratio to Ra to Rb. The same applies when the number of classes is three or more. Class selection scheduling within each class group and selection scheduling between class groups are independent.

As a result, the surplus bandwidth between certain class groups is used only by the classes within that class group, and it can be prevented that another class group can be used. Another class group can use this surplus bandwidth only when there is no cell waiting for output of a certain class group.
Such hierarchical class selection scheduling. For example, applications such as assigning a class group to each company can be considered.

5.2 Method for Correcting Number of Cells of Cell Switch for Priority Control and Fair Queuing between VCs Next, a cell switch (car switch) for performing priority control and fair queuing between VCs (FIG. 25, FIG. 29, FIG. 29) Three
FIG. 4 shows a method of correcting the number of cells in the car management unit KM of 1).
This will be described with reference to FIG.

The principle of modification is to realize improvement of the priority control performance and output port throughput by modifying the number of cells in the same manner in the case of the cage switch described with reference to FIGS. 19 and 20. You can

As an application example of the cell number correcting method of the present invention, it is applied to the car switch shown in FIG. In the car switch, when the management unit 301 instructs the transfer to the front car (Bpi) of class i, the cell of the front car of the class is set to the car (B
ki) and part of it is class multiplexed F
It is transferred to IFO (Bm). Management unit 301 is class i
If you instruct the class multiplexing FIFO to transfer from the
The basket cells of that class are transferred to the class multiplexing FIFO.

As shown in FIG. 45, cell number information and delay time of each cell buffer are determined.

Hpi is the number of HOLs transferred from the previous car to the car by the transfer instruction Ipi, and Hpmi is HO transferred from the previous car to the class multiplexing FIFO by the transfer instruction Ipi.
It is the number of L cells.

As an example, consider the case where the values of the respective delay times are the same. That is, DOp = DIk = DO
Let k = DIm = Dipm = D and DTpm = DTkm. Also, p = [-D, 0). At this time, class i
And the modified number of cells (N'pi, N'k)
i), and the modified cell number (N'm) of the class multiplexing FIFO can be calculated as follows.

[0539]

(Equation 7)

5.3 Continuation of Description of Cell Switch According to Tenth Embodiment FIG. 46 shows an example of connection between the input buffer IB of the car switch and the car management unit KM.

Here, for example, the number of classes is 62 classes, and the cell switch size is 16 inputs and 16 outputs.

The class numbers are {0, 1, 2, ..., 60,
61, UC, IC} and 6 bits.

Class UC is an unassigned cell (Unass
igned Cell), IC is an idle cell (Idl
e Cell) and how to use them is described below.

The number of previous cage cells, the number of cage cells, and the number of class multiplexing FIFO cells are {0, 1, 2, ..., 13, 14, 1, 1.
5 or more} and 4 bits.

Transfer information from the input buffer IB to the car management unit KM is shown below.

(1) Input cell Regarding input cells for each output port (only one output port is output in the case of unicast): Presence / absence of input cell and class ... 6 bits (when there is no input cell) (3) Transfer instruction class (3) Transfer instruction class Regarding transfer instruction class for each output port: -Number of previous cage cells after transfer ... 4 bits-Number of cage cells after transfer ... 4 bits-Transfer cells to class multiplexing FIFO Number ... 2 bits (2 cells of unicast and multicast are transferred at the maximum) (4) Class multiplexing FIFO Only unicast for each output port-Number of class multiplexing FIFO cells ... 4 bits The information about the output port is 20 bits.

All the input buffers I from the car management unit KM
The transfer information broadcast to B is shown below.

(2) For each output port: -Instruction to transfer a unit basket from the previous basket to the basket (for the following classes) ... 1 bit-Instruction to transfer a cell from the basket to the class multiplexing FIFO,
Instruction class: 6 bits (UC class is specified when transfer instruction is not given. If IC class is specified, IB transfers (inserts) idle cells. Idle cells are sent to output port like cells of other classes. It is a cell for throughput adjustment that is exchange-transferred and is replaced with an Unassigned Cell at the time of output from the cell switch.) In total, information on one output port is 7 bits.

The KM transmits the following signal to the corresponding IB for each output port for ABR traffic control.

(5) Number of ABR input cells destined for each output port among all IB input cells: 5 bits (16 inputs 16
In case of output cell switch) Information about one output port is 5 bits.

[0551] Fig. 46 shows two LSs having a basket management unit KM.
3 shows an example of the configuration realized by I. Two L
One of the SIs manages the output ports # 1 to # 8, and the other manages the output ports # 9 to # 16.

Transfer information from IB to KM ((1) above)
Since (3) and (4) have 20 bits per output port, there are 160 bits for 8 ports. If parallel transmission is performed using two pairs of high-speed differential transmission, a transmission rate of 80 bits in one cell cycle will suffice.

Since the broadcast information from KM to IB ((2) above) has 7 bits per output port,
It is 56 bits for 8 ports. If eight parallel transmissions are performed using a normal transmission driver, seven cells can be transmitted in one cell cycle.
A bit transmission rate is sufficient.

Information for ABR traffic control from KM to IB ((5) above) is 5 per output port.
Is a bit.

Considering a cell switch whose cell transmission rate is 622 Mbps, these transmission rates can be sufficiently realized by the present technology.

The IB can reduce the circuit scale for adding the number of cells by transmitting the cell number information from the LSB (least significant digit) to the KM. This is because the adder circuit can add the cell number information transmitted from all IBs in order from the lower digit (for each output port and each class).
More specifically, the adder circuit can calculate the sum of the digit of the input digit and the carry from the lower digit calculated up to that point, and obtain the value of that digit of the addition result. In addition it holds the carry for the calculation of the next digit.

There is the number of class multiplexing FIFO cells in the signal from IB to KM. When the cell switch with back pressure can output the number of accumulated cells for each output port (the number of cells of the output buffer OB in FIG. 25), the KM determines the number of accumulated cells for each output port instead of the number of class multiplexing FIFO cells. May be used.

This has the same effect as the cell multiplexer shown in FIG. 2 for performing priority control between classes and the cell multiplexer shown in FIG. 7 for performing fair queuing between VCs.

FIG. 47 shows a route of information for realizing the ABR service.

FIG. 47 shows, in particular, a portion where an ABR class cell input from port # 1 to port #N is exchange-multiplexed with port #i by cell switch 400 with back pressure. Actually, all the output ports have the same configuration as #i in this figure.

[0561] The ABR service is a service class in which, if there is a usable band at the output port of the cell switch, the band is evenly distributed and used by the ABR class VCs. The RM cell transmitted from the receiving terminal to the transmitting terminal is used for traffic control.

The cell switch 400 knows the bandwidth available to the ABR at the output port #i, and knows the ratio (or difference) between it and the input traffic of the current ABR to control traffic to the transmitting terminal. Can be done. The current ABR traffic can be known from the total of the number of input cells destined for port #i shown in FIG. The input band is calculated from the number of input cells, and if this exceeds the available band of the ABR at the output port, it is overloaded, so the RM input to port #i
An instruction to reduce the VC bandwidth may be written in the cell. On the contrary, if the input band obtained from the number of input cells to the port #i is lower than the band that can be used by the ABR at the output port, the load is low. Write the instruction to increase the bandwidth.
By knowing the ratio or difference between the input band and the output band, it is possible to know the degree of overload or low load, and it is possible to perform fine control.

Although the probability of congestion is reduced by this processing, when the queue length is further monitored in the IB and congestion is detected, EFCI is marked or the RM cell is rewritten to ensure more secure traffic. It is possible to control. Especially for multicast,
Even if the input band is smaller than the output band, there is a possibility of overload, and in that case, traffic control by queue length monitoring becomes important.

As described above, since the car switch according to the tenth embodiment performs fair queuing between VCs, it is possible to realize fair band distribution among VCs even in traffic control by monitoring the queue length. .

[0565]

As described above, according to the packet transfer device (first and second embodiments (claims 1, 2, 3, 4)) for performing priority control between classes according to the present invention, The control unit (class management unit) grasps the status of the entire plurality of input buffers (at least the status of the whole is sufficient, but it may be known for each input buffer).
Because the instruction is issued, the priority relationship between classes does not collapse due to the difference in the accumulation status of each class of each input buffer, and even if the number of input ports, that is, the number of input buffers, increases The priority control of can be realized.

Also, V is spread over a plurality of input buffers.
In order to perform fair queuing between Cs (flows), for example, the control means grasps the input port numbers and VC numbers, packet arrival states, output states, etc. of all VCs (flows) of all input buffers. If the output order of the packets is controlled by the above method, the device configuration becomes complicated and it is difficult to improve the throughput. Therefore, according to the packet transfer device of the present invention (third, fourth and fifth embodiments (claims 5 and 6)), a packet to be output within a certain phase (its time length is indefinite) Introducing the concept of a set (car), each input buffer is responsible for selecting packets to be included in this packet set and outputting only the packets in this packet set (other packets are not allowed to be output). However, since the basket management unit shares the processing for instructing the timing of inserting a new packet in the packet set, for example, fair cell queuing between VCs (flows) can be easily realized in the cell switch of the input buffer system.

Further, the packet transfer device of the present invention (sixth,
According to the seventh embodiment (claims 7 and 8), when the control means (buffer pointer management unit) inputs a packet, it is distributed to a plurality of sets, and when the packet is output. Since it is sufficient to output the pointers belonging to one set, for example, even if the number of VCs to be set increases, it is possible to realize high-speed selection of packets to be output for fair queuing between VCs (flows).

Further, according to the packet transfer device (8th embodiment (claim 9)) which considers the back pressure signal of the present invention, the queue length monitoring result is not easily influenced by the external condition and the stable queue is obtained. The length is easy to monitor.

Further, according to the packet transfer device for correcting the cell number information in consideration of the delay of the present invention (the ninth embodiment (claims 10, 11, 12, 13)), when determining the transfer instruction. Since the history of transfer instructions is used to correct the number of cells transmitted from the buffer to the number of cells at the time when the transfer instruction acts on the buffer, there is little deterioration in performance due to delay time.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a cell multiplexer that performs priority control between classes according to a first embodiment of the present invention.

FIG. 2 is a diagram showing another example of the configuration of a cell multiplexing device that performs priority control between classes according to the second embodiment of the present invention.

FIG. 3 is a diagram showing another configuration example of the output buffer.

FIG. 4 is a diagram showing still another configuration example of the output buffer.

FIG. 5 is a per-VC FIFO according to a third embodiment of the present invention.
The figure which showed the structural example of the output buffer type cell multiplexer provided with.

FIG. 6 is a diagram showing an example of the configuration of a cell multiplexer that performs inter-VC fair queuing according to a fourth embodiment of the present invention.

FIG. 7 is a diagram showing a configuration example of a cell multiplexing device that performs fair queuing between VCs according to a fifth embodiment of the present invention.

FIG. 8 is a cell group F according to a sixth embodiment of the present invention.
The figure which showed the structural example of the cell buffer apparatus which uses IFO.

FIG. 9 is a cell group F according to a seventh embodiment of the present invention.
The figure which showed the structural example of the cell buffer apparatus which uses IFO.

FIG. 10 is a cell group FIFO according to the sixth embodiment.
For explaining a data structure example by the pointer chain of FIG.

FIG. 11 is a cell group FIFO according to the sixth embodiment.
Is a diagram for explaining an example of the data structure by the pointer chain of FIG.

FIG. 12 is a cell group FIFO according to the seventh embodiment.
For explaining a data structure example by the pointer chain of FIG.

FIG. 13 is a cell group FIFO according to the seventh embodiment.
Is a diagram for explaining an example of the data structure by the pointer chain of FIG.

FIG. 14 is a diagram illustrating inter-flow fair queuing using packet groups.

FIG. 15 is a diagram for explaining the operation of the packet buffer device using inter-flow fair queuing using packet groups.

FIG. 16 is a diagram illustrating back pressure consideration queue monitoring according to an eighth embodiment of the present invention.

FIG. 17 is a diagram showing a configuration example of a cell buffer device having a back pressure consideration queue monitoring unit according to an eighth embodiment.

FIG. 18 is a flowchart showing a back pressure consideration queue monitoring algorithm according to an eighth embodiment.

FIG. 19 is a diagram showing a configuration example of a cell buffer device considering delay according to a ninth embodiment of the present invention.

FIG. 20 is a diagram for explaining the basic principle of a correction method of cell number information in consideration of delay.

FIG. 21 is a diagram for explaining another basic principle of the cell number correction method.

22 is a view for explaining a basic function f () used in the cell number correction method of FIG.

FIG. 23 is a view for explaining a basic function g () used in the cell number correction method of FIG. 21.

24 is a diagram for explaining a basic function Sc () used in the cell number correction method of FIG.

FIG. 25 is a diagram showing an example of the overall configuration of a car switch according to a tenth embodiment of the invention.

FIG. 26 is a diagram showing a configuration example of the output buffer of FIG. 25.

FIG. 27 is a diagram showing a configuration example of a first-stage unit switch shown in FIG. 25.

FIG. 28 is a diagram showing a configuration example of a second-stage unit switch shown in FIG. 25.

FIG. 29 is a diagram showing a configuration example of the input buffer of FIG. 25.

FIG. 30 is a diagram for explaining queuing processing of an input buffer.

FIG. 31 is a diagram showing an interface of the input buffer of FIG. 25 with a car management unit.

FIG. 32 is a diagram for explaining the operation of the class-based multicast cell management unit of FIG. 29;

FIG. 33 is a diagram for explaining the operation of the class-based multicast cell management unit of FIG. 29;

FIG. 34 is a diagram for explaining the operation of the class-based multicast cell management unit of FIG. 29;

FIG. 35 is a diagram for explaining the operation of the class-based multicast cell management unit of FIG. 29;

FIG. 36 is a diagram for explaining the operation of the class-based multicast cell management unit of FIG. 29;

FIG. 37 is a diagram for explaining the operation of the class-based multicast cell management unit of FIG. 29;

FIG. 38 is a diagram for explaining the operation of the class-based multicast cell management unit of FIG. 29;

FIG. 39 is a diagram for explaining the operation of the class-based multicast cell management unit of FIG. 29;

FIG. 40 is a diagram showing a configuration example of the output port selection scheduler of FIG. 29.

FIG. 41 is a diagram showing a configuration example of the basket management unit in FIG. 25.

42 is a flowchart showing a specific example of a scheduling algorithm executed by the class selection scheduler of the car management unit of FIG. 41 to limit the maximum bandwidth and guarantee the minimum bandwidth.

43 is a flowchart showing a specific example of a scheduling algorithm executed by the class selection scheduler of the car management unit of FIG. 41 to limit the maximum bandwidth and guarantee the minimum bandwidth.

FIG. 44 is a flowchart showing a specific example of a scheduling algorithm executed by the class selection scheduler of the car management unit of FIG. 41 to limit the maximum bandwidth and guarantee the minimum bandwidth.

FIG. 45 is a diagram for explaining the operation of the cage switch that is an application example of the method for correcting cell number information.

FIG. 46 is a diagram showing a specific example of the connection between the input buffer of FIG. 25 and the basket management unit.

FIG. 47 is a diagram showing a specific example of an information path for an ABR service.

FIG. 48 is a diagram for explaining unfair bandwidth allocation in the conventional UBR service.

FIG. 49 is a diagram for explaining the configuration of a conventional cell multiplexing apparatus that performs priority control between classes.

FIG. 50 is a diagram for explaining the configuration of a conventional cell multiplexer having an input buffer.

FIG. 51 is a diagram for explaining the configuration of a conventional cell buffer device that requires a VC table search.

52 is a diagram for explaining changes in the queue length of the input buffer in the cell multiplexer having the conventional input buffer as shown in FIG. 50. FIG.

FIG. 53 is a diagram for explaining the configuration of a conventional cell multiplexing device that performs priority control.

[Explanation of symbols]

10 ... Input buffer, 11 ... Output buffer, 12 ... Class management unit, 212, 222 ... Basket management unit, 230, 24
0 ... buffer pointer management unit, 282 ... queue monitoring unit,
302 ... Transfer instruction history, KM ... Basket management unit, 400 ... Cell switch with back pressure.

Claims (14)

[Claims] 1. A plurality of input buffers for temporarily storing input packets, control means for controlling these input buffers, and at least one output port for transferring packets output from each of the input buffers. In the packet transfer device, each of the input buffers stores a packet for each class for temporarily storing the input packet for each class, and outputs a packet of a class instructed by the control unit from the storage unit. Output means for outputting to the port, the control means grasps the accumulation status in the entire plurality of input buffers of the accumulation means for each class, and based on this accumulation status, determines the class to which the packet should be output. Packet transfer characterized by determining and transmitting an instruction including designation of the determined class to the plurality of input buffers Location. 2. The output port comprises an output buffer for temporarily accumulating the packet output from the input buffer, and the output means stores the packet according to an accumulation state of the packet inside the output buffer. The packet transfer device according to claim 1, wherein the packet transfer device outputs the packet to an output port. 3. The output means comprises a multiplexing means for multiplexing the packets output from the accumulating means and outputting the multiplexed packets to the output port, wherein the control means comprises the accumulating status. In addition to the above, in addition to grasping the multiplexing status in all of the plurality of input buffers of the multiplexing means, the class to output the packet is determined based on the storage status and the multiplexing status. The packet transfer device described. 4. The input buffer selects a packet to be output from the accumulating unit so that transfer of packets is fair among virtual connections to which each packet belongs in the same class that spans a plurality of input buffers. The packet transfer device according to claim 1, wherein 5. A plurality of input buffers for temporarily storing input packets, control means for controlling these input buffers, and at least one output port for transferring packets output from each of the input buffers. In the next phase, each of the input buffers directs the input buffer from the storage means to the output port in response to an instruction from the control means. A packet to be output by the selection unit, and an output unit that outputs the packet selected by the selection unit to the output port, the control unit including the selection unit in the entire plurality of input buffers. The output status of the packet selected by the means is grasped, and based on this output status, a new packet is selected and the plurality of input packets are selected. A packet transfer device characterized by instructing a power buffer. 6. The selection means of each of the input buffers selects a packet to be output from the storage means so that packet transfer is fair among the virtual connections to which each packet belongs. Item 5. The packet transfer device according to item 5. 7. A buffer for temporarily storing an input packet, control means for controlling the buffer, and at least one for transferring the packet output from the buffer.
A packet transfer device having one output port, wherein the control means divides and manages the packets accumulated in the buffer into a plurality of sets, and the packet input to the buffer belongs to each packet. Distribution means for allocating to any one of the plurality of sets so as to be fair among the flows, and directing packets belonging to one set of the plurality of sets managed by the management means to the output port Instruction means for instructing the buffer to output
A packet transfer device comprising: 8. The allocating means determines the packet input to the buffer based on identification information of a flow to which the packet belongs, and at least one of a weight defined for each flow and an input packet length. 8. The packet transfer apparatus according to claim 7, wherein the packet transfer apparatus allocates the packet to any one of the plurality of sets. 9. A plurality of buffers for temporarily accumulating input packets are connected in series, and a buffer connected to a front stage is directed toward a buffer connected to a rear stage,
A packet transfer device for outputting a packet in accordance with a packet output / prohibition state determined according to a packet accumulation state inside the latter-stage buffer, wherein the former-stage buffer is capable of outputting the packet to the latter-stage buffer. A packet transfer apparatus comprising means for monitoring the storage status of a buffer connected to the preceding stage when a packet is first input to the preceding buffer after changing to the output prohibited state. 10. The packet transfer apparatus according to claim 9, further comprising means for determining that the buffer at the preceding stage is in a congestion state according to the monitored storage status. 11. The packet transfer apparatus according to claim 9, further comprising means for discarding an input packet according to the monitored storage status. 12. A packet transfer device comprising: at least one buffer for temporarily storing an input packet; and control means for controlling transfer of the packet in the buffer, wherein the control means is the buffer. And a packet transfer instruction to the buffer based on a history of packet transfer instructions to the buffer and a storage status of the packet in the buffer. 13. The control means also keeps a history of the transfer instructions from when the buffer notifies the control means of a packet accumulation state until a corresponding packet transfer instruction acts on the buffer. And the number of packet transfer instructions acting on the buffer is determined, and based on the determined number of transfer instructions, the storage status of the packets in the buffer is corrected, and the corrected storage status of the packets is calculated. 13. The packet transfer device according to claim 12, wherein a packet transfer instruction is issued to said buffer. 14. The control means stores the accumulation status of packets in the buffer as a history, and after the buffer notifies the control means of the accumulation status of packets, a transfer instruction of a packet corresponding thereto is issued to the buffer. Before the action is taken, the transfer status of the buffer is judged based on the transfer instruction history and the storage status history, and the packet storage status of the buffer is corrected based on the judged transfer status. 13. The packet transfer device according to claim 12, wherein a packet transfer instruction is issued to the buffer based on the corrected packet storage status.